| 30-Seconds Down Counter I. Objectives 1. To make a Sequential Logic Circuit using Altera Max+Plus II 2.

To know how to operate Altera Max+Plus II 3. To apply the knowledge of making a sequential circuit in Max+Plus II 4. Making a 3-bit Synchronous Down Counter using J-K Flip-flops

II.

Basic Theory Combinational logic circuits have the property that the output of a logic block is only a

function of the current input values, assuming that enough time has elapsed for the logic gates to settle. Yet virtually all useful systems require storage of state information, leading to another class of circuits called sequential logic circuits. In these circuits, the output not only depends upon the current values of the inputs, but also upon preceding input values. In other words, a sequential circuit remembers some of the past history of the systemit has memory. Figure 7.1 shows a block diagram of a generic finite state machine (FSM) that consists of combinational logic and registers that hold the system state. The system depicted here belongs to the class of synchronous sequential systems, in which all registers are under control of a single global clock. The outputs of the FSM are a function of the current Inputs and the Current State. The Next State is determined based on the Current State and the current Inputs and is fed to the inputs of registers. On the rising edge of the clock, the Next State bits are copied to the outputs of the registers (after some propagation delay), and a new cycle begins. The register then ignores changes in the input signals until the next rising edge. In general, registers can be positive edge-triggered (where the input data is copied on the positive edge) or negative edge-triggered (where the input data is copied on the negative edge of the clock, as is indicated by a small circle at the clock input).

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In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the past history of its inputs. This is in contrast to combinational logic, whose output is a function of only the present input. That is, sequential logic has state (memory) while combinational logic does not. Or, in other words, sequential logic is combinational logic with memory. Sequential logic is therefore used to construct some types of computer memory, other types of delay and storage elements, and finite state machines. Most practical computer circuits are a mixture of combinational and sequential logic. There are two types of finite state machine that can be built from sequential logic circuits:

Moore machine: the output depends only on the internal state. (Since the internal state only changes on a clock edge, the output only changes on a clock edge too). Mealy machine: the output depends not only on the internal state, but also on the inputs.

Depending on regulations of functioning, digital circuits are divided into synchronous and asynchronous. In accordance with this, behavior of devices obeys synchronous or asynchronous logic.

| 30-Seconds Down Counter Two Main Types of Sequential Circuits There are two types of sequential circuit, synchronous and asynchronous: Synchronous types use pulsed or level inputs and a clock input to drive the circuit (with restrictions on pulse width and circuit propagation).

Asynchronous sequential circuits do not use a clock signal as synchronous circuits do. Instead the circuit is driven by the pulses of the inputs.

A pulsed output (as used in the block diagrams above) is an output that lasts for the duration of a particular input pulse but can be less in some cases. For the clocked sequential circuits, the output pulse is the same duration as the clock pulse.

| 30-Seconds Down Counter A level output refers to an output that changes state at the start of an input pulse or clock pulse and remains in that state until the next input or clock pulse. An important thing to note with sequential circuits is that duration of the activating pulse should be low enough so that the secondary inputs do not change state in same activating pulse. Allowing the clock pulse to be too long would result in incorrect circuit function, as there will be two different secondary input values for one clock cycle and therefore lead to potentially two state changes in one clock. It would be beneficial to have our storage elements to be edge triggered, as this would mean that the clock pulse can be as long as we would like it to be and the circuit would behave in the same way. This is why flip-flops are used as they are edge triggered storage devices. III. Equipment Used a. b. c. Altera Max+Plus II Pen & Paper Laptop (Personal Computer)

IV.

Procedure a. b. c. d. e. f. g. h. i. Follow the Truth Table shown in Figure A Place 4 J-K Flip-Flops on the graphic screen Connect the J & K according to the Karnaugh-Mapping results Connect all clocks to one input Connect QA ,QB ,QC, and QD to the 7448 Binary-to-7-Segment IC Compile the schematic diagram Check waveform in the waveform editor Simulate the Waveform Editor. Observe results

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Truth Table:
Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QA 1 0 0 0 0 0 0 0 0 1 X X X X X X QB 0 0 0 0 0 1 1 1 1 0 X X X X X X QC 0 0 0 1 1 0 0 1 1 0 X X X X X X QD 1 0 1 0 1 0 1 0 1 0 X X X X X X Jaka 1X 0X 0X 0X 0X 0X 0X 0X X1 X0 X X X X X X Jbkb 0X 0X 0X 0X X1 X0 X0 X0 1X 0X X X X X X X Jckc 0X 0X X1 X0 1X 0X X1 X0 1X 0X X X X X X X jdkd 1X X1 1X X1 1X X1 1X X1 1X X1 X X X X X X

00 01 11 10 00 01 11 10 X X X X X X X X 1 = 00 01 11 10

00 01 11 10 X X X 1 X X X X X X X X X X X =

00 01 11 10 00 01 11 10 X X 1 X X X X X X X X 00 01 11 10

00 01 11 10 X 1 X X X X = X X X X X

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00 01 11 10 00 01 11 10 1 X 1 X X X X X X X X X 00 01 11 10

00 01 11 10 X X X X X X X X X X 1 1 X X

= +

00 01 11 10 00 01 11 10 1 1 X 1 X X X X X X X X 1 1 X X 00 01 11 10

00 01 11 10 X X X X 1 1 X 1 1 1 X X X X X X

= +

= +

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| 30-Seconds Down Counter VI. Results When compiling the circuit, Altera Max+Plus II does not detect any errors on the circuit formed in Figure B.

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Figure C

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After compiling, the circuit was simulated using the waveform editor of Alteras Max+Plus II. Figure C shows the waves that were produced by the output of the circuit. Logic 1 means that the light in the 7-segment display is ON, while Logic 0 means that it is OFF. Because the waveform editor only shows up to 1000ns, the numbers from 3 back to 0 and the loop were not shown. VII. Applications A 7-0 3-bit Down Counter can be utilized in many applications. One such application would be a 9-second wait time for an auto-lock mechanism. When opening a security door, this counter can be applied to make a 7-second delay time, until the opening mechanism kicks in, for safety reasons. This can also be applied when closing that security door. The same design may be employed to a night light after detecting a passerby. There would be a 9-second wait time until the light would automatically turn off and would only turn on again if its sensor has detected another passerby. It would help the owner to conserve and lessen his electricity bill. The counter would start counting down from 7 to 0 after the passerby cannot be detected by the sensor. VIII. Observation The group had observed that the Altera Max+Plus II, can help the students in making their prototype circuits. The Software can make it easier for the students to try out the different possible connections and explore more about Logic Circuits. Altera Max+Plus II, can also simulate the circuits by showing its output waveforms in the form of square waves. The output waveforms are to show the Logic 1s & 0s. The group also observed that there is still more things to be learned from Logic Circuits and the software. It is recommended that there should be more time in teaching the students on how to use the software for better efficiency. Though this is only a 7-0 down counter, that is not the only counter available and many others can be made.

| 30-Seconds Down Counter IX. Conclusion By this experiment the group has gained the knowledge on how to use the Altera Max+Plus II Software and simulate potential circuits. With the knowledge of Logic Circuits, the group made a 7-0 3-bit down sequential counter. Due to specific ICs not allowed in the experiment, the group chose to make the circuit using the J-K Flip Flops. The group had a difficult time initially when there was lack of knowledge of the said project and the use of the software. The group also had to compute manually for the outputs of the circuit and brainstorm on how it would play out. But in time, the group was able to find out the problems in the simulation and was able to correct them. With teamwork and hard-work, the group had achieved their objectives.