A New Duty-Cycle-Shifted PWM Control Scheme for Half-Bridge DC-DC Converters to Achieve Zero-Voltage-Switching 1

Hong Mao, Jaber A. Abu-Qahouq, Songquan Deng, and Issa Batarseh

School of Electrical Engineering and Computer Science University of Central Florida Orlando, Florida 32816, USA batarseh@mail.ucf.edu Abstract Asymmetric control scheme is an approach to achieve ZVS for half-bridge isolated DC-DC converter. However, it is not suited for wide-range input voltage due to the uneven voltage and current components stresses. This paper presents a new duty-cycle-shifted PWM control scheme for half-bridge isolated dc-dc converters to achieve ZVS operation without asymmetric penalties and without adding additional components. Because the duty cycle width is kept identical for both switches, the asymmetric current and voltage stresses problem is eliminated. The principles of operation and key features are illustrated. Experimental results verify that higher efficiency is achieved with the proposed duty-cycleshifted control method, especially at higher switching frequency. Keywords- DC-DC; Converte; Half-Bridge; SoftSwitching; Symmetric Control; Asymmetric Control; DutyCycle-Shifted PWM Control; Low Voltage; High Current; Modulation Scheme. I. INTRODUCTION With the increasing demand for higher power density in dc-dc conversion with much improved dynamic performance, converter switching frequency continues to increase to reduce the size and cost of passive components. However, with increased switching frequency, soft switching operation becomes more desirable to reduce the increased switching losses [1-10]. For isolated dc-dc converters, the phase-shifted full-bridge [1,2] and forward active-clamp topologies [3,4] are desirable soft-switching techniques, which are widely used in industry. Half-bridge topology has relatively simple structure and is a popular approach for medium power level applications. There are two conventional control schemes used in halfbridge topology. One is the conventional symmetric PWM control; the other is the asymmetric (complimentary) control [7-10] where two driving signals are complimentarily generated. For the symmetric control, both primary switches operate at hard switching condition, which limits the increase of switching frequency.
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The asymmetric (complimentary) control employs the leakage inductance and output inductor current to achieve ZVS for both the high-side switch and the low-side switch. Unfortunately, the asymmetric scheme leads to asymmetric disadvantages because high-side switch and low-side switch operate at different width of duty cycles [7-10]. The voltages across the legs capacitors are not identical, as a result, the current stresses on the primary-side switches as well as the voltage and current stresses on the secondary-side rectifiers are not identical [9]. Therefore, higher voltage rate rectifiers should be used which degrades the rectification efficiency due to higher voltage drop and higher reverse recovery losses. Moreover, because the DC voltages gain of the converter is nonlinear, for the same input voltage deviation, larger duty cycle range is needed, resulting in further degrading in the converter performance. Therefore, complimentary control is not suited for wide input voltage range applications such as 300V~400V input frontend dc-dc converters and 36V~75V input Telecom modules. To reduce the duty cycle variation range and voltage stresses applied to rectifiers, an asymmetric winding structure is proposed in [9], resulting in lower voltage rate rectifiers can be used to improve the efficiency. However, the current stresses through rectifiers and filter inductors are still uneven, and the output current has jump ripple due to asymmetric power delivery [9]. In this paper, a new control scheme is proposed to be known as duty-cycle shifted PWM control and to be applied to the half-bridge to achieve ZVS for one of the switches without adding extra components and without adding asymmetric penalties of complementary control. The concept of this new control scheme is shifting one of the two-channel symmetric PWM driving signals close to the other, while keeping the pulse-width-modulation (PWM) control mode. As a result, ZVS may be achieved because one switch turns on just after the other switch is turned off. Moreover, because the width of the two switches duty cycles is kept equal, all corresponding components work at the conditions with even stresses as the case in the symmetric control scheme. Next section describes the basic principle of operation of the new control scheme. Section III presents a comparison between the proposed control scheme and the conventional

US Patent Pending.

0-7803-7768-0/03/$17.00 (C) 2003 IEEE

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control scheme. In Section IV, the experimental work and results are presented. The conclusion is given in Section V. II. PROPOSED SCHEME AND PRINCIPLE OF OPERATION A. Proposed Duty-Cycle Shifted Scheme Figure 1 shows the half-bridge dc-dc converter with current doubler rectifier. The ideal waveforms for the symmetric PWM control is sketched in Figure 2(a), where Lk, is the leakage inductance; ip, iM are the transformer primary input and magnetizing currents, respectively; and iD1 is the forward current through rectifier diode D1. Besides the hard switching, conventional symmetric PWM control has leakageinductance related disadvantages. During off-time period when both switches are off, energy stored in the transformer leakage inductance may be recycled to primary DC bus through body diodes of MOSFETs. However, because of reverse recovery current of body diodes, the oscillation between the transformer leakage inductance and the MOSFET junction capacitance is significant on the primary side. To suppress the ringing, traditionally, snubber circuits are necessarily added but the losses dissipated in the snubber become dramatically large, especially at high input current and high switching frequency. Figure 2(b) shows the key waveforms of the proposed duty-cycle-shifted control. Based on symmetric duty cycle, S2 driving signal Vgs2 is shifted left close to the driving signal of S1. When S1 is turned off, the leakage inductor current and reflected inductor current charge or discharge junction capacitors. After the voltage across drain-source of S2 drops to zero, the body diode of S2 conducts to carry current. During the body diode conduction period, S2 may be turned on with zero-voltage switching. No ringing occurs during the transition period.
S2
A

Mode 2 ( t1 < t < t2 ): S1 is turned off at t = t1 , causing the primary current ip to charge C1 and discharge C2. During the interval, the reflected secondary inductor current dominates the primary current ip. Thus, C2 may be discharged to zero at wide load range, which provides wide ZVS range for S2. Mode 3 ( t2 < t < t3 ): When the voltage across C2 is discharged to zero at t = t2 , the body diode of S2 conducts to carry the current, which provides ZVS condition for switch S2. During this period, leakage inductance is reset and secondary current i1 and i2 freewheel through D1 and D2, respectively.
V gs1 V gs2 V AB ip iM iD 1 t

(a) Conventional Symmetric Control

Vgs1 Vgs2 VAB iP iM

D1 L1
B

LK

i1 i2 D2

L2

S1

Figure 1: Half-bridge Current-Doubler DC-DC Converter B. Operation Modes Analysis The half-bridge converter with the duty-cycle shifted PWM control operation can be described by six operation modes as shown in Figure 3 as follows: Mode 1( t < t1 ): Initially, S1 is conducting, and the input power is delivered to the output. L1 is charged and L2 freewheels (discharges) through D2.

iD1
t1 t2 t3 t4 t5 t6

(b) Proposed Duty-Cycle-Shifted Control Figure 2: Waveforms of the Half-Bridge Converter

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S2

C2 i1 i2

D1

S2

C2 i1 i2

D1

S1

C1

D2

S1

C1

D2

<Mode 1>

<Mode 5>
D1

S2

C2 i1 i2

S2

C2 i1 i2

D1

S1

C1

D2

S1

C1

D2

<Mode 2> <Mode 6>

S2 C2 i1 i2 S1 C1 D2 D1
Figure 3: Operation Modes

<Mode 3>
D1 i1 i2

S2

C2

Mode 4 ( t3 < t < t4 ): S2 is turned on with ZVS at t = t3 ; the primary current decreases to zero and then goes negative. When the negative peak current goes up to reflected L2 current, the diode D2 is blocked and the converter starts to deliver power to the output. The inductor L2 is charged and inductor L1 current keeps freewheeling. Mode 5 ( t4 < t < t5 ): S2 is turned off at t = t4 , causing the primary current ip to charge C1 and discharge C2. When the secondary D1 and D2 start to freewheel, leakage inductance and junction capacitance oscillate on the primary side. During the interval, body diodes might be involved, which makes the ringing worse and results in reverse recovery losses (The ringing waveform is not shown in Figure 2). Mode 6 ( t5 < t < t6 ): The oscillation comes to the end with the identical voltage across both S1 and S2. On the secondary side, L1 and L2 keep freewheeling. At t = t6 , S1 is turned on again going back to Mode 1.

C. PWM Modulation Schemes

S1 C1 D2

<Mode 4>

Figure 4 shows a modulation approach for the realization of duty-cycle-shifted PWM control. Where, Vsaw is the saw carrier waveform for modulation, Vc and Vc is control voltages derived from the front voltage or current controller. By modulating Vc and Vc, driving signals for S1 and S2 can

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be generated, respectively. Because the falling time of saw waveform is small, the falling edge of S1 is always close to the rising edge of S2, which guarantees the ZVS for S2. This modulation method differs from the conventional PWM method for the fact that the direction of variation of the two duty cycles is opposite as shown in Figure 4 by the arrows on the driving signals waveforms. In other words, since Vc and Vc are symmetrically centered around zero, the duty cycle of S1 is regulated by moving its rising edge left and right, while the duty cycle of S2 is regulated by moving its falling edge right and left, keeping S1 and S2 with the same duty cycle. Figure 5 shows another modulation approach for the realization of duty-cycle shifted PWM control. Vc is the control voltage derived from the front voltage or current controller and Vm is the triangular modulation waveform between zero and Vpeak. The signal V1 is generated by comparing Vc to Vm and the signals V2 and V3 are complementary digital signals with 50% duty cycle, which are synchronous with triangular modulation waveform. Using V1, V2 and V3, switches drive signals Vgs1 and Vgs2 can be generated by performing the digital AND operation between V1 and V2, and between V1 and V3, respectively. It should be noted that the triangular modulation waveform Vm can be easily generated from signal V2 (or V3) by integration. III. COMPARISON WITH CONVENTIONAL HALFBRIDGE TOPOLOGIES Comparing the proposed control scheme with the conventional symmetric control, it is clear that the switch voltage and current stresses are the same in the primary side. Although the voltage waveform applied to the transformer is different, the voltage-second value and magnetizing B-H loop of transformer are identical. The peak and rms values of input and output currents flowing through the transformer are also the same for both schemes. Hence, the duty-cycle-shifted control makes no difference in the characteristics and design of the isolation transformer compared to the conventional scheme. On the secondary side, as shown in Figure 2, even though the currents through rectifiers have different waveforms in the two schemes, the peak and rms values of the waveforms are equal. Moreover, the inductors voltagesecond value and current peak and rms values are the same for both schemes. Therefore, the voltage and current stresses for the secondaryside switches and inductors are the same for both schemes. Consequently, there is no penalty with the change of control scheme from conventional to the proposed duty-cycle-shifted scheme for the components selection and design. It can be shown that, in the proposed duty-cycle-shifted control scheme, ZVS is achieved for one of the two switches without adding additional components and without causing asymmetric voltage and current stresses problem of the asymmetric controlled half bridge. Because switching losses and transformer leakage-inductance-related losses are reduced, higher efficiency is expected with the new control method.

The manner ZVS is achieved for S2 is similar with that of leading-leg switches in full bridge [1,2], therefore, wide ZVS range operation is expected for S2.
Vc

Vgs1

+ - Vc Vsaw

Vgs2

(a) Modulation Circuits Vsaw

Vc - Vc Vgs1 Vgs2
(b) Key waveforms Figure 4: PWM Modulation Scheme I
V peak Vm Vc
0

V1 V2

V3 Vgs1=V 1 V 2 Vgs2=V 1 V 3

Figure 5: PWM Modulation Scheme II IV. EXPERIMENTAL VERIFICATION An experimental prototype with 3.3V/25A output and 36V~75V input voltage range was built in laboratory to evaluate the proposed control method. Considering the lowvoltage application, synchronous rectifiers are used instead of the rectifier diodes. For the experimental prototype, IRFS59N10D is used for switch S1 and S2, and Si4420DY is used for synchronous rectifiers. For comparison purpose, symmetric control and the proposed duty-cycle shifted control are applied to the same power stage, respectively. For duty-cycle shifted control, the driving signals are generated using the modulation circuit described in Figure 4, and considering that switch S2 is turned on at zero voltage, an

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extra capacitor is paralleled with S2 to reduce the turn-off losses. RC snubber is paralleled with S1 to damp the oscillation between leakage inductance and capacitance when S2 is turned off. For symmetric control scheme, RC snubbers are used in parallel with S1 and S2, respectively.

Figure 6 shows the experimental waveforms of gate signals of switch S1 and S2 for duty-cycle-shifted control scheme. Figures 7 shows the zero-voltage-switching waveforms of switch S2. Figure 8 shows the transformer primary voltage and current at full load with 48V input voltage. It can be observed that the ringing is reduced for duty-cycle shifted control. Figures 9, 10, 11 and 12 compare the efficiency of two control schemes at 100kHz, 200kHz, 300kHz and 400kHz, respectively. It is clear that the improvement in efficiency increases with the increase of the switching frequency, and at 400kHz, efficiency improvement is up to 1.6%. This is because switching losses and transformer leakage inductance related losses are positively proportional to the switching frequency.

Figure 6. Gate signals of S1, S2

Figure 7. Zero-voltage-switching of S2

Figure 9: Efficiency Comparison at 100KHz

(a) Conventional symmetric control

(b) Duty-cycle-shifted control Figure 8. Transformer Primary Voltage and Current

Figure 10: Efficiency Comparison at 200KHz

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symmetric PWM control. Better efficiency improvement is expected at higher switching frequency. REFERENCES
[1] W. Chen, F.C. Lee, M.M. Jovanovic, and J.A. Sabate, A comparative study of class of full bridge zero-voltageswitched PWM converters IEEE Applied Power Electronics conference Proceedings, 1995, pp.893~899. [2] R. Redl, N. O. Sokal, L Balogh, A novel soft-switching fullbridge converter: analysis, design considerations, and experimental results at 1.5 kW, 100kHz, IEEE Power Electronics Specialists Conference Records, 1990, pp.162~172. [3] arvelis, G.A., Manolarou, M.D.; Malatestas, P.; Manias, S.N, Analysis and design of non-dissipative active clamp for forward converters, Electric Power Applications, IEE Proceedings , Volume: 148 Issue: 5, Sept. 2001 Page(s): 419 424 [4] Ji, H.K, Kim, H.J. Active clamp forward converter with MOSFET synchronous rectification, IEEE Power Electronics Specialists Conference, 1994, pp. 895 901. [5] Cobos, J.A.; Garcia, O.; Uceda, J.; Sebastian, J.; de la Cruz, E., Comparison of high efficiency low output voltage forward topologies, Power Electronics Specialists Conference, PESC '94 Record., 25th Annual IEEE , 1994 , pp. 887 894 [6] Sebastian, J.; Fernandez, A.; Villegas, P.J.; Hernando, M.M.; Lopera, J.M, Improved active input current shapers for converters with symmetrically driven transformer, IEEE Transactions on Industry Applications, Volume: 37 Issue:2, March-April 2001 pp: 592 600. [7] Sebastian, J.; Cobos, J.A.; Garcia, O.; Uceda, J.,An overall study of the half-bridge complementary-control DC-to-DC converter, Power Electronics Specialists Conference, 1995. pp.1229 1235. [8] Miftakhutdinov, R.; Nemchinov, A.; Meleshin, V.; Fraidlin, S., Modified asymmetrical ZVS half-bridge DC-DC converter, Applied Power Electronics Conference and Exposition, 1999. APEC '99, pp.567 574. [9] Weiyun Chen; Peng Xu; Lee, F.C., The optimization of asymmetric half bridge converter, Applied Power Electronics Conference proceedings, 2001, pp. 703 707. [10] P.Imbertson and N. Mohan, Asymmetrical duty cycle permits zero switching loss in PWM circuits with no conduction loss penalty, IEEE Transaction on Power Electronics, Vol.29, No.1, pp.121-125, 1993.

Figure 11: Efficiency Comparison at 300KHz

Figure 12: Efficiency Comparison at 400KHz V. CONCLUSION A simple and effective PWM control method known as duty-cycle-shifted control method was proposed to reduce switching losses and transformer-leakage-inductance-related losses in the half-bridge DC-DC converter topology. Using the proposed scheme, by shifting one of the symmetric PWM driving signals, Zero-Voltage-Switching (ZVS) is achieved for one of the switches without adding extra components and without adding asymmetric penalties of the complementary duty cycle control. This control concept reduces the switching losses and transformer leakage-inductance-related losses. These losses significantly degrade the efficiency, especially when operating in high switching frequencies. Moreover, two modulation schemes to generate the required driving signals were also presented. Experimental results showed that the proposed control scheme improves the efficiency up to 1.6% at 400kHz switching frequency when compared to the conventional

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