Silos

Users Manual

Silvaco, Inc. 4701 Patrick Henry Drive, Bldg. 2 Santa Clara, CA 95054 Phone (408) 567-1000 Web http://www.silvaco.com

September 11, 2013

Silos Users Manual Copyright 2013 Silvaco, Inc. 4701 Patrick Henry Drive, Bldg. 2 Santa Clara, CA 95054 Phone: Web: (408) 567-1000 http://www.silvaco.com

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The information contained in this document is subject to change without notice. Silvaco, Inc. MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. Silvaco, Inc. shall not be liable for errors contained herein, or for incidental or consequential damages in connection with the furnishing, performance, or use of this material. This document contains proprietary information, which is protected by copyright. All rights are reserved. No part of this document may be photocopied, reproduced, or translated into another language without the prior written consent of Silvaco, Inc.. ACCUCELL, ACCUCORE, ACCUMODEL, ACCUTEST, ATHENA, ATHENA 1D, ATLAS, BLAZE, C-INTERPRETER, CATALYSTAD, CATALYSTDA, CELEBRITY, CELEBRITY C++, CLARITYRLC, CLEVER, CLEVER INTERCONNECT, DECKBUILD, DEVEDIT, DEVEDIT3D, DEVICE3D, DEVICE3D BUNDLE, DISCOVERY, EDIF WRITER, ELITE, EXACT, EXPERT, EXPERT200, EXPERTVIEWS, FERRO, GATEWAY, GATEWAY200, GIGA, GIGA3D, GUARDIAN, GUARDIAN DRC, GUARDIAN LVS, GUARDIAN NET, HARMONY, HIPEX, HIPEX C, HIPEX NET, HIPEX RC, HYPERFAULT, INTERCONNECT MODELING, LASER, LED, LED3D, LISA, LUMINOUS, LUMINOUS3D, MAGNETIC, MAGNETIC3D, MASKVIEWS, MC ETCH & DEPO, MC DEVICE, MC IMPLANT, MERCURY, MIXEDMODE, MIXEDMODE3D, MODELLIB, NOISE, OLED, OPTOLITH, ORGANIC BUNDLE, ORGANIC DISPLAY, ORGANIC SOLAR, OTFT, PDK FLOW, QUANTUM, QUANTUM3D, QUEST, REALTIMEDRC, REM 2D, REM 3D, S-PISCES, S-PISCES BUNDLE, SSUPREM3, SSUPREM4, SSUPREM4 BUNDLE, SCOUT, SDDL, SFLM, SIC, SILOS, SIMULATION STANDARD, SMARTLIB, SMARTSPICE, SMARTSPICE API, SMARTSPICE DEBUGGER, SMARTSPICE RF MULTICORE, SMARTSPICE RUBBERBAND, SMARTSPICE RF, SMARTSPICE200, SMARTVIEW, SOLVERLIB, SPAYN, SPDB, SPIDER, SPRINT, STELLAR, TCAD DRIVEN CAD, TCAD OMNI, TCAD & EDA OMNI UTILITY, TFT, TFT BUNDLE, TFT3D, TFT3D BUNDLE THERMAL3D, TONYPLOT, TONYPLOT3D, UTMOST III, UTMOST III BIPOLAR, UTMOST III DIODE, UTMOST III GAAS, UTMOST III HBT, UTMOST III JFET, UTMOST III MOS, UTMOST III MULTICORE, UNIVERSAL TOKEN, UNIVERSAL UTILITY TOKEN, UTMOST III SOI, UTMOST III TFT, UTMOST III VBIC, UTMOST IV, UTMOST IV FIT, UTMOST IV FULL PACKAGE, UTMOST IV MEASURE, UTMOST IV OPTIMIZATION, VCSEL, VERILOG-A, VICTORY, VICTORY CELL, VICTORY DEVICE, VICTORY DEVICE BUNDLE, VICTORY DEVICE SINGLE EVENT EFFECTS, VICTORY PROCESS, VICTORY PROCESS ADVANCED DIFFUSION & OXIDATION, VICTORY PROCESS BUNDLE, VICTORY PROCESS MONTE CARLO IMPLANT, VICTORY PROCESS PHYSICAL ETCH & DEPOSIT, VICTORY STRESS, VIRTUAL WAFER FAB, VWF, VWF AUTOMATION TOOLS, VWF INTERACTIVE TOOLS, and VYPER are trademarks of Silvaco, Inc. All other trademarks mentioned in this manual are the property of their respective owners. Copyright 1984 - 2013, Silvaco, Inc.

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How to Read this Manual

Style Conventions Font Style/Convention Description This represents a list of items or terms. Example 1. 2. 3. This represents a set of directions to perform an action. Bullet A Bullet B Bullet C

To open a door: 1. Unlock the door by inserting the key into keyhole. 2. Turn key counter-clockwise. 3. Pull out the key from the keyhole. 4. Grab the doorknob and turn clockwise and pull.

This represents a sequence of menu options and GUI buttons to perform an action. This represents the commands, parameters, and variables syntax. Schoolbook Schoolbook This represents the menu options and buttons in the GUI. This represents the equations. This represents the additional important information.

FileOpen

Courier

HAPPY BIRTHDAY

New Bold

Century

File abc=xyz

New Century Italics Note:

Note: Make sure you save often while running an experiment. ATHENA, ATLAS, EXPERT, GATEWAY, HIPEX, SMARTSPICE, STELLAR, and UTMOST.

New Century SchoolBook in Small Caps

This represents the names of the products.

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Table of Contents
Chapter 1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1: Silos Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2: Silos Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3: Platforms Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4: Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-1 1-1 1-2

Chapter 2: Quick Start Tutorial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1: Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2: Starting Silos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3: Opening the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4: Running the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5: Opening the Explorer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6: Opening the Waveform Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7: Accessing On-line Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8: Exiting Silos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-1 2-2 2-3 2-4 2-6 2-7 2-7

Chapter 3: Tutorial Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2: Tutorial Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.3: Tutorial Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.4: Tutorial 1: Creating a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.5: Tutorial 2: Simulating a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.5.1: Messages in the Output Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.5.2: Using the Explorer to Display Signals as Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.5.3: Viewing Source code Variables and Expressions as Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.5.4: Using Title Tips. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.5.5: Rearranging the Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.5.6: Setting Waveform Colors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.5.7: Expanding and Collapsing a Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.5.8: Displaying Vector Contents using Symbolic Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.5.9: Creating an Annotated Timeline for the Waveform Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.5.10: Groups, Buses, Vectors and Signals in the Analyzer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.5.11: Creating Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.5.12: Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.5.13: Displaying a Logic Condition as a Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.5.14: Timing Markers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.5.15: Scan-to-Change, Scan-to-Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.5.16: Zoom-Buttons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 3.5.17: Scrollbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 3.5.18: Bookmark, Timescale, Goto Timepoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3.5.19: Scrolling the Waveform Window (for systems equipped with wheel mice) . . . . . . . . . . . . . . . . . . . . . 3-30
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3.5.20: Viewing Simulation Results in HDL Code using Data Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.21: Exiting Silos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6: Tutorial 3: Analog and Digital Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1: Opening the Project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2: Viewing Analog Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3: Expanding Analog Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.4: Changing Display Type of Analog Waveforms between PWL and Step . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.5: Creating Analog Overlays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.6: Expanding an Analog Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.7: Identifying Overlay Signals Using Trace Colors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.8: Changing the Y- Axis from Variable to Fixed Scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.9: Performing Mathematical Operations on Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.10: Displaying Analog Signals as Digital Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.11: Displaying a Group of Analog Signals as a Digital Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.12: Exiting Silos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7: Tutorial 4: Debugging Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1: Trace Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2: Visual Debug using Behavioral Traceback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.3: Single Stepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.4: Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8: Tutorial 5: Code Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1: Generating Line Coverage Reports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2: Generating Operator Coverage Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.3: Merging Code Coverage Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.4: Exiting Silos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9: Tutorial 6: Gate Level Debugging Using Trace Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.1: Trace Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.2: Exiting Silos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10: Tutorial 7: Error Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.1: Exiting Silos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-30 3-32 3-33 3-33 3-34 3-34 3-36 3-39 3-39 3-40 3-41 3-44 3-45 3-46 3-46 3-47 3-47 3-49 3-53 3-57 3-59 3-59 3-62 3-65 3-67 3-68 3-68 3-69 3-70 3-72

Chapter 4: Graphical User Interface Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1: GUI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1: Dockable/Detachable Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.2: Context Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.3: Dialog Box Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.4: Interrupting Silos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2: The Menu Bar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3: The Toolbars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3.1: Tools Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3.2: Analyzer Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.4: The Explorer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.5: Explorer Design Hierarchy Tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.5.1: Copy Scope Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.5.2: Select Scope Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.5.3: Instance Name Filter Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

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4.5.4: Go to <module definition/instance> Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.5: Module Properties Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6: Explorer Port and Variable List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1: Go To Definition Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2: Add Signals to Analyzer Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.3: Name Filter Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.4: Regular Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.5: Sort by Name or Type Menu Selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7: The Data Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8: Data Analyzer Signal List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.1: Trace Inputs Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.2: Go to Definition Menu Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.3: Signal Groups Menu Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.4: Display Group as Analog Overlay Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.5: Display Group as Digital Bus Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.6: Do Not Display Group Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.7: Set Radix Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.8: Change Signal Color Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.9: Set Analog Display Options Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.10: Expand All Analog Signals Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.11: Collapse All Analog Signals Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.12: Display as Digital Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.13: Add Menu Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.14: Reverse Bit Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.15: Delete Item/s Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.16: Move Item Up Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.17: Move Item Down Menu Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.18: Clear Signal List Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9: Data Analyzer Waveform Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9.1: Data Analyzer X-Axis Area and Goto Timepoint Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9.2: Pan T1, Pan T2, and Pan Last View Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9.3: Timescale Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9.4: Add Bookmark Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9.5: Delete Bookmark Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10: The Output Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10.1: Copy Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10.2: Select All Menu Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11: Source Code Editor Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.1: Source Editor Debug Tab Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.2: Undo Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.3: Redo Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.4: Cut Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.5: Copy Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.6: Paste Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.7: Open File Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.8: Insert/Remove Breakpoint Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.9: Data Tips Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.10: Data Tip Radix Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Silvaco, Inc.

4-12 4-13 4-14 4-16 4-16 4-16 4-17 4-18 4-19 4-19 4-21 4-21 4-21 4-22 4-22 4-22 4-22 4-23 4-23 4-23 4-23 4-23 4-23 4-24 4-24 4-24 4-24 4-24 4-24 4-25 4-26 4-26 4-26 4-26 4-27 4-27 4-27 4-28 4-28 4-28 4-28 4-28 4-28 4-29 4-29 4-29 4-29 4-29
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Silos Users Manual

4.11.11: Upscope to <module name> Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.12: Downscope to <instance name> Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.13: Current Module Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.14: Select Scope Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.15: Go to Definition of Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12: The Status Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13: File Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.1: New Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.2: Open Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.3: Save Menu Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.4: Save As Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.5: Save All Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.6: Close Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.7: New Project Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.8: Open Project Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.9: Save Project Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.10: Save Project As Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.11: Close Project Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.12: Import Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.13: Export Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.14: Link to Gateway Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.15: Run Lint on Project Files Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.16: Run Lint on File/s Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.17: Save Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.18: Restore Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.19: Print Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.20: Print Analyzer Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.21: Recent Files Menu Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13.22: Recent Projects Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14: Edit Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14.1: Undo Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14.2: Redo Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14.3: Cut Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14.4: Copy Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14.5: Paste Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14.6: Select All Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14.7: Find Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14.8: Find Next Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14.9: Replace Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14.10: Goto Line Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14.11: Add Spice .INCLUDE card Menu Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14.12: Add Spice .LIBRARY card Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14.13: Project Properties Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14.14: Preferences Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15: View Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15.1: Toolbars Menu Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15.2: Analyzer Menu Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15.3: Explorer Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii

4-30 4-30 4-30 4-30 4-30 4-31 4-32 4-33 4-33 4-33 4-33 4-33 4-34 4-34 4-34 4-34 4-34 4-34 4-34 4-36 4-37 4-37 4-37 4-37 4-38 4-38 4-38 4-38 4-38 4-39 4-39 4-39 4-39 4-39 4-39 4-39 4-39 4-40 4-40 4-40 4-40 4-40 4-40 4-51 4-66 4-66 4-66 4-66

Silvaco, Inc.

Table of Contents

4.15.4: Watch Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15.5: Back and Forward Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16: Analyzer Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16.1: Zoom In Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16.2: Zoom Out Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16.3: Zoom Full Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16.4: Zoom Markers Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16.5: Pan T1 Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16.6: Pan T2 Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16.7: Pan Last View Menu Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16.8: Trace Source Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16.9: Signal List Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16.10: X-Axis Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17: Debug Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17.1: Go Menu Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17.2: Break Simulation Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17.3: Step Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17.4: Finish Current Timepoint Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17.5: Load/Reload Input Files Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17.6: Reload and Go Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17.7: Restart Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17.8: Data Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17.9: Data Tip Radix Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17.10: Enable Single Step/Breakpoints Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17.11: View Breakpoints Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17.12: Insert/Remove Breakpoint Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18: Explorer Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19: Reports Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19.1: Activity Reports Menu Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19.2: Errors and Warnings Menu Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19.3: Iteration Menu Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19.4: Nonconvergence Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19.5: Nonconvergence For Gate Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19.6: Nonconvergence (Hanging) for Behavioral Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19.7: Sizes Menu Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19.8: Enable Code Coverage Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19.9: Merge Code Coverage Files Menu Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19.10: Export Code Coverage Data Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19.11: Code Coverage Line Report Menu Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19.12: Branch Coverage Report Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19.13: Code Coverage Operator Report Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19.14: Restricting Code Coverage Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20: Help Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20.1: Silos Help Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20.2: Release Notes Menu Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20.3: About Silos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-66 4-66 4-67 4-67 4-67 4-67 4-67 4-67 4-67 4-67 4-67 4-67 4-68 4-69 4-69 4-69 4-69 4-69 4-69 4-70 4-70 4-70 4-70 4-70 4-70 4-71 4-71 4-71 4-72 4-73 4-73 4-74 4-74 4-75 4-76 4-76 4-77 4-77 4-77 4-77 4-78 4-79 4-80 4-80 4-80 4-80

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Chapter 5: Advanced Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1: Programming Language Interface (PLI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1: Silos PLI Interface on the Windows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.2: PLI Interface on Linux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.3: List of Implemented PLI Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2: Standard Delay Format (SDF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.1: Example of SDF Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.3: Inputting Value Change Dump (VCD) Files for Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.4: Creating Smaller Save Files for Logic Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.4.1: Using Recirculation to Create a Constant Save File Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.4.2: Saving Selected Wires and Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.5: How to Simulate Designs that Run on Other Simulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.6: Source File Encryption Using Sencrypt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

Chapter 6: Interactive Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1: Commands Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2: Stopping Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.3: Activity Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.4: Bus Contention Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.5: Exporting Code Coverage Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.6: Exclude Code Coverage for Module Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.7: Keeping Code Coverage for Module Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.8: Merge Code Coverage Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.9: Control Parameters For Logic Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.10: Default Device Delay Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 6.11: Disk File Name Reassignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 6.12: Error Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6.13: Exclude Saving Simulation Node States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6.14: Exiting The Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.15: File Name Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.16: Keeping Simulation Node States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.17: Warning Message Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.18: Exclude Saving Module Instance Variable Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6.19: Keeping Module Instance Simulation Variable Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6.20: No Convergence Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 6.21: Narrow Storing Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6.22: Preprocessing Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.23: Probing Node States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.24: Quitting Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 6.25: Resetting Selected Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 6.26: Scope For Printing Module Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 6.27: Logic Simulation Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
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6.28: Size-Of-Data Reprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.29: Spike Summary Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.30: Storing Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.31: Strength Specification For Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.32: Symbol Modification For Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-27 6-27 6-28 6-29 6-30

Chapter 7: Linting Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.1: What Silos Lint Does . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2: Why You Need Silos Lint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.2.1: Race Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2.2: Hardware Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2.3: State Machines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.4: Design Policies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.5: Syntax and Semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.6: Design for Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.3: How to run Lint in Silos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.4: Lint Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.4.1: Lint Option Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

Appendix A: Frequently Asked Questions (FAQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Appendix B: Command Line Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1: Command Line Argument Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8

Appendix C: Example Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 Appendix D: File Extensions Used by Silos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 Appendix E: Non-Standard Verilog HDL Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
E.1: Expected Values and Stimulustable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.1.1: BNF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.1.2: Stimulustable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.1.3: Radix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.1.4: Delay Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.1.5: Memory Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.1.6: Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.1.7: I/O Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.1.8: Expected Value Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.1.9: Expected Value Error Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.1.10: Incremental Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.1.11: Changing Behavioral Stimulus to a stimulustable Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.2: Analog Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 E-1 E-1 E-2 E-2 E-3 E-3 E-4 E-5 E-6 E-6 E-7 E-8

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E.2.1: Real and Integer Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-8 E.2.2: Utility Transcendental Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9 E.2.3: Examples for Transcendental Math Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9 E.3: silos Keyword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-10 E.4: Extensions to Turn-off, Reset and Turn-on Saving of Simulation Data. . . . . . . . . . . . . . . . . . . . . . . . . . E-10 E.5: $save( ) Extension to Create a .cmm File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-10 E.6: Allowing Non-Standard Extensions to Verilog HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-11 E.6.1: Global Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-11 E.6.2: Procedural Assignment to Wires: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-11 E.6.3: Continuous Assignments to Register and Memory Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-11 E.6.4: Continuous Assignments Using Intra-assignment/non-blocking Delays . . . . . . . . . . . . . . . . . . . . . . . . E-11 E.6.5: Default State Value for UDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-11 E.6.6: UDP Additional States for High-Z on Inputs or Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-12 E.6.7: UDP Edge for High-Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-12 E.6.8: UDP Multiple Edges in a Row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-12 E.6.9: Non-Constant Specify Block Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-12 E.6.10: Parameter for Specify Block Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-13 E.6.11: Stimulustable Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-13 E.6.12: "input/output/inout" Declarations After the Variable's Declaration. . . . . . . . . . . . . . . . . . . . . . . . . . . . E-13 E.6.13: Using Registers as Module Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-13 E.6.14: Duplicate Variable Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-13 E.6.15: Parameter Used for Sizing Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-14 E.6.16: Null Statements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-14 E.6.17: Timing Checks Without Edge Specifications for Selected Variables . . . . . . . . . . . . . . . . . . . . . . . . . E-14 E.6.18: More Precision in "$timeformat" than "`timescale" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-14 E.6.19: Missing Port Connections Connected to GND for VCS Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . E-14 E.6.20: VCS Compatibility Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-14 E.7: $dumpactivity System Task Extension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-15 E.8: `uselib Compiler Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-16 E.9: System Commands Passed as Command Line Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-16

Appendix F: Message Codes for Lint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-1 Appendix G: STARC Rule Message Codes for Lint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-1 Appendix H: XML Project File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-1
H.1: XML Project File Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-1

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Chapter 1: Introduction
1.1: Silos Overview
SILOS is a simulation environment developed for use in the design and verification of electronic circuits and systems. SILOS can simulate designs at the behavioral and gate levels. It can also simulate designs modeled with the Verilog Hardware Description Language (HDL). SILOS can back annotate delays

specified using the Standard Delay Format (SDF). The IEEE Programming Language Interface (PLI) is supported.

1.2: Silos Features

During logic simulation, SILOS saves every changed event for every variable in a very compact, binary save file. The save file allows SILOS to display waveforms for any signal and to trace on any variable. The save file is random access so results are quickly displayed no matter how large the simulation. The debugging capabilities include: The mouse cursor can be held over variables and expressions in the source code to directly see their value at a time point. Drag and drop variables and expressions directly from the source file into the Data Analyzer Waveform window, or from the SILOS Explorer to the Data Analyzer window to provide easy access to the simulation results. Unlimited traceback for behavioral and gate designs quickly isolates the cause of Unknown levels. Code Coverage reporting for Line, Operator and Branch coverage display a purple dot beside any line or operator that was not executed by the testbench.

1.3: Platforms Supported

SILOS is available on Windows and Linux platforms. Please contact Silvaco for an updated list of

supported platforms.

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1.4: Technical Support

Silvaco offers technical support to customers on maintenance. The most efficient way to contact Silvaco's technical support is via the support area of the Silvaco website (www.silvaco.com). When sending problem circuits to Silvaco. Describe the tool name (e.g. SILOS). Describe the version number of the tool (e.g. 1.0.0.R). Describe the operating system (e.g. Windows XP Service Pack 2). Please send the complete design, so that it can be run to duplicate the problem, including any libraries and the .spjx file. You may want to compress the files using the zip format. Precisely describe the problem and how to run the circuit, for example: At time=200, node "top.out1" should be high instead of unknown. To run the circuit, use project "problem.spjx". Silvaco's mailing address, phone number, and fax number are: Silvaco, Inc. 4701 Patrick Henry Drive, Bldg 2 Santa Clara, CA 95054 Phone: (408) 567-1000

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Chapter 2: Quick Start Tutorial

This chapter provides an introduction to SILOS using a quick start tutorial. The Quick Start Tutorial is designed for more experienced users of simulation tools who need to quickly learn how to run SILOS.

2.1: Before You Begin

SILOS contains a number of tutorial examples. These examples are stored in the examples directory in the SILOS installation. Before beginning, please copy the SILOS examples directory from the SILOS

Installation Directory to your personal directory.

2.2: Starting Silos

On a Windows platform, SILOS can be started by double clicking on the SILOS icon in Silvaco Shortcuts on the desktop. On a Linux platform, SILOS can be started by typing silos in a command line shell.

Figure 2-1: Starting Silos

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2.3: Opening the Project

Load the quick start tutorial project by selecting the FileOpen Project menu. Then open the analog project example in the examples/tutorial/analog directory by selecting the analog.spjx file.

Figure 2-2: Open Project

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2.4: Running the Simulation

Figure 2-3: Go Button

The simulation can be started by clicking on the Go button. When the simulation end time is reached the simulation stops.

Figure 2-4: Simulation Complete

Note: SILOS will display a busy indicator in the status bar in the lower right hand corner to indicate the tool is running a simulation.

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2.5: Opening the Explorer

The Explorer can be used to examine the design hierarchy. Click on the Explorer button.

Figure 2-5: Explorer Button

Figure 2-6: The Explorer

The design hierarchy can be expanded by clicking on the blocks in the design.

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Figure 2-7: Expanded Design Hierarchy

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2.6: Opening the Waveform Viewer

You can use one of two Waveform Viewers to examine the results of the simulation. The viewer selection is controlled by the program preferences dialog EditPreferencesWaveform Viewer. Clicking on the Waveform Viewer button will start the selected viewer. The Waveform Viewer selection will affect the simulation data files created and the method for viewing these files offline. Simulation data files: The data displayed in the waveform viewer is stored in a binary file. This file will have an extension of .rawd if SMARTVIEW is selected and .sim if the Analyzer is the selected viewer. Offline viewing of waveforms: If SMARTVIEW is the selected waveform viewer, the simulation data file/s are available after the program has been closed. These files can be viewed by running SMARTVIEW and opening the desired data file/s. If the Analyzer is the selected viewer, waveforms can only be viewed interactively while the program is running. Simulation data can be viewed at a later time if the state of the simulator is saved (FileSave Simulation) prior to exiting the program. The program can be restarted and the simulation restored using FileRestore Simulation. After doing the restore, the Analyzer can be used to view the saved data from the restored simulation.

Figure 2-8: Waveform Viewer Button

Figure 2-9: The Analyzer

Click on the Zoom Full button to see the results for the entire simulation.

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Figure 2-10: Zoom Full Button

2.7: Accessing On-line Help

The complete SILOS USERS MANUAL is available as an on-line help file. This manual is also available as a PDF file in the docs subdirectory in the SILOS installation for viewing and printing.

Figure 2-11: Help Menu

To access the on-line help for SILOS: Select the Help menu.

The following are provided as on-line help files:

SILOS HELP. This help file provides the complete SILOS USERS MANUAL as an on-line help file.

Release Notes. The release notes for the product.

Many questions are answered in Appendix A: Frequently Asked Questions (FAQ).

2.8: Exiting Silos

Exit SILOS by selecting the FileExit menu selection. This concludes the Quick Start Tutorial.

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Chapter 3: Tutorial Examples

3.1: Introduction
This section contains a number of tutorials that introduce the features of SILOS. The files used for the Tutorial examples can be found in the silos/tutorial subdirectory in examples installation directory. Please note: Actions that you should do to run this tutorial are in bold. Click on means place the mouse cursor on the appropriate item and click and release on the item using the left mouse button. You can see the tool tips (text labels) for each of the buttons on the toolbars for SILOS by placing the mouse cursor over a button for a few seconds until the text label for the button appears. Then move the mouse along the toolbar and stop at each button to see the text label. There can be more than one toolbar. The location of each toolbar on the screen can be changed by using the mouse to grab an edge of a toolbar and dragging the toolbar to the desired location. Each Tutorial assumes that you follow the topics in the order they are listed. If you skip some topics then you may experience difficulties with that Tutorial.

3.2: Tutorial Projects

The examples subdirectory for the SILOS installation has a number of tutorials to assist you. Before using these examples it is recommended that you copy them to your personal directory, and if necessary change the file permissions. The tutorial subdirectory contains a number of Verilog examples. Appendix C: Example Projects contains a detailed list of all examples supplied with SILOS.

3.3: Tutorial Topics

The topics presented in the following tutorial are: Creating a project. Simulating a Design. Analog and Digital Waveforms. Debugging Designs. Code coverage. Gate level debugging. Error reporting.

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3.4: Tutorial 1: Creating a Project

This tutorial introduces the concept of a project. It shows how to create projects. Projects provide easy access to the input files and libraries for a design. Projects can be easily passed between designers in a team by simply providing the project file name. All of the settings to run the design and organize the signal names for viewing waveforms are saved in a project.

Procedure
The circuit for this example is a RTL description of a newspaper vending machine. The project has two files, vendtest.v and ven.v. This section shows you how to create a new project for inputting your source files. Start SILOS. Select the FileNew Project menu selection to open the Create New Project dialog box.

Figure 3-1: Create New Project Dialog

To change to the tutorial/rtl subdirectory of the examples directory, use the drop-down arrow for the Save in box in the Create New Project dialog box. In the File name box, enter rtl, and then click on the Save button to close the dialog box. SILOS will automatically append the suffix .spjx to the project name if you do not add a suffix to the project name.

The Project Properties dialog box will be automatically opened so that you can specify the input files for the project.

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Figure 3-2: Project Properties Dialog

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To input the files for project rtl.spjx: Click on the Add button to open the File Selection dialog.

Figure 3-3: File Selection Dialog

Select the file vendtest.v and click Add to add it to the Verilog Files list. Next, add the file vend.v the same way. Now, click on the Ok button to close the Project Properties dialog box. To specify library files, see the -y and -v command line options in Appendix B: Command Line Arguments.

Exit SILOS by using FileExit. When SILOS exits it will automatically save the project and any recent changes to the associated .spjx file. This concludes the tutorial.

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Tutorial Examples

3.5: Tutorial 2: Simulating a Project

This Tutorial shows how to simulate a project. The tool bar buttons have yellow pop up title boxes called data tips so that their function can be easily identified. Clicking on the Go button to simulate a design and start debugging.

Procedure
Start SILOS. Load the previous project rtl.spjx by using FileOpen Project.

Figure 3-4: Load Project Dialog

For this demo, ensure the Enable debugging (Single Step/Breakpoints) button on the Main toolbar is enabled (depressed in) by clicking on it, if necessary, before starting the simulation. When the Enable debugging (Single Step/Breakpoints) debug button is enabled, then single stepping and setting breakpoint capabilities are available for this tutorial example. If you do not need to use single stepping and breakpoints for your design, then you should disable the Enable debugging (Single Step/Breakpoints) button to increase the simulation speed for behavioral designs. Next, click on the Go button on the toolbar to load the input files and run logic simulation (you can see the text labels for each of the buttons on the toolbar for SILOS by placing the mouse cursor over a button for a few seconds until the text label for the button appears). The logic simulation will run until it encounters the $finish system task in file vendtest.v. You could also have used the DebugGo menu to run the logic simulation.

Note: SILOS will display a busy indicator in the status bar in the lower right hand corner to indicate the tool is running a simulation.

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Figure 3-5: Simulation Output Window

3.5.1: Messages in the Output Window

To see the source statement that caused a message in the Output window, such as from a $display statement or a timing violation message, double-click on the message Adding coins to vending machine and file vendtest.v will be opened in a Text Editor window with the Verilog HDL statement highlighted that caused the message.
SILOS uses a highlight color to identify messages in the output window that respond to a double click

action.

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Figure 3-6: Output Window

Figure 3-7: Text Editor Window

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3.5.2: Using the Explorer to Display Signals as Waveforms

Any variable can be viewed as a waveform without re-simulating. This is possible because SILOS's algorithms quickly and compactly save everything to disk when simulating. The design's hierarchy is displayed so that variables can be easily selected.

Procedure
SILOS has the capability to drag and drop variable names from the Explorer window (and also from any HDL source window) to the Data Analyzer window. To do this:

Click on the Analyzer button on the toolbar to open the Data Analyzer window. Next, click on the Explorer button on the toolbar to open the Explorer window. You can change how the signal names are sorted in the SILOS Explorer by clicking with the right mouse button on the right hand side of the Explorer to open the context menu, and then selecting Sort by Name.

Figure 3-8: Explorer and Data Analyzer Window

The instance name stimulus, in the left-hand box of the SILOS Explorer window, is the top-level module for the design. To select the signal names for instance stimulus: Use your mouse to select instance stimulus. To highlight the variable names for instance stimulus, click and release on the first signal name, clock. Next, hold down the Ctrl key on the keyboard, and then click and release on additional signal names: coin[1:0], newspaper and reset. To drag and drop signal names, click on the highlighted variable names without releasing the left mouse button, and drag them from the Explorer window and drop them in the Name list box in

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Tutorial Examples

the Data Analyzer window. The waveforms for each signal will then appear in the Analyzer window. To drag and drop signal names from further down in the hierarchy: Click on the + sign to the left of instance stimulus to show the hierarchy beneath it. You can also change how the signal names are sorted by clicking with the right mouse button in the right side of the Explorer to open the context menu, and then selecting Sort by Type. Then select instance vendY to show the variable names in the right hand side of the Explorer window. The symbol to the left of each variable shows its function. Input ports have the pad symbol pointing to the right, output ports have the pad symbol pointing to the left, and inout ports have the pad symbol pointing in both directions. For non-port variables, the symbol for a wire is a wire connecting two points, the symbol for a register is a flop symbol, P is used for parameters, R for real variables and I for integer variables. Select signals NEXT_STATE and PRES_STATE for instance vendY, and use the Add Signals to Analyzer menu selection in the Explorers right hand side context menu by clicking with the right mouse button in the right hand pane of the Explorer.

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3.5.3: Viewing Source code Variables and Expressions as Waveforms

Any variable or expression can be dragged and dropped from the source window to be viewed as a waveform without re-simulating.

Procedure
SILOS has the capability to drag and drop variables and expressions from the Source window to the Data Analyzer window. To do this:

Click on the FileOpen File button on the Main toolbar to open the vendtest.v file. To view the waveform for variable pad, scroll to line 15 of file vendtest.v, wire pad = enable? clock: 1'bz; and double click on pad to select it. Next, left click on pad and, without releasing the mouse button, drag pad to the Name box of the Data Analyzer, and release the left mouse button to drop pad and view the waveform. To view the right hand side (rhs) expression for pad, use the left mouse button to highlight enable ? clock : 1'bz. Next, without releasing the mouse button, left click on the highlighted expression, drag the expression to the Name box of the Data Analyzer, and release the left mouse button to drop the expression and view the waveform.

Figure 3-9: Drag and Drop Signals, Variables and Expressions to Data Analyzer Window

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3.5.4: Using Title Tips

In order to maximize the display area for waveforms, Title Tips lets you see the full name for signals, making it easier to debug designs.

Procedure
Resize the Name list box by using the mouse to drag the right vertical edge of the Name list box and slide it to the left or the right. The Name, Scope and Value columns can be resized by using the mouse to move the vertical separator between them. Each of the signal names can have its full hierarchical path (Title Tips) displayed when the mouse cursor is held over the hierarchical name in the Scope column. Right click on the label, and choose to display or un-display the Scope or Value column of the Name list box.

Figure 3-10: Full Hierarchical Path (Title Tips)

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Figure 3-11: Option to Display the Scope or Value Column of the Name List Box

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3.5.5: Rearranging the Signal Names

Rearranging the signal names using drag and drop makes it easier to view relationships between signals.

Procedure
To prevent source windows from popping up, click on the Trace Source button on the Analyzer toolbar so that the button is out and the Trace Source capability is off. The Trace Source capability is discussed in Section 3.7.1:Trace Source. Signal names can be rearranged in the Name list box by using the mouse to drag the signal and then drop it just before the pointed end of the mouse cursor arrow. For example: Select signal reset with the mouse. Drag it to just above the signal clock.

Figure 3-12: Rearranging the Signal Names

Multiple signals can also be selected using the following modifier keys: To perform multiple signal selections, keep the control key (Ctrl) depressed while using the mouse to select. To select a set of signals in a contigious list, keep the Shift key depressed while dragging the mouse.

Having selected a group of signals, the following modifiers can be used to control whether the signals are moved or copied: The Shift key will allow the signals to be moved to a new location. The Ctrl key will allow the signals to be copied to a new location.

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3.5.6: Setting Waveform Colors

By default, a waveform is displayed using a color to denote its strength. A waveforms color can be changed to allow it to be easily located in the Data Analyzer window. The Data Analyzer background color can also be changed.

Procedure
Right mouse click on signal coin[1:0] in the Name list box in the Data Analyzer to open the context menu, and select Set Trace Color to open the Change Signal Color dialog box. Choose red as the waveform color, and click on the OK button to close the dialog box.

Figure 3-13: Change Signal Color Dialog

To use color to represent a waveforms logic strength, right mouse click on signal name in the Name list box in the Data Analyzer to open the context menu, and select Set Strength Color Coding. The color used to depict the waveform will depend on the logic strength of the waveform at a given time. To change the background Background menu selection. color use the EditPreferencesOptionsWaveform

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3.5.7: Expanding and Collapsing a Vector

You can display the individual bits for a vector without re-simulating.

Procedure
To expand the individual bits for a vector: Click on the plus (+) box to the left of the vector name coin[1:0]. Click on the minus (-) box to the left of the vector name again will hide the vector signal bits.

To make the signals easier to view, you can add blank lines by using the Add Blank Line menu selection in the context menu for the Name list box. For more information on accessing context menus in the Data Analyzer, see Section 4.7:The Data Analyzer.

Figure 3-14: Expanding a Vector in the Data Analyzer

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3.5.8: Displaying Vector Contents using Symbolic Names

Vectors and buses can be displayed with meaningful state machine names, such as 5 cents. This eliminates constantly looking up the state machine symbol corresponding to a hex value for a vector.

Procedure
Use a Symbol Table file to establish the relationship between the opcode and the data. Because a design may contain many types of opcodes, each opcode set is given a name. That opcode set is applied to the signal using Set Radix. One way to think of the opcode is that it is implemented as a special type of radix. 1. Decide on name for the set of opcodes (e.g. coin_values). 2. Decide on a mapping between values and opcodes (e.g. 2=dime). 3. Create a Symbol Table file to enable this mapping (e.g. opcode.sym). 4. Enter the opcode mapping in the Symbol Table file using the following format: [coin_values] 0=none 1=nickel 2=dime 3=dime + nickel Note: You can add additional entries for other opcodes in the same file. 5. Save the file. 6. Load the mapping using the EditProject PropertiesOther Settings menu option. 7. Select the signal you wish to be represented as an opcode. 8. Use the context menu and select Set Radix from the menu. A dialog box will appear. 9. From the dialog box, select Symbol for the Radix and the opcode name (e.g. coin_values) for the symbol table. 10. Click OK to represent the signal using the selected opcodes. To display the state PRES_STATE[1:0]: machine values for vectors coin[1:0], NEXT_STATE[1:0], and

Select the EditProject PropertiesOther Settings menu.

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Figure 3-15: Other Settings Menu

Use the Browse button in the Project Properties dialog box to open the Select Symbol Table dialog box. Double-click on file rtl.sym to set the Analyzer Symbol Table File box. The format for the symbol table file lets you specify hex values and associate those values with symbolic names, i.e.: 001b=jump The hex values are listed as hex numbers, i.e. 1, 8, b, without any size or base specification. Note the hex value in the table must exactly match the hex value for the vector that is displayed by the Data Analyzer as shown when the Hex radix is used. For example, if a vector was nineteen bits wide and its hex value when displayed in the Data Analyzer is 001b, then the symbol table entry must be: 001b=jump Also, notice there are no blank spaces on either side of the equal sign. To view an example of the format for a symbol file, use the FileOpen menu to open file rtl.sym in the examples directory. Click on the OK button to close the Project Properties dialog box. Click on the No button in the message box that asks to reload the project. To open the context menu in the Name list box, click with the right mouse button over top of signal coin[1:0] in the Name list box for the Data Analyzer window. Then select the Set Radix selection to open the Set Radix dialog box. In the Set Radix dialog box, click on the drop-down arrow for Radix and select Symbol. For the Symbol Table box in the Set Radix dialog box, click on the drop-down arrow and select coin_values, and then click on the OK button.

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Figure 3-16: Set Radix Dialog

Figure 3-17: Displaying Vectors using Symbolic Names

Now use the Set Radix menu selection to set the radix for the vectors NEXT_STATE[1:0] and PRES_STATE[1:0]. To set the radix for both vectors at the same time, select both vectors by holding down the Ctrl key on the keyboard as you select them, and then use the Set Radix menu selection to change the radix. Make sure you click on the minus sign (-) for the default group to save the new radixes.

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3.5.9: Creating an Annotated Timeline for the Waveform Display

An annotated timeline displays the design's operation using meaningful symbols making it much easier to find and debug the design's operations.

Procedure
If you are debugging a design, displaying a vector as ASCII text that explains what the simulation is doing can be very useful. To demonstrate this:

Figure 3-18: Displaying the Vectors in ASCII Text

Use the Open File button on the Main toolbar to open file vendtest.v. Scroll to the bottom of file vendtest.v, and view the case statement used to set the vector info to ASCII strings. This illustrates how to setup the ASCII vector in your source code so that you can use it to display a timeline.

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Figure 3-19: Displaying the Vectors in ASCII Text

To add signal info directly from the source window, double click on signal info to select it. Now use the mouse to drag and drop signal info to the bottom of the Default group in the Name list box for the Data Analyzer window. To change the radix for signal name info to String, right click on signal info[96:1] in the Name list box for the Data Analyzer window. Then select the Set Radix selection to open the Set Radix dialog box. In the Set Radix dialog box, change the radix to String, and click on the OK button. Because the initial value is an Unknown level x for vector info, you can scroll to the right in the Data Analyzer to see meaningful descriptions. Make sure you click on the minus sign (-) for the default group to save the new radixes.

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3.5.10: Groups, Buses, Vectors and Signals in the Analyzer

SILOS uses the concept of a group to help organize signals. A group is a collection of signals. Signals must always be a member of a group. If a group does not exist, then SILOS will automatically create a group called Default. The Default group may be renamed.

Additional groups can be created using the New Group menu selection from the Analyzer context menu. When a new group is created it is called New Groupi where i is an integer that begins at 1 and increments each time a new group is created. The group can be renamed after it is created. If no group or signal is selected when a new group is created, then the new group is placed at the top level of the group hierarchy. If a group or signal is selected when the group is created then the group is embedded at the same level of the group hierarchy as the selected signal. If a group is embedded (i.e. it is not at the top level) then the analyzer will display a composite representation of the signals in the group. The composite representation can be an analog overlay, a digital bus or empty. The menu options Display Group as Analog Overlay, Display Group as Digital Bus and Do not display Group Waveform are used to change how a group is displayed.

Note: The Analog Overlay, Display Group as Digital Bus are not available if the group is at the toplevel of the group hierarchy (e.g. the default group). When displaying a group as a digital bus, the top most signal in the group is taken as the MSB, and the bottom signal as the LSB.

The Analyzer allows you to specify which groups are displayed and hidden in order save drawing time and screen space. A group can be used to organize busses, vectors and signals. A bus is an embedded group, a vector is a multi-bit register or wire, and a signal a single bit constant, register or wire.

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3.5.11: Creating Groups

Procedure
The Name list box for the Data Analyzer has the following options for groups:

Figure 3-20: Context Menu in Name List Box

New Group: This selection can be used to add a new group to the Name list box. Insert Group: This selection opens the Insert Group dialog box. This dialog box will insert a group within a group. The inserted group is displayed as a bus, which can be expanded and hidden by double-clicking on it. Show Groups: This selection opens the Select Visible Groups dialog box. This dialog box can be used to select which groups are displayed in the Data Analyzer. Move Item Up: This selection moves the selected group up. Move Item Down: This selection moves the selected group down.

When the Data Analyzer window is opened, the Default group is displayed. To save the signals that have been added to the Default group: Click on the minus sign (-) just to the left of the Default group in the Name list box.
SILOS will ask you if you want to save the changes to the Default group (unless they have already

been saved). Click on the Yes button (if the signals have not already been saved).

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3.5.12: Buses
New buses can be easily created without re-simulating, which saves time.

Procedure
Groups can be used to represent a bus. For example, to create a bus that uses the signals clock and newspaper: Click with the right mouse button in the Name List Box for the Data Analyzer to open the context menu.

Figure 3-21: Creating a New Group

Select New Group in the context menu. This will add the group labeled New Group1 to the Name List Box. To change the name of the new group, select the group and press F2. Change the name to clk_news and press the Enter key on the keyboard.

Note: You need to press the Enter key after renaming the signal. Select signals clock and newspaper by holding down the Ctrl key, and use the mouse to drag and drop them to the new group clk_news. To reverse the bit order in group clk_news, highlight signals clock and newspaper in group clk_news. Then open the context menu in the Name list box and select Reverse Bit Order.

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Figure 3-22: Inserting a Group into an Existing Group

To display the group as a vector, insert the group into an existing group. Right mouse click on the group where you want to insert the other group and select Insert Group. In the Insert Group dialog, select the newly created group and click the OK button. The new group will be displayed as a vector in the Destination group. You can also add blank lines before and after clk_news.

Note: If an existing group is selected when a new group is created, the new group will automatically be placed inside the existing group and be displayed as a vector.

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3.5.13: Displaying a Logic Condition as a Waveform

Without re-simulating, you can define a search condition using any Verilog HDL expression. Scanning to the condition and viewing it as a waveform gives you quick access to important conditions of the design's operation. Searching on any Verilog HDL expression is possible because SILOS saves everything quickly and compactly to disk when simulating.

Procedure
A unique feature of SILOS is the ability to view a search condition as a waveform. You can use any valid Verilog HDL expression to create a search condition and then display it as a waveform.

Figure 3-23: Add Signal/Expression to Data Analyzer Dialog

For example, to create a search condition for when stimulus.clock and stimulus.coin[1] are both true: Click with the right mouse button in the Name list box for the Data Analyzer to open the context menu. Select the Add Signal menu selection to open the Add Signal dialog box. Set the scope in the Scope edit box to stimulus. Enter the expression (clock && coin[1]) in the Signal (or Expression) edit box, and click the OK button. The waveform for the expression (clock && coin[1]) will then be displayed in the Data Analyzer. If you single click on the expression that you added to the Data Analyzer, pause, then click on the expression again (or use F2), you can modify the expression. For example, you can change coin[1] in the expression to coin[0].

3.5.14: Timing Markers

The Waveform Display window allows you to set two timing markers, T1 and T2, which can be used to display the time that edges occur, and the delta time between edges. To set the timing markers: Place the mouse cursor over the Waveform Display window. Click on the left and right mouse buttons to set the T1 (blue vertical line) and T2 (red vertical line) timing markers.

The T1 and T2 time values, and the delta time between the T1 and T2 timing markers are displayed in the Status bar at the bottom of the SILOS window. These time values are also displayed at the bottom of the waveform window if the program preference setting EditPreferencesWaveform ViewerAnalyzer OptionsDisplay Marker Time Values is checked. The state value at the T1 timing marker for each waveform is displayed in the Value column for the Name list box for the Data Analyzer. When setting the T1 and T2 timing markers for the Data Analyzer, they will snap to the nearest edge if the PreferencesAnalyzer OptionsSnap to Edge menu selection is active. When setting a timing marker, you can hold down the shift key to temporarily toggle the Snap to Edge selection to its opposite effect.

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3.5.15: Scan-to-Change, Scan-to-Value

You can scan to change in a waveform state, or scan to a particular waveform value. Easy scanning and panning saves time when debugging.

Procedure

Figure 3-24: Enter Scan Value Drop-Down Box

To demonstrate scanning to a change edge, highlight vector NEXT_STATE[1:0] in the Name list box and click on the 1> toolbar button to scan the T1 marker to the right. The state value for each waveform in the Value column will change as you scan the T1 marker edge to edge. The T2 marker has no effect on the state values in the Value column. To demonstrate scanning to a value, click on the drop down arrow for the Scan to Change box on the main toolbar, and choose the Enter Scan Value selection. Enter the value 15 cents in the box on the main toolbar, and click on the 1> button on the Main toolbar to scan the T1 marker to the right as it matches each value of 15 cents for the vector NEXT_STATE[1:0]. Scan to Value can be used to scan to the value for a bit, a vector, or a symbolic name because Scan to Value does a character match. The ? character can be used as a don't care character, such as ?ff? would match with 1ff3 and ffff.

Figure 3-25: Scan to Change

The Pan to T1, Pan to T2 and Pan Last buttons on the Analyzer toolbar let you pan to the T1, T2 timing markers, or pan to the last view in the Data Analyzer.

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Figure 3-26: Scan to Value

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3.5.16: Zoom-Buttons
Allows for easy viewing of waveforms across simulation time.

Procedure

Figure 3-27: Zoom Buttons

The zoom buttons on the toolbar allow you to zoom-full, zoom-out, zoom-in, and zoom-in-between markers. To demonstrate the zoom capabilities: Click on the Zoom-Full button on the toolbar to display the entire simulation range. This may take some time with large simulations, but you can stop the zoom-full by holding down the escape key Esc on the keyboard. Use the Zoom Out button to zoom-out by a factor of two and the Zoom In button to zoom-in by a factor of two. Next, use the T1 and T2 timing markers to frame a portion of the simulation range. Use the Zoom Markers button on the toolbar to zoom in-between the timing markers. The Zoom Markers feature is also linked to the middle mouse button for systems that support that function.

3.5.17: Scrollbar
Allows for scrolling of waveforms across simulation time.

Procedure

Figure 3-28: Waveform Window Scrollbar

The scrollbar at the bottom of the waveform display can be used as a go to button. Use the mouse to move the scrollbar to approximately time 1 us (micro seconds). The new time values are displayed along the horizontal time axis as you move the scrollbar. The keyboard left and right arrow keys may also be used to scroll the waveform window.

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3.5.18: Bookmark, Timescale, Goto Timepoint

Enables you to quickly jump between simulation times and resolutions during debug.

Procedure
The Data Analyzer window has a context menu that includes selections for Goto Timepoint, Time Scale and Add Bookmark menu selections. To invoke the context menu, use the right mouse button to click on the timescale just above the Waveform Display window. The context menu will remain open while the left mouse button is used to select a menu item.

Figure 3-29: Add Bookmark

Figure 3-30: Goto Timepoint, Time Scale, Add Bookmark Dialog

The Goto Timepoint menu selection opens the Goto Timepoint dialog box. The specified timepoint can be displayed either at the left or the center of the Waveform Display window. Silvaco, Inc. 3-29

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Note: At certain zoom levels the tool may not be able to place the time point at the specified location. For example, if the waveform is fully zoomed, then the timepoints at the left and center of the display will be fixed. however, the marker will be moved to the correct timepoint.

The Timescale menu selection opens the Time Scale dialog box. When specifying the time scale you can use any standard unit, such as 600ns (nanoseconds), 1000ps (pico seconds), etc. The Add Bookmark menu selection places a virtual marker at the center of the Waveform Display window for the current time and timescale resolution. After opening the Add Bookmark dialog box you will see the default bookmark name, i.e. Bookmark1, Bookmark2, etc. You can specify any string of characters for the bookmark and then click on the OK button to set the bookmark. The bookmarks you have set are listed at the bottom of the context menu. To demonstrate using a bookmarker: Activate the context menu by clicking with the right mouse button in the Data Analyzer x-axis. Select the Add Bookmark menu selection to open the Add Bookmark dialog box. To set Bookmark0, click on the OK button. Open the context menu and use the Goto Timepoint menu selection to go to another simulation time, such as 0.5us. Then open the context menu again and select Bookmark0 to go back to where you were.

3.5.19: Scrolling the Waveform Window (for systems equipped with wheel mice)
The waveform window can be scrolled by vertically using the scroll wheel, and horizontally if the keyboard Shift key is depressed while scrolling the mouse wheel. If the Shift key and Ctrl key are simultaneously depressed, the scrolling will use larger steps.

3.5.20: Viewing Simulation Results in HDL Code using Data Tips

The simulation value for any variable or expression can be viewed by opening the Verilog HDL source window and holding the mouse cursor over the variable, or highlighting an expression and holding the mouse cursor over the expression. This lets you debug directly in a Verilog HDL source code window. The Goto Module Definition and Goto Instance Definition menu selections can be used to quickly display a module definition or instance in the hierarchy.

Procedure
The Explorer window can be used to open the source file for a module definition to display the value for a variable or expression. To demonstrate this: To open the context menu in the Explorer window, select instance stimulus in the hierarchy in the left side of the Explorer window, and click with the right mouse button while over the instance stimulus. In the context menu that appears, select Goto Module Definition. This will open file vendtest.v with the cursor just to the left of the definition for module stimulus. Hold the mouse cursor over the variable clock. The value, scope, radix, and simulation time for variable clock will be displayed. The simulation time for the value is determined by the following criteria: If the simulation timepoint has not completed, such as during single stepping, then the current simulation time point is displayed. If the Data Analyzer is not open, then the last simulation time point is used to display the data tip value. If the Data Analyzer is open, then the time for the left axis of the Waveform window for the Data Analyzer is used to display the data tip value. If the T1 timing marker is displayed in the

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Data Analyzer, then the time associated with the T1 timing marker (blue color, set by left mouse button) is used to display the data tip value. Setting the T1 timing marker lets you display the data tips value at different time points. If you want to select the radix for the value displayed by the Data Tips, open the context menu in a source window by clicking in the source window with the right mouse button, and then select the Data Tip Radix menu selection to see the list of radixes.

Figure 3-31: Explorer Context Menu

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Figure 3-32: Data Tip

3.5.21: Exiting Silos

Exit SILOS by selecting the FileExit menu selection. This concludes the Tutorial.

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3.6: Tutorial 3: Analog and Digital Waveforms

This Tutorial covers how to view and manipulate Analog and Digital waveforms.

3.6.1: Opening the Project

Start SILOS and begin by opening the analog project example in the examples/verilog-d directory.

Figure 3-33: Open Project

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3.6.2: Viewing Analog Waveforms

In this example a number of waveforms are analog in nature. In SILOS an analog waveform is indicated by an analog waveform icon to the left of the signal name as shown in Figure 3-34.

Figure 3-34: Analog Waveforms

3.6.3: Expanding Analog Waveforms

In order to see more detail, an analog waveform can be expanded in the Y-axis by double clicking on the analog waveform icon to the left of its name. When an analog signal is expanded, SILOS displays more detailed y-axis information to the left of the window. This information can be exposed or hidden by using the Expand Y-Axis and Collapse Y-Axis buttons.

Figure 3-35: Expand Y-Axis Button

Figure 3-36: Collapse Y-Axis Button

Figure 3-37: Selecting a Signal

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Figure 3-38: Expanding an Analog Signal by Double Clicking

It is possible to expand all the analog signals by using the Expand All Analog Signals command on the analyzer context menu (see Figure 3-39).

Figure 3-39: Expand all Analog Signals Menu Selection

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Figure 3-40: Result of Expanding All Analog Signals

All analog signals can be collapsed by selecting Collapse All Analog Signals from the Analyzer context menu.

3.6.4: Changing Display Type of Analog Waveforms between PWL and Step
Analog waveforms can be displayed as either a Step or Piece Wise Linear (PWL) function. By default, a waveform is displayed as a PWL function. In order to change how the waveform is displayed, select the signal name and right click to bring up the Context menu. From this menu, select Analog Display Options. Then change the Display Type to Step.

Figure 3-41: Select Signal

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Figure 3-42: Set Analog Display Options Menu Selection

Figure 3-43: Set Display Type Menu

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Figure 3-44: Switching Display Type Menu

Figure 3-45: Result of Changing The Waveform Display Type to Step

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3.6.5: Creating Analog Overlays

Any number of analog waveforms can be superimposed in an overlay. In order to form an overlay, create a group containing the signals of interest (see Section 3.5.10:Groups, Buses, Vectors and Signals in the Analyzer), select the group, and then use the Display Group as Analog Overlay option from the context menu.

Figure 3-46: Analog Overlay

3.6.6: Expanding an Analog Overlay

An analog overlay can be expanded in exactly the same way as any other analog signal by double clicking on the signal, or clicking on the + to the left of the signal name (see Section 3.6.3:Expanding Analog Waveforms).

Figure 3-47: Analog Overlay After Expansion

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3.6.7: Identifying Overlay Signals Using Trace Colors

In order to identify individual signals in an overlay, a trace color can be assigned to each signal by clicking on the plus sign (+) to the left of the overlay and using the Set Trace Color option from the context menu (see Section 3.5.6:Setting Waveform Colors for more details).

Figure 3-48: Analog Overlay Components

Figure 3-49: Analog Overlay with Individual Trace Colors

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3.6.8: Changing the Y- Axis from Variable to Fixed Scale

By default, waveforms are displayed with a variable Y-Axis scale. Depending on the portion of the waveform being viewed the Analyzer will automatically select the Y-axis limits in order to present the best possible waveform view.

Figure 3-50: Waveforms with Variable Y-Axis

In order to change to a fixed axis where the Y-axis limits do not change, use the Set Analog Display options menu selection from the Analyzer context menu. Set the Scale Options to Fixed Scale and the Min and Max values to the desired values.

Figure 3-51: Set Analog Display Options Menu

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Figure 3-52: Switch to Fixed Scale

Figure 3-53: Setting Scale Values

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Figure 3-54: Waveform with Fixed Y-Axis

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3.6.9: Performing Mathematical Operations on Signals

Analog waveforms can be manipulated by applying a mathematical function to their value. In this example an analog waveform with a voltage span of 0v to .05v can be converted to a crude digital representation by scaling its voltage span to 0v and 1v. This is performed by dividing the signal value by 5.

Figure 3-55: Selecting Signal

Figure 3-56: Converting to 0 and 1 by Dividing by 1.8

Select the signal name and replace it with a mathematical function: feedback/1.8.

Note: The mathematical operations supported are those of the Verilog-D HDL.

Note: An Additional casting function is supported to allow an analog signal to be converted to digital about a threshold: ((reg 0.9) feedback.

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3.6.10: Displaying Analog Signals as Digital Signals

Analog signals can be displayed as digital signals by using the Analyzer context menu option Display as Digital.

Figure 3-57: Selecting Signal

Figure 3-58: Display as Digital Menu Selection

A dialog will request a threshold value for conversion. Enter 0.9 into the dialog box.

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Figure 3-59: Enter Threshold Dialog

Once the threshold value is entered, the analog signal will be displayed as a digital signal. The signal can be displayed as an analog signal again by removing the casting function.

Figure 3-60: Analog Signal Converted to Digital

3.6.11: Displaying a Group of Analog Signals as a Digital Bus

In order to display a group of Analog Signals a digital bus, convert the analog signals to digital using Display as Digital, and then select the group and then select Display Group as Digital Bus from the context menu.

Figure 3-61: Analog Signals Displayed as a Digital Bus

3.6.12: Exiting Silos

Exit SILOS by selecting the FileExit menu selection. This concludes the Tutorial.

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3.7: Tutorial 4: Debugging Designs

3.7.1: Trace Source
With the Trace Source capability, you can left mouse click on a waveform to pop up the source file and highlight the Verilog HDL statement which caused that waveform's value. The Trace Source capability for behavioral code is enabled by checking the Enable Visual Debug checkbox in the Project PropertiesOther Settings dialog box. When the Trace Source button is depressed, the Trace Source capability is active.

Figure 3-62: Project Setting to Enable Visual Debug

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Figure 3-63: Trace Source

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3.7.2: Visual Debug using Behavioral Traceback

Enabling Visual Debug allows behavioral code to be used with the Trace Source and the Trace Inputs capability. Trace Source displays which Verilog HDL statement caused a level on a waveform. Trace Inputs traces through behavioral code displaying the cause of an Unknown level on a waveform.

Procedure
Behavioral traceback is initiated from a Data Analyzer window. First, place the T1 marker on the waveform for newspaper by left mouse clicking on the waveform for newspaper around time=0.057us. Then right-mouse click on the name for signal newspaper to obtain the context menu. In the context menu, select the Trace Inputs menu selection to open the Trace Inputs window.

Figure 3-64: Trace Input Analyzer Context Menu Selection

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Figure 3-65: Trace Inputs Window

The signals shown in the Trace Inputs window are edge-sorted such that the first Verilog HDL statement is the one that most likely caused the level at the T1 marker. The sort is live, so moving the T1 marker may cause the window to be refreshed with a new sort. Trace Inputs provides three useful functions: 1. When more than one Verilog HDL statement causes the value of a waveform at a time point, the Trace Source capability can be useful in distinguishing which Verilog HDL statement caused the waveform's value.

Example
A wire with multiple drivers: In the simulation shown below, pad is a bidirectional pad where the enable is incorrect for one clock cycle, causing an Unknown level on pad. If pad is not already in the Data Analyzer (from an earlier step in the Tutorial), drag and drop signal pad from the top level of the SILOS Explorer to the Name box of the Data Analyzer. Press the Trace Source button to enable Trace Source, and left mouse click on the waveform for pad around time=0.091us. This will show the statement that caused the Unknown level on pad. Next right mouse click on the name pad in the Data Analyzer to bring up the context menu, and select Trace Inputs to open the Trace Inputs window for tracing on pad. After this step in the Tutorial, delete pad and the expression enable ? clock : 1'bz; from the Data Analyzer, as these signals are no longer needed for the Tutorial.

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Figure 3-66: Trace Signal Input from Data Analyzer Window

2. A register with multiple assignments at a time point: For example, in the screen capture shown below, reset is set in an initial block. However, this triggers an always block which sets reset to unknown in the same time point. To duplicate this enable Trace Source (if Trace Source is not already enabled), and left mouse click on the waveform for reset around time=0.055us. This will show the statement that caused the Unknown level on reset. Next, right mouse click on the name reset in the Data Analyzer to bring up the context menu, and select the Trace Inputs menu selection to open the Trace Inputs window for tracing on reset. In the Trace Inputs window, when you double-click on one of the input names or right hand side (rhs) signal names for an assignment, the Trace Inputs window is refreshed and the name double clicked on is placed at the top, and its inputs are displayed below it. By double-clicking on enough inputs, one ends up in the testbench. By double clicking on the top signal name you can go back to the previous Trace Inputs window.

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Figure 3-67: Trace Signal Input from Data Analyzer Window

3. Whenever the inputs, or right-hand-side (rhs) variables of assignment statements, need to be viewed as waveforms, Visual Debug automatically adds them for viewing. This saves valuable time by not having to drag and drop signals into the Data Analyzer or Trace Inputs windows.

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3.7.3: Single Stepping

You can single step through the source code as it executes to understand, locate and fix problems. The value for any variable or expression in the source code can be displayed to assist with debugging. Any variable or expression can be dragged and dropped to the Data Analyzer to view the waveform.
SILOS's ability to quickly and efficiently save every variable during simulation makes this possible.

This intuitive approach to source code debugging reduces the time required to understand design flaws. The single stepping and breakpoints features can reduce simulation speed, so these features should be disabled before simulation if you do not intend to use them.

Procedure
This topic covers: Single stepping through a design. Dragging and dropping variables and expressions from your source code into the Data Analyzer window. Viewing variables as they change value in the Data Analyzer window. Setting the value for a two bit register. Using breakpoints to skip over uninteresting behavioral code.

To demonstrate the capabilities of single-stepping for behavioral code: Click on the Enable Debugging (Single Step/Breakpoints) button to enable the debugging feature. Click on the Load/Reload Input Files button to restart the simulation to time = 0. Click on the Step button on the toolbar until SILOS automatically opens the source window for file vendtest.v and puts a yellow arrow to the left of the source code line that was just executed. SILOS has a built-in editor for basic editing in the source windows.

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Figure 3-68: Single Stepping

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Figure 3-69: Add Signal and Expression to Watch Window and Data Analyzer
Next click on the Watch button on the toolbar to open the Watch window. To select a variable, double-click on variable clock in the source window. Drag and drop variable clock from the source window to the Watch window and to the top of the Default group in the Data Analyzer window. To create additional space for viewing the windows, minimize the Output window. Single stepping can be used to determine the condition for an if test or a case statement before SILOS branches into it. To demonstrate this, continue clicking on the Step button on the main toolbar until the source window opens for file vend.v (it should take at least 8 clicks). Use the mouse to highlight the expression reset == 'b1 in file vend.v and drag and drop the expression into the Data Analyzer window and the Watch window. You will see that the expression is true, so that the next step will go to the statement directly below the if test. Then continue to click on the Step button. Notice that the values in the Watch window and the Data Analyzer window are updated as the single-stepping progresses.

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Figure 3-70: Add Signal and Expression to Watch Window and Data Analyzer

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3.7.4: Breakpoints
Breakpoints let you skip over sections of source code so that you can focus your debugging time on the code that is causing the problem.

Procedure

Figure 3-71: Breakpoints Dialog

Breakpoints can be set using the DebugView Breakpoints menu selection, or click on the left side of the numline of the Text Editor. SILOS has the following breakpoints for debugging behavioral code: Break at Simulation Time: Stops logic simulation before the selected time is simulated. Break at Location: Stops logic simulation before the selected source line is simulated. Break in Module Instance: Allows you to select a module and then stop logic simulation each time any source line in the selected module instance is to be simulated. Break in Module (Any Instance): Allows you to select a module instance and then stop logic simulation each time a source line in any instance of the module is to be simulated.

Setting a breakpoint can be used to skip over uninteresting code so that you can continue to single step in the code of interest. For example, to keep single stepping in file vendtest.v in the Examples subdirectory: Put the mouse cursor on the line (near the bottom of file vendtest.v): #20 clock = ~clock; Click on the line number to the left of the code. A small, red stop sign symbol will be placed to the left of the line next to the line number. You can also use the menu option DebugInsert/Remove Breakpoint. Next, continue to click on the Step button on the toolbar until you leave file vendtest.v. Again, click on the line number to the left of the code and a small, red stop sign symbol will be placed to the left of the line next to the line number. Now you can continue to single step in module vendtest.v.

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Figure 3-72: A Breakpoint set at line 70

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3.8: Tutorial 5: Code Coverage

This Tutorial covers SILOSS Code Coverage feature. Code Coverage reports behavioral lines that did not execute, and operators not fully exercised. Code Coverage is simple to use: flip a switch, simulate, and look for red text boxes. No preprocessing of files is required, and the results are directly annotated into the source files. Exporting of coverage results. Sorting by execution count, file name, module name, line number for the tabular presentation of coverage. Double-clicking on an entry in the line coverage report, or the operator coverage report directly, opens the corresponding source code. Annotation of coverage results directly onto the source windows. Independent reporting of operands. Merging of coverage data from independent simulation runs. Ability to turn off coverage for specific lines and blocks of behavioral source code. Automatic elimination of spurious time 0 initialization from coverage results. Graphical selection of scope of code coverage.

3.8.1: Generating Line Coverage Reports

This topic covers: Setting up Code Coverage. Displaying a report for lines that are not executed. Revealing possible inefficiencies in the behavioral model. Sorting by execution count, file name, module name, line number for the tabular presentation of coverage. Exporting of coverage results.

Procedure
Start SILOS. To open the example for Code Coverage, select the FileOpen Project menu selection to open the Open Project dialog box. Select the project named code_coverage.spjx in the Examples directory, and click on the Open button to close the dialog box. Since this example does not include single stepping or setting breakpoints, these features can be disabled to improve simulation speed by clicking on the Enable Debugging (SingleStep/ Breakpoints) button on the Main toolbar to push the button out (if it is not already pushed out). To setup Code Coverage, click on the Enable Code Coverage button if it is not already selected. If the Enable Code Coverage button is selected after inputting the files for the design, SILOS will query if you want to reload the design and setup Code Coverage. Click on the Go button to simulate the design. Select the ReportsCode Coverage Line Report menu selection to open the Code Coverage Line Coverage report. This report is sorted by the number of times each line is executed (Hits) in ascending order. Normally you are interested in which lines are not executed (0 Hits). However, the report can also be used to see which lines have a high number of executions, indicating a possible flaw in the design. If you want to change the sort order, click on the column heading that you wish to sort by.

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Figure 3-73: Code Coverage Line Report

Figure 3-74: Data Tip Showing Code Coverage Information

When the Code Coverage Line Report comes up, double click on the first entry in the report that has zero Hits. This will open the code_coverage.v file, and display the line that did not execute with a red text box to the left of the line. Click the Main window to change the focus to the text window. Place the mouse cursor over the red text box in file code_coverage.v, and a yellow box will pop up stating Line Not Executed. A large number of hits in the Code Coverage Line Report may indicate a looping problem in the design. To see an example of this, double click on the last entry in the Code Coverage Line Report to automatically go to that line of file code_coverage.v. Notice that this line is in an always loop that triggers itself by recursively setting the variable in the sensitivity list. To see how many times

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the line was executed, change the focus back to the Main text window, place the mouse cursor over the green text box, and a yellow box will pop up stating Line Execution Count=44.

Figure 3-75: Code Coverage Line Report

Figure 3-76: Data Tip Showing Code Coverage Information

You may want to display the Code Coverage results in another program, such as Microsoft Excel. The demonstrate the exporting of the Code Coverage results, select the ReportsExport menu selection to open the Export Code Coverage Data dialog box. Select a file name of your choice, and click the OK button to close the dialog box. You can edit the file you created to view the export format, or import the file into a program such as Microsoft Excel.

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3.8.2: Generating Operator Coverage Reports

This section covers: Selecting module instances to be covered using the Explorer. Displaying a report for operands that fail to affect the corresponding operator. Displaying a report for bits in the operands that fail to affect the corresponding operator.

Procedure
To eliminate the testbench from code coverage, click on the Open Explorer button on the Main toolbar to open the Explorer window. Click with the right mouse button when the mouse cursor is over the top level instance testbench. In the context menu, select Module Properties to open the Module Properties dialog box. Uncheck the Save code coverage data for this entry box, and click OK to close the dialog box. To enable the design select_ABCD for code coverage, click with the right mouse button when the mouse cursor is over the top level instance select_ABCD. In the context menu, select Module Properties to open the Module Properties dialog box. Check the Save code coverage data for this entry box, and click OK to close the dialog box. The Save code coverage data for this entry will be grayed out if the module instance is outside of the device under test ($fs_dut system task), or if code coverage is not enabled.

Figure 3-77: Module Properties Dialog

Click the Enable Code Coverage button if it is not already selected. If the Enable Code Coverage button is selected after inputting the files for the design, SILOS will query if you want to reload the design and setup Operator Coverage. Answer Yes to the query. Enabling Operator Coverage can increase the simulation time, so normally you would not enable this until ready to review Operator Coverage. If the files were reloaded, click the Go button on the Main toolbar to run the simulation.

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Tutorial Examples Select the ReportsCode Coverage Operator Report menu selection to open the Select Operator Report Options dialog box. The DEFAULT Operator 1/0 Result option is already selected, so click the OK button to close the dialog box, and open the Code Coverage Operator Report list box. The DEFAULT Operator 1/0 Result option will report the result of each operator, except for math operators (+, -, /, *, %). Double click on the first entry in the Code Coverage Operator Report list box to go to the corresponding line of file code_coverage.v. In the code_coverage.v file, a red text box shows that the result for the > operator for the expression C > D failed to be true. When there is more than one expression on a line, the Operator Report will list them separately. However, if you want to visually see a red text box message in the SILOS GUI for each operator, you can put each operator on a separate line in your Verilog HDL source code.

Figure 3-78: Code Coverage Operator Report

The Operator Report can also be used to show which operands did not affect the corresponding operator. Select the ReportsCode Coverage Operator Report menu selection again to open the Select Operator Report Options dialog box. Next deselect the DEFAULT Operator 1/0 Result, and select the remaining options in the Select Operator Report Options dialog box. This will display a red text box on each line where an operand failed to affect an operator.

Figure 3-79: Code Coverage Operator Report

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Figure 3-80: Data Tip Showing Code Coverage Information

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3.8.3: Merging Code Coverage Reports

This section covers: Using the GUI to merge the code coverage results from two regression simulations using different testbenches for the same design. Disabling code coverage for the testbench. You should disable code coverage in the testbench, as it is unlikely you want to see code coverage results for the testbench. it is important to put the testbench in a separate file, so that changing the testbench does not change the line positioning for your design. Code coverage results depend on keeping your design files constant as you run the simulations, because the line number for each line of source code is used during code coverage. For this reason, to see how to disable code coverage for the testbench, select the FileOpen menu selection to open the Open dialog box. Select the testbench for this run, file testbench2.v, and click on the Open button to open the file. Notice that file testbench2.v contains the following compiler directives to disable code coverage: `disable_codecoverage module testbench; endmodule `enable_codecoverage The `disable_codecoverage compiler directive turns off code coverage for the lines that follow it. The `enable_codecoverage turns code coverage back on.

Procedure
You may want to run different testbenches on the same design and merge the results. Regression runs can be used to simulate different testbenches. The results can then be combined and displayed with the SILOS GUI. Start SILOS. To open the example for code coverage, select the FileOpen Project menu selection to open the Open Project dialog box. Select the project named code_coverage.spjx in the examples directory, and click on the Open button to close the dialog box. To enable code coverage, click on the Enable Code Coverage button if it is not already selected. If the Enable Code Coverage button is selected after inputting the files for the design, SILOS will query if you want to reload the design. Click on the Load/Reload Input Files button to input the design and simulate to time=0. Click on the Start Simulation button to start the simulation. Select FileClose Project to close the current project, the code coverage information is stored in the file code_coverage.codecov. Open another project code_coverage2.spjx. Enable Code Coverage and start simulation. View the line coverage or operator coverage by selecting ReportsCode Coverage Line Report or ReportsCode Coverage Operator Report. To merge the results from this run and the previous run, select the ReportsMerge Code Coverage Files menu selection to open the Code Coverage File Select dialog box. Select the file. Click Open to merge the code coverage results from the first regression run with those of the second run. This dialog box is additive, so you can select multiple files if you want. You can use this dialog box again to add additional results.

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Figure 3-81: Line Coverage Before Merge of Coverage Results

Figure 3-82: Code Coverage File Selection Dialog

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Figure 3-83: Line Coverage After Merge of Coverage Result

Figure 3-84: Code Coverage File Selection Dialog

Now that code coverage results have been merged, you can select the Code CoverageLine Report menu selection or the Code CoverageOperator Report menu selection to review the combined code coverage results.

3.8.4: Exiting Silos

Exit SILOS by selecting the FileExit menu selection. This concludes the Tutorial.

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3.9: Tutorial 6: Gate Level Debugging Using Trace Inputs

This Tutorial covers gate level debugging in SILOS using the Trace Inputs feature.

3.9.1: Trace Inputs

SILOS has the ability to trace a signal backwards (using the Trace Inputs feature) through the

topology to find the cause of an undesired state value.

Procedure
For the Tutorial, the Trace Inputs feature is used to find out why the signal newspaper went from an Unknown level to a Low level at time=0.021 us in the gate level synthesized design for the newspaper vending machine. Please note that for gate level traceback, the Enable Trace Source checkbox in the Project Settings dialog box can be disabled and gate level traceback will work. The Enable Trace Source checkbox only effects behavioral traceback: Select the FileOpen Project menu to open the Open Project dialog box. Highlight the gate.spjx project file (gate level design for the Newspaper Vending Machine FSM) and click on the Open button in the Open Project dialog box. To increase simulation speed, disable Enable Code Coverage and Enable Debugging (Single Step/Breakpoints) using the buttons on the Main toolbar. Code Coverage applies only to behavioral code, and Debugging enables single stepping and breakpoints for behavioral code, neither of which apply to a gate level simulation. Click on the Go button to simulate the design. Click on the Analyzer button to open the Data Analyzer (unless it automatically opens).

Figure 3-85: Analyzer and Trace Inputs Window

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Tutorial Examples

The Trace Inputs window displays newspaper as driven by an output port named .out, that is connected to the local variable named out.

Note: If you see No Saved Data instead of a waveform, this means the variables simulation history was not saved. A possible cause for not saving the simulation history is that the signal may be inside of a `celldefine boundary. Signal stimulus.vendY.U118.out should now be at the top of the Trace Inputs window. Listed below signal stimulus.vendY.U118.out is the two input and gate whose output is driving the signal. Since both inputs for the and gate go from Unknown to Low at time=0.021us, you could trace backwards on either input. For the purposes of this example, back track on signal \PRES_STATE[0].

3.9.2: Exiting Silos

Exit SILOS by selecting the FileExit menu selection. This concludes the Tutorial.

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3.10: Tutorial 7: Error Reporting

This Tutorial covers error reporting in SILOS. Syntax errors in your design will be automatically reported to the Output window. Whenever the file name and line number are reported with the syntax error, you can double click on the error in the Output window, and the Source File window will be automatically opened with the error highlighted. You can also use the ReportsErrors and Warnings menu selection and the syntax errors will be reported in separate report window.

Procedure
In this Tutorial, project rtl_err.spjx has a syntax error. To view the syntax error: Select the FileOpen Project menu selection to open the Open Project dialog box. Highlight the rtl_err.spjx project file (RTL level design for the Newspaper Vending Machine FSM) and click on the Open button in the Open Project dialog box. Click on the Go button to attempt to simulate the design.

Figure 3-86: Output Window

Double click on the syntax error that is reported in the Output window. This will open file vend_err.v and highlight the syntax error. Notice that the real error occurred on the line above due to the missing semi-colon (;) at the end of the line. This is very common because SILOS could not determine there had been an error until it parsed the next line, where, instead of finding the module port list, SILOS encountered a register statement.

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Figure 3-87: Reported Error

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3.10.1: Exiting Silos

Exit SILOS by selecting the FileExit menu selection. This concludes the Tutorial.

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Chapter 4: Graphical User Interface Reference

4.1: GUI Overview
Figure 4-1 shows an overview of the GUI.

Figure 4-1: GUI Overview

4.1.1: Dockable/Detachable Elements

All of the GUI elements, except the Analyzer and Output Editor windows, are Dockable and Detachable.

4.1.2: Context Menus

Many windows have context menus that can be accessed by clicking on the right mouse button.

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4.1.3: Dialog Box Conventions

The following conventions should be noted for dialog boxes: Selecting the OK button will close the dialog box and use any selected options or specifications. Selecting the Cancel button will close the dialog box and not affect any options or specifications. Selecting the Apply button will keep the dialog box open, and any active options or specifications will be used. The File Open dialog filters can be modified, see Options->File Open Dialog Filters in Section 4.14.14: Preferences Menu Selection.

4.1.4: Interrupting Silos

Selecting the Stop Simulation button on the toolbar, or holding down the Escape key (Esc) on the keyboard (wait until SILOS checks for it, e.g. when SILOS writes to the Output window, or writes to the save file on disk) will stop the current process, such as reading a file or running logic simulation. If SILOS hangs and does not respond to the STOP button, see Section 4.19.6: Nonconvergence (Hanging) for Behavioral Designs. For the command line version, pressing Ctrl+C on the keyboard will stop the current process.

The GUI is composed of a number of regions discussed in the following sections.

4.2: The Menu Bar

Figure 4-2: Menu Bar

The menu bar pull down menus are discussed in more detail in the following sections: Section 4.13: File Menu Section 4.14: Edit Menu Section 4.15: View Menu Section 4.16: Analyzer Menu Section 4.17: Debug Menu Section 4.18: Explorer Menu Section 4.19: Reports Menu Section 4.20: Help Menu

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4.3: The Toolbars

There are two toolbars: Tools toolbar and Analyzer toolbar.

4.3.1: Tools Toolbar

Figure 4-3: Tools Toolbar Table 4-1: Tools Toolbar Buttons

Icon Function Open Project Button

Save Project

New File Button

Open File Button

Save File Button

Lint Button

Load Reload Input Files Button

Reload and Go

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Table 4-1: Tools Toolbar Buttons

Go Button

Break Button

Step Button

Waveform Viewer Button

Explorer Button

Watch Button

Enable Debugging

Enable Code Coverage

Back Button

Forward Button

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4.3.2: Analyzer Toolbar

Figure 4-4: Analyzer Toolbar Table 4-2: Analyzer Toolbar Buttons

Icon Function Zoom Full Button

Zoom Out Button

Zoom In Button

Zoom Marker Button

Scan T2 Marker Left

Scan T1 Marker Left

Scan to Change Button

Scan T1 Marker Right

Scan T2 Marker Right

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Table 4-2: Analyzer Toolbar Buttons

Pan T1

Pan T2

Pan Last View

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4.4: The Explorer

Figure 4-5: Explorer

The Explorer can be used in two modes, Modules or Files. These modes are selected by the tab control on the top of the Explorer window.

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Explorer File Mode

The Explorer File Mode displays the source files for a project in a File Browser type display. The Folder tree will display the directory trees that contain files used in the current simulation project. If the ExplorerFile Tree Flat Mode menu option is selected, the file list will display only those project files at or below the directory selected in the Folder tree. Double clicking on a file name in the file list will open the selected file in the editor window.

Figure 4-6: Explorer File Mode

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Explorer Module Mode

The Explorer Module Mode is similar to a File Browser, there are two panes (sub windows) and a Scope bar. The left pane (Module Tree) displays the module hierarchy of the current simulation and the right pane displays the pins and variables for the module selected in the tree. The Scope bar (see Figure 4-8) displays the scope (hierarchical path) of the module selected in the Module Tree. The Scope drop down list contains a list of recently selected module scopes. If a valid scope is typed into the Scope control, the module tree with be updated to select that scope.

Figure 4-7: Explorer Module Mode

Figure 4-8: Scope Bar

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4.5: Explorer Design Hierarchy Tree

The Design Hierarchy Tree displays the instance name of a module and the module name separated by a :. To traverse the hierarchy of the design, click-on the plus sign (+) to the left of the instance, or doubleclick on module instances. As each module instance or gate is selected in the left window; the names of the variables in that instance are displayed in the right window.

Figure 4-9: Design Hierarchy Tree

The left-hand side of the Explorer window has a context menu for the Copy Scope, Select Scope, Instance Name Filter, Go to <module definition>, Go to <module instance>, and Module Properties menu selections. To invoke this context menu, use the right mouse button to click on any part of the left-hand side (the side with the hierarchical tree) of the Explorer window. The context menu will remain open while the left mouse button is used to select a menu item.

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Figure 4-10: Design Hierarchy Tree Context Menu

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4.5.1: Copy Scope Menu Selection

The ExplorerTreeCopy Scope menu selection is located in the context menu in the left hand Tree side of the Explorer window. When you select a hierarchical instance in the Explorer window, the Copy Scope menu selection (or simultaneously holding down the Ctrl and the C keys on the keyboard) will copy the hierarchical instance name to the Windows Clipboard. This enables you paste the hierarchical name (simultaneously holding down the Ctrl and the V keys on the keyboard). To invoke this menu selection, right click on any part of the left hand side of the Explorer window to open the context menu and select the Copy Scope menu selection.

4.5.2: Select Scope Menu Selection

The ExplorerTreeSelect Scope menu selection is located in the context menu in the left hand Tree side of the Explorer window. This feature lets you quickly find an instance in the Explorer window. The Select Scope menu selection opens the Enter Scope dialog, where you specify the scope for the instance that you want to find. Then click on the Ok button and the Explorer window will highlight the instance you selected. To invoke this menu selection, right click on any part of the left hand side of the Explorer window to open the context menu and select the Select Scope menu item.

4.5.3: Instance Name Filter Menu Selection

The ExplorerTreeInstance Name Filter menu selection is located in the context menu in the left hand Tree side of the Explorer window. This feature allows you to use a regular expression to filter the instance names to assist you with quickly finding an instance in the Explorer window. The Instance Name Filter menu selection opens the Name Filter dialog, where you specify the filter for the instance that you want to find. The check box for Exclude Matching Names lets you display all instance names except those that match the regular expression you entered. Then click on the Ok button and the Explorer window will show only the instances you selected. For more information on regular expressions, see Section 4.6.4: Regular Expressions.

4.5.4: Go to <module definition/instance> Menu Selection

The ExplorerTree<module definition> and ExplorerTree<module instance> menu selections are located in the context menu in the left hand Tree side of the Explorer window. This feature lets you quickly find the source code for any instance in your design. When you select a hierarchical instance in the Explorer window, the Go to <module definition> menu selection opens a source window that displays the source code for the module definition. When you select a hierarchical instance in the Explorer window, the Go to <module instance> menu selection opens a source window that displays the instantiation of that module inside of the module definition that invokes it. To invoke this menu selection, right click over the instance name in the left hand side of the Explorer window to open the context menu and select the Go to <module definition> or Go to <module instance> menu selection.

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4.5.5: Module Properties Menu Selection

The Module Properties menu selection is located in the context menu in the left hand Tree side of the Explorer window. The Properties menu selection opens the Module Properties dialog box. The Module Properties dialog box lets you specify which module instances you want to save the simulation data for during simulation. See Section 6.19: Keeping Module Instance Simulation Variable Values for an additional method of saving instances in the hierarchy.

Figure 4-11: Module Properties Menu

If Save simulation data for this entry is selected, then SILOS saves the simulation data for the following items during simulation: All local variables for the module instance. All port variables for the module instance (even if the ports connect to module instances that are not saved below it in the hierarchy). Any instance below it in the hierarchy of the design, unless the instance below it is specifically not saved.

If Save simulation data for this entry is not selected, then SILOS does not save the simulation data for following items during simulation: All local variables for the module instance not selected. The simulation data for any instance below it in the hierarchy of the design.

Before the Save simulation data for this entry specifications can take effect, the files must be reloaded by using the Load/Reload Input Files button on the Main toolbar. The Module Properties dialog box also has a check box for Save code coverage data for this entry. When this is checked, code coverage information is saved for this instance. If this box unchecked, code coverage information is not saved for this instance. The Save code coverage data for this entry will be grayed out if the module instance is outside of the device under test ($fs_dut system task), or if code coverage is not enabled. Before the Save code coverage data specifications can take effect, the files must be reloaded by using the Load/Reload Input Files button on the Main toolbar. To invoke this menu selection, right click over the instance name the left hand side of the Explorer window to open the context menu and select the Properties menu item.

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4.6: Explorer Port and Variable List

Figure 4-12: Port and Variable List

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The Port and Variable list uses the following convention:

Table 4-3: Port and Variable Display

Icon Item Bi-Directionals

Inputs

Outputs

Registers

Wires

Parameters

Reals

Integers

The right-hand side of the Explorer window has a context menu for the Go to Definition, Add Signals to Analyzer, Name Filter, Sort by Name, and Sort by Type menu selections. To invoke this context menu, use the right mouse button to click on any part of the right-hand side (the side with the signal names) of the Explorer window. The context menu will remain open while the left mouse button is used to select a menu item.

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Figure 4-13: Port and Variable List Context Menu

4.6.1: Go To Definition Menu Selection

The ExplorerListGo to Definition menu selection is located in the context menu in the right hand Signal side of the Explorer window. The Go to Definition menu selection will automatically open the source file, and highlight the definition line for the variable that is selected in the right side of the Explorer window. To invoke this menu selection, right click on a variable in the right hand side of the Explorer window to open the context menu and select the Go to Definition menu selection.

4.6.2: Add Signals to Analyzer Menu Selection

The ExplorerListAdd Signals to Analyzer menu selection is located in the context menu in the right hand Signal side of the Explorer window. The Add Signals to Analyzer menu selection is useful for adding signals to the Data Analyzer when it is difficult to drag and drop the signals due the screen size. To invoke this menu selection, highlight the signal you want to add to the Data Analyzer, then right click over the signal names to open the context menu, and select the Add Signals to Analyzer menu selection.

4.6.3: Name Filter Menu Selection

The ExplorerListName Filter menu selection is located in the context menu in the right hand Signal side of the Explorer window.

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To invoke this menu selection, right click on any part of the right hand side of the Explorer window to open the context menu, and select the Name Filter menu selection. The name filtering in the Explorer window uses regular expressions. A short description of regular expressions follows.

4.6.4: Regular Expressions

A regular expression is a notation for specifying and matching strings. Regular expressions have two basic kinds of characters: 1. Special characters: These are characters that have special meaning for matching strings. The special characters for regular expressions are: \ where: \ This escapes or quotes other characters, such as \$ matches the "$". A useful quoted string is \| which means or. Another useful quoted string is \( and \) which allow the parenthesis to be used to group regular expressions. For example, ac* means the character a and zero or more characters of c. However, \(ac\)* means zero or more occurrences of the character string ac. This matches the preceding character at the beginning of a string. When ^ is the first character in a character class it means the compliment of the character class. This matches the preceding character at the end of a string. This matches any single character. ] Characters enclosed in brackets are a character class. This matches zero or more occurrences of the character that precedes the *. This matches one or more occurrences of the character that precedes the +. This matches zero or one occurrence of the character that precedes the ?. ^ $ . [ ] * + ?

$ . [ o o ?

2. Ordinary characters: These are all the other available characters. These characters match themselves, such as a would match the letter a. The character class [ ] has special rules. Inside a character class, all characters have their literal meaning, except for the quoting character \, ^ at the beginning, and - between two characters. Each of the characters in a character class are treated as an or search. For example, [ab] will find any single character name a or b. The character class [a-z] will match any single character lower case name. The character class [^a-zA-Z] will match any single character name that is not an alpha. Some examples of using regular expressions are listed below: a a.* .*a .*a.* [abc] [a-z] Matches only the name lowercase a. Matches any name that begins with a. Matches any name that ends with a and the name a. Matches any name that has an a anywhere in the name. Matches only the names a or b or c. Matches any name that is a single lower case character, such as b.

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[a-z]* [a-zA-Z]*

Matches any name that is only lower case characters, for example data. Matches any name that is upper and/or lower case characters, for example data, DATA and Data. Matches any name that has upper and/or lower case characters and/or digits, for example data, DATA and Data, 123, data1.

[a-zA-Z0-9]*

[a-zA-Z0-9_]* Matches any name that has upper and/or lower case characters, and/or digits, and/or _, for example data, DATA and Data, 123, data1, and DATA_bus1. Some programming books (such as AWK and Perl) show regular expressions enclosed with slashes // . The SILOS style of searching for regular expressions is a character search, and forward slashes have no special meaning. For example, using the regular expression /clock/ to try to find any name that contains an a will find only the name /clock/. Regular expressions are not like the Unix style wildcards (where ? matches any single character, * matches any pattern, and [list] matches any character in list including ranges). For example, using the regular expression a to find any name that contains an a will not find any names. If you want use regular expressions to find every name that has an a, you can enter: .*a.* For the above expression, .*a.* means search for zero or more occurrences (the first *) of any character (the first .), followed by a single character a, followed by zero or more occurrences (the second *) of any character (the second .). So, with the search .*a.* you could find names such as a, data, read, etc.

4.6.5: Sort by Name or Type Menu Selections

The ExplorerListSort by Name and the ExplorerListSort by Type menu selections are located in the context menu in the right hand Signal side of the Explorer window. The Explorer window supports the ability to sort the names in the right-hand window by the type of variable (port, wire, register, etc.), or by name. The Explorer displays the name of every module instance and variable in the design in a tree structure similar to the directory structure for the Windows Explorer. The Shift and Ctrl keys can be used to select variable names in a similar manner to the Windows Explorer. Names can then be dragged and dropped to the other windows, such as the Data Analyzer window and the Watch window. The Explorer window also has context menus that can be accessed by using the right mouse button.

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4.7: The Data Analyzer

Figure 4-14: Analyzer

The Data Analyzer contains a two sub regions: The Signal List Window and the Waveform Window.

4.8: Data Analyzer Signal List Window

Figure 4-15: Signal List Window

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Table 4-4: Analyzer Signal Type Icons

Icon Type Analog Signal

Analog Overlay

Digital Bus

The left-hand side of the Data Analyzer has a context menu:

Figure 4-16: Context Menu

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4.8.1: Trace Inputs Menu Selection

The AnalyzerSignal ListTrace Inputs menu selection opens a Trace Inputs window. The Trace Inputs window lets you interactively trace an incorrect value at a net, or a variable to its cause, by displaying the waveforms of all the devices or assignments that are driving the net. To trace on a variable in behavioral code, the Enable Trace Source option must be enabled in the Project Settings dialog box. Trace Inputs is initiated from a Data Analyzer window. First, place the T1 marker on a waveform of interest, then right-mouse click on the name of the signal to obtain the context menu. In the context menu select the Trace Inputs menu selection to open the Trace Inputs window. The signals shown in the Trace Inputs window are edge-sorted such that the first Verilog HDL statement is the one that most likely caused the level at the T1 marker for the top-most signal. The sort is live, so moving the T1 marker may cause the window to be refreshed with a new sort. The T2 marker is automatically placed on the input/rhs variable edge that SILOS guesses to be the cause of the T1 signal value. After you visually confirm this, double-click on the input signal name to trace through the design. To assist with debugging, you may also drag-and-drop other signals into a Trace Inputs window, such as a clock. If you see no saved data instead of a waveform, this may mean that the signal is inside of a `celldefine boundary. To save data within `celldefine boundaries, see the Save `celldefine data option in Section 4.14.13: Project Properties Menu Selection. Trace Inputs provides three useful functions: 1. When more than one Verilog HDL statement causes the value of a waveform at a time point, the Trace Source capability can be useful in distinguishing which Verilog HDL statement caused the waveform's value. SILOS alerts you to this condition by flashing a red message at the left of the status bar that states more than one Verilog HDL statement is causing the waveform value. Two possible cases that could cause this are: A wire with multiple drivers, or; A register with multiple assignments at a time point.

2. In the Trace Inputs window, when you double-click on one of the input names or right hand side (rhs) signal names for an assignment, the Trace Inputs window is refreshed and the name double clicked on is placed at the top, and its inputs are displayed below it. By double-clicking on enough inputs, you end up in the testbench. By double clicking on the top signal name, you can go back to the previous Trace Inputs window. 3. Whenever the inputs, or right-hand-side (rhs) variables of assignment statements, need to be viewed as waveforms, Visual Debug automatically adds them for viewing. This saves valuable time by not having to drag-and-drop signals into the Data Analyzer or Trace Inputs windows.

4.8.2: Go to Definition Menu Selection

The AnalyzerSignal ListGoto Definition menu selection is useful for finding where a signal name is defined in the source code. To invoke the context menu, right click over the signal name in the Name list box and select the Goto Definition menu item. The Goto Definition menu selection opens a source window that highlights the definition of the signal you selected.

4.8.3: Signal Groups Menu Selections

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also useful for assisting engineers who are unfamiliar with the design, and for record keeping if the design is reused. The context menu for the Name list box provides the following selections for groups: New Group: This selection can be used to add a new group to the Name list box. Delete Group: This selection can be used to delete a group. Insert Group: This selection opens the Add Group dialog box. This dialog box will insert a group into an existing group. The inserted group is displayed as a bus. The individual bus signals can be expanded and hidden by double-clicking on it. Show Groups: This selection opens the Select Signal Groups dialog box. This dialog box can be used to select which groups are displayed in the Data Analyzer. Groups that are not displayed in the Data Analyzer are referred to as hidden groups. Reload Groups: This selection will cause the Data Analyzer to clear the list box and reload the group information from the project file. This is useful when a user written program is used to modify the groups while SILOS is running. Save Groups: Save any signal groups that have changed to the project file.

To invoke the context menu, right click over the group you want affected, and select the group menu item of interest. When the Data Analyzer window is opened, the Default group is displayed. To save any signals that are added to the Default group (or any group), click on the minus sign (-) just to the left of the group's name. SILOS will ask you if you want to save the changes to the group.

4.8.4: Display Group as Analog Overlay Menu Selection

This menu selection displays the group contents as an analog overlay.

4.8.5: Display Group as Digital Bus Menu Selection

This menu selection displays the group contents as a digital bus.

4.8.6: Do Not Display Group Waveform

This menu selection will not create a waveform for the group.

4.8.7: Set Radix Menu Selection

The AnalyzerSignal ListSet Radix menu selection is located in the context menu for the Name list box. Setting the radix for a vector can assist with debugging the design. The radix can be set to binary, octal, hexadecimal, decimal, analog, or time to conveniently display the vector. Symbolic names can be used to represent the values for a state machine. ASCII vectors can be displayed to create a timeline of events for the Data Analyzer display. To set the radix for a vector: Right click on the vector to open the context menu. Next, select the Set Radix menu selection in the context menu. The Set Radix dialog box will then be opened and you can select the Radix. If you select the Symbol Table radix, then select the correct symbol table in the Symbol Table box (Symbol Tables can be specified in the Project Settings dialog box).

The OK button closes the dialog box and sets the vector to the selected radix. The Cancel button closes the dialog box and does not affect the vector's radix.

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4.8.8: Change Signal Color Menu Selection

The Data AnalyzerSignal ListChange Signal Color menu selection opens the Select Trace Color dialog box, which can be used to select a color for a waveform.

4.8.9: Set Analog Display Options Menu Selection

This menu selection brings up a dialog that allows an analog waveform to be displayed as either a PWL or Step waveform.

4.8.10: Expand All Analog Signals Menu Selection

This menu selection expands the Y-axis of an analog waveform to show more detail.

4.8.11: Collapse All Analog Signals Menu Selection

This menu selection collapses the Y-axis on an analog waveform to hide the detail.

4.8.12: Display as Digital Menu Selection

This menu selection allows an analog signal to be converted to digital for display purposes. The selection uses a dialog box to request a threshold value for conversion.

4.8.13: Add Menu Selections

To invoke the context menu, right click on any part of the Name list box and select the appropriate bit menu item. The context menu for the Name list box for the Data Analyzer has the following selections: Add One Bit Menu Selection: Adds a single bit signal at a high level just ahead of the selected signal name. Add Zero Bit Menu Selection: Adds a single bit signal at a Low level just ahead of the selected signal name. Add Signal Menu Selection: The Data AnalyzerSignal ListAdd Signal menu selection opens the Add Signal dialog box. Adding a signal can be very useful for performing conditional searches. The added waveform can be any expression whether the expression exists in your HDL source code or not. For a conditional search, you can then use the scan to change feature and the States list box to review the signal values for the conditional search.

The Add Signal feature can also be useful for adding expressions that exist in your source code, such as for an if test, and then viewing then the expression is true (high). The Add Signal dialog box contains an edit box Scope to specify the scope for the signal. The Specify Signal/Expression dialog box also contains a Signal or (Expression) edit box to enter a signal or an expression. Any valid Verilog HDL expression can be entered. You can copy and paste an expression that is in your source code window by highlighting the expression and using the Ctrl C keys on the keyboard to copy and the Ctrl V keys to paste the expression into the Signal or (Expression) list box. If the expression or scope is not valid then the waveform will be blank. The OK button closes the dialog box and displays the specified expression in the Data Analyzer. The Cancel button closes the dialog box and does not display the expression. If you single click on the expression (or use F2) that you added to the Data Analyzer, pause, then click on the expression again, you can modify the expression. Add Blank Line Menu Selection: The Data AnalyzerSignal ListAdd Blank Line menu selection inserts a blank line in the Data Analyzer just above the signal name that is highlighted.

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4.8.14: Reverse Bit Order

Reverses the signal order for the highlighted signals in the Name list box. This is useful for reversing the bit order for a group.

4.8.15: Delete Item/s Menu Selection

The Data AnalyzerSignal ListDelete Items menu selection deletes all of the signal names that are selected in the Name list box.

4.8.16: Move Item Up Menu Selection

This selection moves the selected group up.

4.8.17: Move Item Down Menu Selection

This selection moves the selected group down.

4.8.18: Clear Signal List Menu Selection

The Data AnalyzerSignal ListClear Signal List menu selection deletes all of the signal names in the Name list box. Use the AnalyzerSignal ListReload Groups menu selection to restore the last saved Signal Groups to the Name list box.

4.9: Data Analyzer Waveform Window

Figure 4-17: Waveform Window

Figure 4-18: Waveform Window Scrollbar

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Figure 4-19: Waveform Window Expand Y-Axis Button

Figure 4-20: Waveform Window Collapse Y-Axis Button

The Data Analyzer has an x-axis context menu that includes Pan to T1, Pan to T2, Pan to Last View, Goto Timepoint, Timescale, Add Bookmark and Delete Bookmark menu selections. To invoke this context menu, right click on any part of the time point display area (the gray area just above the Waveform Display window). The context menu will remain open while the mouse is used to select a menu item.

Figure 4-21: Data Analyzer X-Axis Context Menu

4.9.1: Data Analyzer X-Axis Area and Goto Timepoint Menu Selection
The AnalyzerX-AxisGoto Timepoint menu selection opens the Goto Timepoint dialog box for specifying the time point for the left axis or the center of the Waveform Display window. The Goto Timepoint dialog box enables you to precisely position the Waveform Display window for debugging and printing. The time value for the Time Point box can be specified in any standard time unit, such as ns for nano seconds, ps for pico seconds, etc. For example: 12000.3ns

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To invoke the context menu, right click on any part of the x-axis display area (the gray area just above the Waveform Display window) and select the Goto Timepoint menu item.

4.9.2: Pan T1, Pan T2, and Pan Last View Menu Selection
The AnalyzerPan T1 menu selection and the Pan T2 menu selection will center the Waveform Display window around the T1 or T2 timing marker. The Pan to Last View will return the Waveform Display window to the preceding view. These menus are useful during debugging for jumping between views of the simulation results. To invoke the context menu right click on any part of the x-axis display area (the gray area just above the Waveform Display window) and select the Pan T1, Pan T2, or Pan Last View menu item.

4.9.3: Timescale Menu Selection

The AnalyzerX-AxisTimescale menu opens the Time Scale dialog box for setting the number of time units per division of display. Setting the timescale is useful for debugging the design. The current time scale, T1 time value, T2 time value, and delta time value can be displayed by holding the mouse cursor over the x-axis for a few seconds. To modify the time scale, open the Time Scale dialog box and enter a value in the Time/Div box. You can use any standard time unit, such as ns for nano seconds, ps for pico seconds, etc. For example: 12000.3ns The OK button closes the dialog box and causes the Data Analyzer to use the selected time scale. The Cancel button closes the dialog box and does not affect the Data Analyzer.

4.9.4: Add Bookmark Menu Selection

The AnalyzerX-AxisAdd Bookmark menu selection enables you to place a virtual marker for the time and the timescale resolution of the center of the Waveform Display window. When debugging your design, the bookmakers you set enable you to jump back and forth between waveform views with the same or different timescale. After opening the Add Bookmark dialog box you will see the default bookmarks (i.e. Bookmark1, Bookmark2, etc.). You can specify any string of characters for the bookmark name, and then click on OK to set the bookmark. The bookmarks you have set are listed at the bottom of the context menu. To go to a bookmarker, select it with the left mouse button. To invoke the context menu right click on any part of the time point display area (the gray area just above the Waveform Display window) and select the Add Bookmark menu item.

4.9.5: Delete Bookmark Menu Selection

The AnalyzerX-AxisDelete Bookmark menu selection enables you to delete a bookmarker. After opening the Delete Bookmark dialog box you will see the bookmarkers (i.e. Bookmark1, Bookmark2) listed in the Bookmarks list box. You can delete a bookmark by selecting it with the mouse can clicking the Delete button. Click the OK button to close the dialog box. To invoke the context menu right click on any part of the time point display area (the gray area just above the Waveform Display window) and select the Delete Bookmark menu item.

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4.10: The Output Window

Figure 4-22: Output Window

The Output window has a context menu.

4.10.1: Copy Menu Selection

The Output windowCopy menu selection copies text from a document onto the Clipboard, leaving the original intact and replacing the previous Clipboard contents.

4.10.2: Select All Menu Selection

The Output windowSelect All menu selection selects all the text in a document at once. You can copy the selected text onto the Clipboard, delete it, or perform other editing actions.

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4.11: Source Code Editor Window

4.11.1: Source Editor Debug Tab Option
This option is intended to minimize the number of Source Editor tabs open when viewing error messages. As error messages in the Output window are clicked on, the appropriate source file will be opened on the Source Editor Debug tab. Clicking on an error message from a different source file will switch the file opened on the Debug tab to the new file. If this option is disabled, each new source file will open on a new tab. This option is controlled by a checkbox in the EditPreferencesEditor dialog (see Figure 4-45).

Figure 4-23: Source Code Editor Window

The Source Code Editor window has a context menu.

4.11.2: Undo Menu Selection

The Undo menu selection undoes your last editing or formatting action, including cut and paste actions. If an action cannot be undone, Undo appears dimmed on the Edit menu.

4.11.3: Redo Menu Selection

The Redo menu selection cancels the previous Undo operation.

4.11.4: Cut Menu Selection

The Cut menu selection deletes text from a document and places it onto the Clipboard, replacing the previous Clipboard contents.

4.11.5: Copy Menu Selection

The Source windowCopy menu selection copies text from a document onto the Clipboard, leaving the original intact and replacing the previous Clipboard contents.

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4.11.6: Paste Menu Selection

The Paste menu selection pastes a copy of the Clipboard contents at the insertion point, or replaces selected text in a document.

4.11.7: Open File Menu Selection

The Open File selection will be enabled if the mouse cursor is over a file name or a file name is selected in the editor window. Selecting this item will open the file in a new window.

Figure 4-24: Source Editor Conext Window

4.11.8: Insert/Remove Breakpoint Menu Selection

The InsertRemove Breakpoint menu selection places or removes a simulation breakpoint at the location of the cursor in the source window.

4.11.9: Data Tips Menu Selection

The Data Tips menu selection toggles the Data Tips capability on or off . This feature enables you to trace the cause of problems directly in a Verilog HDL source code window. The Data Tips capability displays the value, scope, radix, and simulation time point for a variable or expression in the source window. Any variable or expression in a source window can be viewed by opening the source window and holding the mouse cursor over a variable or by highlighting an expression and holding the mouse cursor over the expression. If SILOS does not know the scope for the variable or expression, the Data Tips message will request that you open the context menu in the source window by clicking on the variable or expression with the right mouse button, and select the Go to Instance menu to set the scope.

4.11.10: Data Tip Radix Menu Selection

The Source windowData Tip Radix menu selection sets the radix for the Data Tips capability. The allowed radixes are binary, octal, hexadecimal, decimal, real and string. This feature enables you to trace the cause of problems directly in a Verilog HDL source code window.

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4.11.11: Upscope to <module name> Menu Selection

The Upscope to <module name> menu selection will go up in the hierarchy to the instantiation of the current module, open the source window and highlight the instantiation of the current module. The name of the current module is listed in the Current Module Name menu selection.

4.11.12: Downscope to <instance name> Menu Selection

When the mouse cursor has been placed on a module instance name, the Downscope to <instance name> context menu selection will open the source window and highlight the module definition name for the instance.

4.11.13: Current Module Menu Selection

Informs you of the name of the current module.

4.11.14: Select Scope Menu Selection

Select the Select Scope context menu selection in the source window. If the Explorer window is open, highlight the current scope.

4.11.15: Go to Definition of Menu Selection

The Go to Definition of context menu selection in the source window will highlight the definition of the selected variable.

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4.12: The Status Bar

Figure 4-25: Status Bar

The Status Bar will become yellow when SILOS is busy. Any GUI operations will not be serviced while the tool is busy. During simulations, the Simulation Time will be highlighted in yellow. The status bar contains the following information: T1 Marker Time T2 Marker Time Tdelta, the time difference between the T1 and T2 markers. Simulation Time Busy Indicator The product name and version number.

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4.13: File Menu

The File menu has the following menu selections: New menu selection Open menu selection Save menu selection Save As menu selection Save All menu selection Close menu selection New Project menu selection Open Project menu selection Save Project As menu selection Close Project menu selection Import menu selection Export menu selection Link to Gateway menu selection Run Lint on Project Files menu selection Run Lint on File/s menu selection Save Simulation menu selection Restore Simulation menu selection Print menu selection Print Analyzer menu selection Recent Files menu selection Recent Project menu selection

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Figure 4-26: File Menu

4.13.1: New Menu Selection

The FileNew menu selection opens a new source window for editing.

4.13.2: Open Menu Selection

The FileOpen menu selection opens a source window for an existing file so that you can view or edit the file. More that one source window can be open at the same time. Use the source window tab to switch among the multiple open documents.

4.13.3: Save Menu Selection

The FileSave menu selection saves the contents of the source file window that has the focus. When you choose Save, the document remains open so you can continue working on it.

4.13.4: Save As Menu Selection

The FileSave As menu selection allows you to specify a file name and then save the contents of the source file window that has the focus. When you choose Save As, the document remains open so you can continue working on it.

4.13.5: Save All Menu Selection

The FileSave All menu selection will save all the source files that have been edited.

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4.13.6: Close Menu Selection

The FileClose menu selection will close the current source file that is been edited.

4.13.7: New Project Menu Selection

The FileNew Project menu selection opens the Create New Project dialog box. The Create New Project dialog box enables you to specify the name and working directory for a new project. Projects provide a useful method for organizing your source files, as the files and libraries for the project may be scattered across many directories. The new project name can be typed into the File Name box. SILOS will automatically append the suffix .spjx to the project name if you do not add a suffix. Click on Save to create the project name and exit the dialog box. Click on Cancel to exit the dialog box without creating a project name. After selecting the Save button, the Project Files dialog box is automatically opened. The Project Properties dialog box enables you to specify all the source files, library files, and PLI library files associated with a project. To create a new project that is similar to an existing project, you may want to use the FileSave Project As menu selection (see Section 4.13.10: Save Project As Menu Selection).

4.13.8: Open Project Menu Selection

The FileOpen Project menu selection opens the Choose a Project dialog box to specify the name for opening an existing project. Click on the Open button to open the project. Click on the Cancel to exit the menu. Before opening a project SILOS is automatically reset so that the results from any previous project are lost.

4.13.9: Save Project Menu Selection

The FileSave Project menu selection forces the project settings to be written to the project file. This menu item can be used to ensure any changes to the project settings as well as Analyzer display groups and settings, are saved to the project file. Normally the project is only saved to the project file when the project is closed, a new project is selected or the program is closed.

4.13.10: Save Project As Menu Selection

The FileSave Project As menu selection saves the project to the project name that you specify. After it is selected, the Save Project As dialog pops up. Click the Save button, the current project is closed and the new project becomes the current open project. If there are any changes in the source files of the previous project that have not been saved, a prompt pops up and asks if you want to save the changes. It does not save the simulation history for the Data Analyzer. The Save As feature can be used to easily clone projects for testing purposes without having to modify the original project.

4.13.11: Close Project Menu Selection

The FileClose Project menu selection closes the current project. If there are any changes in the source files that have not been saved, a prompt pops up and asks if you want to save the changes. All windows such as the Output window and the Data Analyzer window are also closed.

4.13.12: Import Menu

The FileImport selection opens a submenu. The submenu has the following selection: Project Properties menu selection The FileImportProject Properties selection allows the import of project data from a project file or a partial project file of the correct format into the current project. The supported formats are the original project file (.spj) format or the XML project file format. After selecting the import file in the file select dialog, the file will be read and a project data selection dialog will open. This dialog can be used to select the data from the import file to be added to the current project.

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Figure 4-27: Project Properties Data Selection Dialog

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4.13.13: Export Menu Selection

Figure 4-28: Export Menu Seletction

The FileExport selection opens a submenu. The submenu has the following selections: Analyzer Menu Selection The FileExportAnalyzer selection exports the waveforms in Data Analyzer to the clipboard or the file. If you select the To Clipboard submenu, the wave form in Data Analyzer is exported to clipboard. You can open any image editor and paste the waveform in clipboard into the editor. If you select the To File submenu, a Select file name and type dialog opens. You can select the format of the image file and the file name then select Save to save the wave form image into the file. Project Files Menu Selection The FileExportProject Files selection will save the files used by the current project in an archive file. This menu selection is only available after the project file have been read by the program (i.e., DebugLoad/Reload or DebugGo has been run). Project Properties Menu Selection The FileExportProject Properties selection exports selected project data to a file in the XML project file format. Selecting this menu item will open file select dialog. After selecting the export file name, the project data selection dialog will open. This dialog is used to select the data from the current project to be written to the export file (See Figure 4-29).

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Figure 4-29: Project Properties Data Selection Dialog

4.13.14: Link to Gateway Menu Selection

The Link to GATEWAY option is enabled by the menu item FileLink to Gateway. This option is disabled unless the GATEWAY Schematic Editor is running and the GATEWAY top level schematic matches the SILOS Schematic Root selection in the Explorer module tree window. Explorer linked to Gateway When the Link to Gateway option is enabled, the hierarchical name of the item selected in the Explorer will be sent to GATEWAY which will update the Design Browser to match the Explorer selection.

4.13.15: Run Lint on Project Files Selection

The FileRun Lint on Project Files menu selection will run the built in Lint tool on all the Verilog files included in the project.

4.13.16: Run Lint on File/s Selection

The FileRun Lint on File/s menu selection will run the built in Lint tool on user specified Verilog files.

4.13.17: Save Simulation

The FileSave Simulation menu selection saves the current state of the simulator in a file projectname.cmm. This allows a simulation to be stopped and restored at any time, even if you quit the simulator.

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4.13.18: Restore Simulation

The FileRestore Simulation menu selection restores the current state of the simulation. The option assumes the file projectname.cmm exists and was created using Save Simulation.

Note: You can only restore a .cmm file on the same platform it was generated on. A .cmm file from Windows will not work on Linux.

4.13.19: Print Menu Selection

The FilePrint menu selection uses a Windows common dialog box to print the source and report windows.

4.13.20: Print Analyzer Menu Selection

The FilePrint Analyzer menu selection prints the wave form in Data Analyzer on a printer. After it is selected, the Print dialog pops up. You can select the printer to print the wave form in the Data Analyzer.

4.13.21: Recent Files Menu Selection

The FileRecent Files menu selection opens any recently opened file. The submenus of the menu selection are the most recently opened files. Selecting any of the submenus will open the corresponding file.

4.13.22: Recent Projects Menu Selection

The FileRecent Projects menu selection opens any recently opened project. The submenus of the menu selection are the most recently opened projects. Selecting any of the submenus will open the corresponding project.

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4.14: Edit Menu

The Edit menu provides the following menu selections: Undo menu selection Redo menu selection Cut menu selection Copy menu selection Paste menu selection Select All menu selection Find menu selection Find Next menu selection Replace menu selection Goto Line menu selection Project Properties menu selection Preferences menu selection

4.14.1: Undo Menu Selection

The EditUndo menu selection un-does your last editing or formatting action, including cut and paste actions. If an action cannot be un-done, Undo appears dimmed on the Edit menu.

4.14.2: Redo Menu Selection

The EditRedo menu selection re-does your last editing or formatting action, including cut and paste actions. If an action cannot be re-done, Redo appears dimmed on the Edit menu.

4.14.3: Cut Menu Selection

The EditCut menu selection deletes text from a document and places it onto the Clipboard, replacing the previous Clipboard contents.

4.14.4: Copy Menu Selection

The EditCopy menu selection copies text from a document onto the Clipboard, leaving the original intact and replacing the previous Clipboard contents. When the Data Analyzer window has the focus, the EditCopy menu selection copies the full path for the selected signal name from the Data Analyzer window to the Clipboard.

4.14.5: Paste Menu Selection

The EditPaste menu selection pastes a copy of the Clipboard contents at the insertion point, or replaces selected text in a document.

4.14.6: Select All Menu Selection

The EditSelect All menu selection selects all the text in a document at once. You can copy the selected text onto the Clipboard, delete it, or perform other editing actions.

4.14.7: Find Menu Selection

The EditFind menu selection searches for characters or words in a document. You can match uppercase and lowercase letters and search forward or backward from the insertion point.

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4.14.8: Find Next Menu Selection

The EditFind Next menu selection repeats the last search without opening the Find dialog box.

4.14.9: Replace Menu Selection

The EditReplace menu selection replaces one string with another.

4.14.10: Goto Line Menu Selection

The EditGoto Line menu selection goes to the source line number that was specified.

4.14.11: Add Spice .INCLUDE card Menu Selection

The EditAdd Spice .INCLUDE card menu selection is enabled if the current editor file is a "Spice" type file (file extension .in, .cir or .sp*). Selecting this menu entry will display a file selection dialog. If you select a file in this dialog and click the Add button, the program will add a .INCLUIDE card into the current editor file.

4.14.12: Add Spice .LIBRARY card Menu Selection

The EditAdd Spice .INCLUDE card menu selection is enabled if the current editor file is a "Spice" type file (file extension .in, .cir or .sp*). Selecting this menu entry will display a file selection dialog. If you select a file in this dialog and click the Add button, the program will add a .LIBRARY card into the current editor file.

4.14.13: Project Properties Menu Selection

The EditProject Properties menu selection changes the current project settings. After it is selected, the Project Properties dialog pops up. By selecting different category under the project tree, you can change different settings of the project. The following project settings can be changed:

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Source Files

Figure 4-30: Source Files Project Properties Dialog

The Source File setting is used to specify what files are used in a project.

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Library Files

Figure 4-31: Library Files Project Properties Dialog

This setting maps to the -v Verilog command line argument described in Appendix B: Command Line Arguments.

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Library Directories

Figure 4-32: Library Directories Project Properties Dialog

This setting maps to the -y Verilog command line argument described in Appendix B: Command Line Arguments.

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Include Directories

Figure 4-33: Include Directories Project Properties Dialog

This setting maps to the +incdir Verilog command line argument described in Appendix B: Command Line Arguments.

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PLI Library Files

Figure 4-34: PLI Library Files Project Properties Dialog

This setting can be used instead of the pliload command, as described in Section 5.1.1: Silos PLI Interface on the Windows.

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Other Settings

Figure 4-35: Other Settings Project Properties Dialog

Functional simulation: This setting sets all the device delays to zero. Enable Non-Standard Verilog HDL Extensions: This setting is documented in Chapter E: Non-Standard Verilog HDL Extensions. Enable log file: This setting controls whether a log file is generated. The log file is named 'project'.log and contains a copy of everything written to the Output Window. Disable floating node warnings: This disables warnings generated by the presence of floating nodes in the design. Use alternate behavioral evaluation order: This setting changes how RTL blocks are evaluated. As the Verilog specification does not specify the order of execution of the blocks, this setting may be useful when dealing with code that depends on a specific implementation of block execution. Enable code coverage for library modules: By default library modules contained within a `celldefine `endcelldefine construct are not examined for code coverage. This setting enables code coverage for library modules. Enable Visual Debug: This setting is documented in Section 3.7.1: Trace Source. Auto text file save: If this setting is enabled then any source files modified in the text editor will be saved when the project is reloaded. Warning message limit: This control specifies the limit for the number of warning messages displayed in the Output window (see Section 6.17: Warning Message Limit). Delay selection: This setting controls whether min, typ or max delays are used in the simulation. It performs a similar function to the +mindelays, +maxdelays and +typdelays described in Appendix B: Command Line Arguments.

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Command line arguments: This setting is documented in Appendix B: Command Line Arguments. Analyzer symbol table file: This setting is documented in Section 3.5.8: Displaying Vector Contents using Symbolic Names.

Simulation Data File

Figure 4-36: Simulation Data File Project Properties Dialog

Save all digital data: This option enables saving all digital data.

Note: If this option is not enabled then the simulator may run faster, however, the GUI may become unresponsive until the simulation is complete. The following pop-up appears when the simulation is run (see Figure 4-37).

Figure 4-37: Simulation Warning

Save `celldefine data: This option enables saving data for library cells.

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Disable cache: This setting disables the Simulation Data File Cache. If the program runs out of memory due to large simulation runs then disabling the cache will allow the simulation to run longer. Maximum File Size Options: These are documented in Section 5.4.1: Using Recirculation to Create a Constant Save File Size. Simulation data file name: Use this box to select the name of the simulation data file. The default name is the same root file name as the project file with ".sim" as the extension. This root file name will also be used for code coverage files.

PlusArgs

Figure 4-38: PlusArgs Project Properties Dialog

This setting can be used to supply plusargs in the tool. See +plusargs in Appendix B: Command Line Arguments.

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PlusDefines

Figure 4-39: PlusDefines Project Properties Dialog

This setting maps to the +define Verilog command line argument described in Appendix B: Command Line Arguments.

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Analyzer Settings

Figure 4-40: Analyzer Settings Project Properties Dialog

Analog Signal Scale Options

Use auto scale: If this option is selected then the waveform analyzer will use the min and max values for a waveform in the displayed time range to determine what Y-axis values to use. Use default scale values: If this option is selected then the Waveform Analyzer will use the values from the Max Scale Value and Min Scale Value dialog boxes to determine what Y-axis values to use.

Default Analog to Digital Conversion Threshold

This option is used to set the default threshold that is used to decide whether a signal is a logic 0 or a logic 1.

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4.14.14: Preferences Menu Selection

The EditPreferences menu selection allows you to change the shortcuts, menu and other GUI interface settings. After it is selected, the Preferences dialog pops up.

Figure 4-41: Preferences

The tool preferences can be set for the current session, or saved for future sessions using the Save these settings on exit checkbox. The following preferences can be set:

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Manage Preferences
Manage Preferences allows you to control the tool preferences. Preferences can be imported and exported using a Standard Preferences File (.spf). The preferences can also be reset to the factory default.

Figure 4-42: Manage Preferences

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Application
The toolbars and shortcuts can be configured. SILOS supports two tools bars called Tools and Analyzer. Each toolbar contains a configurable set of icons. The icon size, text label and hints can also be controlled.

Figure 4-43: Shortcuts Preferences

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Figure 4-44: Toolbars Preference

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Editor
The editor tab width, Debug Tab option and the font used in SILOSS editor can be configured. The Source Editor Debug Tab option is described in Section 4.11: Source Code Editor Window.

Figure 4-45: Editor Editing Options

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Figure 4-46: Editor Font

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Most Recently Used (MRU)

SILOS maintains a list of recently opened files and projects. The length of these lists can be set.

Figure 4-47: MRU Length

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Options
Command Line: You can show or hide the Command Line window at the bottom of the program output window. Explorer show full instance name: If checked, this option will display the full hierarchal path (scope) for each entry in the Explorer tree view. Use system dialogs: Selecting this option will cause the program to use the operating system file dialogs and not the QT generated file dialogs.

Figure 4-48: User Interface Options

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Options->File Open Dialog Filters

Displays the file filters used by file open dialogs to limit the list of file names displayed. Each filter consists of two text fields, Description and Filter, and a third field that specifies the file open dialogs that will display the filter. The description field (e.g., Verilog Files) describes the filter field (e.g., (*.v)) which is specified as a wildcard pattern. The third field is modified by selecting the field and clicking on the browse button which opens a list box that selects the dialogs using the filter.

Figure 4-49: File Open Dialog Filters

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Figure 4-50: Figure Filter Browse Button

There is a default set of filters that is loaded by using the Reset button.

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Real Number
The notation used for real numbers can be configured between Engineering and Scientific. The number of significant digits can also be configured.

Figure 4-51: Real Number Notation Preferences

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Waveform Viewer Options

Waveform Viewer list box: Allows the user to select SMARTVIEW or the Anlayzer as the preferred waveform viewer. Changes to the viewer selection will only take effect after the program is restarted or the project is loaded or reloaded. SmartView Options: Allows the user the select which version of SMARTVIEW will be used when the waveform viewer toolbar button is pushed. The SMARTVIEW version can be changed at any time. Use Default Path checkbox: If this check box is checked, the program will use the program installation directory to locate the available SMARTVIEW versions. The available versions will be added to the Version list box. Installation: This edit box displays the default installation path if the Use Default Path checkbox is checked or allows the user to select alternate program installation path. Version: This listbox displays the SMARTVIEW versions available in the current Installation directory. Analyzer Options: The signal list box and waveform background colors can be set. The X-Axis and YAxis grid can be toggled on and off. The waveform markers snap to an edge feature can also be toggled and whether marker time values are displayed. Setting Signal Background Alternates causes alternate lines in the Analyzer to be highlighted with a different background. This can make it easier to follow a given signal across the width of the display. The Display State Change Hazard feature can be toggled using the checkbox. When enabled, State Charge Hazards are indicated by flashing red dots. The tool tip shows how many events occured during the Hazard.

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Figure 4-52: Waveform Viewer Options

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Waveform Viewer Font

This dialog allows you to select the Analyzer waveform viewer font.

Figure 4-53: Waveform Viewer Font

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Third Party Software

Figure 4-54: Altera Quartus II Preferences

Altera Quartus II software, Version 8.0 or later, can be enabled to generate Verilog source for SILOS. Once enabled, SILOS will appear as an EDA Tool in the Tool Name drop down listbox of the AssignmentsEDA Tool SettingsSimulation dialog box of Quartus II. Selecting SILOS in this dialog generates Verilog source code for SILOS.

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4.15: View Menu

The View menu provides the following menu selections: Toolbars menu selections Analyzer menu selection Explorer menu selection Watch menu selection Back menu selection Forward menu selection

4.15.1: Toolbars Menu Selection

The ViewToolbars menu selection shows or hides toolbars. Its submenus are: Tools, Analyzer, Line up and Customize. Tools and Analyzer are toggle submenus. Clicking on the Tools menu will show or hide the tools toolbar. Clicking the Analyzer menu will show or hide the Data Analyzer toolbar. There are icons on the menu indicating whether the toolbar is shown or hidden.

4.15.2: Analyzer Menu Selection

The ViewAnalyzer menu selection shows or hides the Data Analyzer window. It is a toggle menu, and the icon on the menu indicates whether the Data Analyzer is shown or hidden.

4.15.3: Explorer Menu Selection

The ViewExplorer menu selection allows you to show or hide the Hierarchy Explorer window. It is a toggle menu, and the icon on the menu indicates whether the Hierarchy Explorer is shown or hidden.

4.15.4: Watch Menu Selection

The ViewWatch menu selection shows or hides the Watch window. It is a toggle menu, and the icon on the menu indicates whether the Watch window is shown or hidden.

4.15.5: Back and Forward Menu Selection

The ViewBack and ViewForward menu selection opens the previous or next source file edit window.

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4.16: Analyzer Menu

The Analyzer menu has the following menu selections. Zoom In menu selection Zoom Out menu selection Zoom Full menu selection Zoom Marker menu selection Pan T1 menu selection Pan T2 menu selection Pan Last View menu selection Trace Source menu selection Signal List menu selection Timeline menu selection

4.16.1: Zoom In Menu Selection

The AnalyzerZoom In menu selection zooms in the Data Analyzer window by a factor of two.

4.16.2: Zoom Out Menu Selection

The AnalyzerZoom Out menu selection zooms out the Data Analyzer window by a factor of two.

4.16.3: Zoom Full Menu Selection

The AnalyzerZoom All menu selection displays the entire simulation time range.

4.16.4: Zoom Markers Menu Selection

The AnalyzerZoom markers menu selection will zoom-in-between the T1 and T2 timing markers if they are displayed.

4.16.5: Pan T1 Menu Selection

The AnalyzerPan T1 menu selection will center the Waveform Display window around the T1 timing marker.

4.16.6: Pan T2 Menu Selection

The AnalyzerPan T2 menu selection will center the Waveform Display window around the T2 timing marker.

4.16.7: Pan Last View Menu Selection

The AnalyzerPan Last View will return the Waveform Display window to the preceding view.

4.16.8: Trace Source Menu Selection

The AnalyzerTrace Source will toggle on/off the Trace Source capability for behavioral code. With the Trace Source capability, you can left mouse click on a waveform to pop up the source file, and highlight the Verilog HDL statement which caused that waveforms value.

4.16.9: Signal List Menu Selection

The submenus under the AnalyzerSignal List menu selection are the same as the context menu of Signal Name List Box of the Data Analyzer.

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4.16.10: X-Axis Menu Selection

There are Goto Timepoint, Timescale and Add Bookmark submenus under the AnalyzerXAxis menu selection.

Goto Timepoint Submenu

See Section 4.9.1: Data Analyzer X-Axis Area and Goto Timepoint Menu Selection.

Timescale Submenu
See Section 4.9.3: Timescale Menu Selection.

Add Bookmark Submenu

See Section 4.9.4: Add Bookmark Menu Selection.

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4.17: Debug Menu

The Debug menu provides the following menu selections: Go menu selection Break menu selection Step menu selection Finish Current Timepoint menu selection LoadReload Input Files menu selection Reload and Go menu selection Restart Simulation Data Tips menu selection Data Tip Radix Enable Single StepBreakpoints menu selection View Breakpoints menu selection Insert/Remove Breakpoints

4.17.1: Go Menu Selection

The DebugGo menu selection starts simulation. The Go button is also available on the toolbar. When Go is selected the files specified for the project are automatically input into SILOS (unless they have already been input). Simulation is then run until a $stop or $finish is encountered in the design. During simulation, the Go button will change into a Break button, which can be clicked on to halt the simulation at any time. The Go button can be useful during single stepping to skip across uninteresting source code to the next breakpoint, at which point the single stepping can be resumed.

4.17.2: Break Simulation Menu Selection

The DebugBreak menu selection will stop the SILOS simulation. Holding down the Escape key (Esc) on the keyboard or the clicking on the Break button on the toolbar performs the same function.

4.17.3: Step Menu Selection

The DebugStep menu selection single steps through the HDL source code for the project. As SILOS single steps it places a yellow arrow to the left of the line. Single stepping can be very useful when combined with breakpoints and the Watch window for debugging behavioral code. As you step through the HDL source code you can highlight variables and expressions, and drag and drop them into the Data Analyzer window and the Watch window. The toolbar also has a Step button.

4.17.4: Finish Current Timepoint Menu Selection

The DebugFinish Current Timepoint menu selection is used to continue the simulation until the end of the current timepoint. This is useful to complete the time step during single-stepping so that the Data Analyzer waveforms are updated.

4.17.5: Load/Reload Input Files Menu Selection

The DebugLoadReload Input Files menu selection automatically resets SILOS and inputs the files specified for the project.

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4.17.6: Reload and Go Menu Selection

The DebugReload and Go menu selection automatically resets SILOS, inputs the files specified for the project, and then runs simulation until a $stop or a $finish system task is encountered, or until you select the Break button on the toolbar.

4.17.7: Restart Simulation

This starts the simulation from time zero.

4.17.8: Data Tips

This enables or disables the data tip display.

4.17.9: Data Tip Radix Menu Selection

With DebugData Tip Radix menu selection, you can change the radix of the value displayed in Data Tips. It has Binary, Octal, Hex, Decimal, String, Symbol and Real submenus.

4.17.10: Enable Single Step/Breakpoints Menu Selection

The DebugEnable Single StepBreakpoints menu selection turns on or off the single stepping capability, and the breakpoints capability. The advantage of turning of the debugging would be to increase simulation speed, perhaps by as much as 25%.

4.17.11: View Breakpoints Menu Selection

The DebugView Breakpoints menu selection opens the Breakpoints dialog box for setting breakpoints. A typical method to debug a design using breakpoints would be to set a breakpoint in a module instance, then click the Go button on the toolbar and simulate until the simulation stops in the module with the breakpoint. Next, single step through the module to review how the source code is executing, and watch variables change value in the Watch and Data Analyzer window. The Go button could then be used again to simulate until the simulation stops in the module and singlestepping is resumed. There are four types of breakpoints:

Break at Simulation Time

The Break at Simulation Time selection allows you to specify a simulation time and stops the simulation before the specified time is simulated. To specify a stop time, select Break at Simulation Time in the Type box and enter the stop time in the Timepoint box. Then click the Add button.

Break at Location
The Break at Location selection stops logic simulation before the selected source line is simulated. To select a breakpoint location, you can use the Toggle Breakpoint feature in text editor, or you can use the Breakpoints dialog box. To use the Toggle Breakpoint feature, first open a source file window by single-stepping with SILOS, or use the FileOpen menu selection or Open button on the toolbar to open the source file window. Simply click in the area to the left of the line next to the line number. A red stop sign symbol will be placed to the left of the line next to the line number. You can also see that the breakpoint has been set in the Breakpoints dialog box. Click in the area one more time will delete the breakpoint.

Break in Module Instance

The Break in Module Instance selection allows you to select a module instance and then stop simulation each time a source line in the selected module instance is to be simulated. To select a breakpoint location, use the Explorer window to highlight the module instance you want to select. 4-70 Silvaco, Inc.

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Right mouse click on the module instance, select the Copy Scope in the context menu. In the Breakpoints dialog box, select Break in Module Instance for the Type box. Right mouse click in Scope box and select paste. The corresponding module instance name will appear in the Scope box. Next, press the Add button to add the name of the module instance to the list of breakpoints.

Break in Module (Any Instance)

The Break in Module (Any Instance) selection allows you to select a module instance and then stop simulation each time a source line in any instance of the module is to be simulated. To select a breakpoint location, use the Explorer window to highlight the module instance you want to select. Right mouse click on the module instance, select the Copy Scope in context menu. In the Breakpoints dialog box, select Break in Module (Any Instance) for the Type box. Right mouse click in Scope box and select paste. The corresponding module instance name will appear in the Scope box. Next press the Add button to add the name of the module instance to the list of breakpoints. The Add button adds the specified breakpoint to the Breakpoints list. Active breakpoints are preceded by a plus (+) sign. Inactive breakpoints (Disable button) are preceded by a minus (-) sign. Individual breakpoints can be deleted with the Delete button. All breakpoints can be deleted by the Clear All button. The OK button closes the Breakpoints dialog box and saves the changes. The Cancel button closes the Breakpoints dialog box without saving the changes.

4.17.12: Insert/Remove Breakpoint Menu Selection

The DebugInsertRemove Breakpoint menu selection is used to insert or remove line breakpoints in source window. Open a source file in text window, and put the cursor to the line where you want to set the breakpoint. Clicking the menu selection will insert a breakpoint at the line in the current file. Click one more time will remove the breakpoint.

4.18: Explorer Menu

The Explorer menu has the following menu selections: Tree menu selection List menu selection

The Tree menu selection has submenus, which are the same as the context menu the left window of the Explorer. The List menu has submenus, which are the same as the context menu of the right window of the Explorer.

4.19: Reports Menu

The Reports menu provides the following menu selections: Activity Reports menu selection Inactivity menu selection Toggle menu selection Export Activity Data menu selection

Errors and Warnings menu selection Iteration menu selection Nonconvergence menu selections Sizes menu selection Enable Code Coverage menu selection Merge Operator Coverage menu selection

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Export Code Coverage Data menu selection Line Report menu selection Operator Report menu selection

4.19.1: Activity Reports Menu Selection

Inactivity and Toggle Menu Selection
The ReportsActivity ReportsInactivity menu selection can be used to pre-grade the test vectors for fault simulation by reporting nodes that have no activity (level transitions) during a logicsimulation. Using the Inactivity report to pre-grade test vectors saves time because logic simulation is much faster to run than fault simulation. The Inactivity report is useful because faults at nodes which make no level transitions can not be detected. The Inactivity menu selection can be used to generate the following report: An activity table that lists the node names of nodes that do not transition. An activity summary that lists totals for the number of nodes at each level of activity count. An activity histogram that shows known and potential level transitions versus time.

For the activity table for the Inactivity report, you will see the following legend: Legend for TRANSITION COUNT column: The legend is stating that a value is reported to the left of a node name. A definite transition is defined as a change from a Low to High level or High to Low level, even if it goes through an intermediate Unknown level. A possible transition is defined as a change from a High or Low level to the Unknown level, or from the Unknown level back to a High or Low level. An H reported to the left of the node name, means the node never had a definite transition, and the node was High at the time specified as the minimum time for the time range for the report. The default minimum time is time=0. An L reported to the left of the node name means the node never had a definite transition, and the node was Low at the time specified as the minimum time for the time range for the report. For the summary, the percentages are based on the nodes listed that are within the range specified for the Inactivity report. The default range is zero transitions for the maximum and minimum number of transitions. The default is zero because the purpose of the Inactivity report is to report nodes that did not toggle for fault simulation. The ReportsActivity ReportsToggle menu selection can be used to report which nodes have activity (level transitions) during a logic-simulation. The Toggle report can be useful to show which parts of the design have a high activity, which may indicate a problem in the design: value: number of definite transitions (value): number of possible transitions H: no definite transitions, node High at Min time specified L: no definite transitions, node Low at Min time specified

Section 4.19.1: Activity Reports Menu Selection provides a report of the nets that do not toggle for use with fault simulation. The Toggle menu selection can be used to generate the following report: An activity table that lists the node names of nodes that transition. An activity summary that lists totals for the number of nodes at each level of activity count. An activity histogram that shows known and potential level transitions versus time.

For the activity table for the Toggle report, you will see the following legend: Legend for "TRANSITION COUNT" column:

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The legend is stating that a value is reported to the left of a node name. A definite transition is defined as a change from a Low to High level or High to Low level, even if it goes through an intermediate Unknown level. A possible transition is defined as a change from a High or Low level to the Unknown level or from the Unknown level back to a High or Low level. An H reported to the left of the node name, means the node never had a definite transition, and the node was High at the time specified as the minimum time for the time range for the report. The default minimum time is time=0. An L reported to the left of the node name, means the node never had a definite transition, and the node was Low at the time specified as the minimum time for the time range for the report. For the summary, the percentages are based on the nodes listed that are within the range specified for the Activity report. The default range is zero transitions for the minimum number of transitions and 2147483647 for the maximum number of transitions. The ReportsActivity ReportsExport Activity Data menu selection (Figure 4-55) can be used to generate an activity data file to save node transition count data that can be merged into the activity table data from later simulations. The activity data file format is similar to the VCD file format and can be included in an Activity report (see Section 6.3: Activity Command). An activity data file can also be created by including the $dumpactivity(<filename>) system task in the Verilog source code (see Section E.7: $dumpactivity System Task Extension).

Figure 4-55: Export Activity Data Menu Selection

4.19.2: Errors and Warnings Menu Selection

The ReportsErrors and Warnings menu selection reports the errors that occurred during read-in, preprocessing or simulation. An error level of 1 indicates a warning. Error levels 2 through 5 will prevent simulation until the error has been corrected.

4.19.3: Iteration Menu Selection

The ReportsIteration menu selection is useful for finding zero delay loops, race conditions and order of evaluation problems. This menu selection displays every signal that has more than one iteration at a timepoint from time=0 to the current timepoint.

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4.19.4: Nonconvergence Menu Selection

The ReportsNonconvergence menu selection generates a report of any nonconverged nodes and their oscillating states for the time point that nonconvergence occurred. The Nonconvergence menu selection can only be used to debug nonconvergence in gate level designs. For behavioral level designs, the Nonconvergence menu selection will produce a report that states there is no data to report. To debug nonconvergences for behavioral designs, see Section 4.19.6: Nonconvergence (Hanging) for Behavioral Designs. value: number of definite transitions (value): number of possible transitions H: no definite transitions, node High at Min time specified L: no definite transitions, node Low at Min time specified

4.19.5: Nonconvergence For Gate Designs

The ReportsNonconvergence menu selection reports the following information: Names of the unresolved devices and nodes. The type of device and node as either a .type data keyword, NODE for a wired connection with at least one bi-directional device, or BUS for a wired connection between two or more unidirectional enabled gates. The node state values for the nonconvergence time point. State values reported are preceded by a ... to indicate possible previous states.

Nonconvergence only occurs when gate delays are zero. Zero delays can cause the circuit to oscillate at a single timepoint. As the circuit oscillates, the simulator must iterate over the circuit trying to resolve the circuit to a single set of values. When the iteration limit is exceeded, the circuit has nonconvergence. A simple example of a circuit that would cause nonconvergence is a ring of three inverters whose delays are set to zero. Zero-delays occur during logic simulation when either a zero delay, or no delay is specified for devices (the default delay for Verilog HDL gate devices is zero). Zerodelays also occur during logic initialization (LINIT command), which forces delays to be zero so that SILOS can perform a steady-state, DC solution of the circuit at time=0. Nonconvergence may be due either to circuit path length, or problems with designs involving feedback. To eliminate oscillations caused by problems involving feedback, the circuit design must be corrected. When nonconvergence is due to path length, increasing the iteration limit should enable the circuit to converge. In general, each node in a serial path length requires one iteration to propagate a signal. The iteration limit during simulation is specified by the .CONTROL .MXITR command. The iteration limit at time=0 is specified by the .CONTROL .MXDCI command. Arbitrarily increasing the iteration limits is not recommended as it may dramatically increase the execution time necessary to reach nonconvergence. To debug a nonconvergence due to a problem in the circuit design, you will need to use the NONCONV command to store the nonconvergence report (see Section 6.20: No Convergence Summary). Many times an important clue in solving a nonconvergence is to know which signal started oscillating first. The probe command can be used to find out which signal started oscillating (see Section 6.23: Probing Node States). Use following steps to debug your circuit: In the Command window for the Main toolbar, enter the disk command to name an output file, such as: disk file1 Then, in the Command window for the Main toolbar, enter the nstore nonconv command to store the nonconvergence report in file1. Next, edit file1 and copy and paste the net names from the nonconvergence report to another file (file2) that you have the probe command in, for example:

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!probe iter time1 time_end net1,,net2,,net3 where time1 is the timepoint before the nonconvergence, and time_end is the nonconvergence timepoint. If the net names use the SILOS style ( to delimit hierarchy, then you will have to change the ( to .. Then, in the Command window for the Main toolbar, prompt the input file that has the !probe command: input file2 From the probe report, determine which net is oscillating first. Next, open the Data Analyzer and the Explorer window. In the Explorer window, select the signal that was first oscillated and drag and drop it to the Data Analyzer. Then highlight the signal in the Data Analyzer and use the Trace Inputs menu to trace backwards from the net that started oscillating so that you can draw the circuit for that net and figure out the cause of the nonconvergence.

The Nonconvergence menu selection only reports the basic options for the nonconvergence report. For additional options, such as the INPUT option that reports the states for all inputs of devices which drive the oscillating nodes, and the ITER=val option that specifies the iteration number to the 1st of eight states for each node reported for nonconvergence, see Section 6.20: No Convergence Summary.

4.19.6: Nonconvergence (Hanging) for Behavioral Designs

When nonconvergence occurs in behavioral designs, SILOS may be able to stop the simulation and report an error stating that there has been nonconvergence. For nonconvergence during behavioral simulation, the ReportsNonconvergence menu selection report may produce a report that states there is no data to report. When this happens, you can click on the Step button on the Main toolbar, and immediately begin to single step in the no converged source code. Infinite loops in your behavioral code can cause SILOS to hang and not respond. When the infinite loop occurs at time=0 SILOS will hang and never get to the Ready: prompt. When the infinite loop occurs during simulation, SILOS will hang and does not respond to the STOP button, or holding down the Esc key on the keyboard. Different techniques are used to debug hangs at time=0, and hangs during simulation. When SILOS hangs at time=0, and the Output window never displays the Ready: prompt, this is usually due to an error in the behavioral code in an initial or an always block. The following example hangs at time=0 due to the incorrect code i=+1 which should be i=i+1 in the below for loop: module hang_at_0; reg a; integer I; initial for (i = 0; i < 10; i = +1) a = ~a; endmodule To debug a design that hangs at time=0, use comments /* */ to comment out portions of the design until it no longer hangs at time=0. Then inspect the commented code and fix the problem in the behavioral code. When SILOS hangs during simulation the program will not respond to the STOP button or holding down the Esc key on the keyboard. User errors in behavioral code are usually what cause SILOS to hang. These errors are usually caused by a loop with no delay, such as in these code segments:

Code Segment 1
for (i = a; b < c; i = i + 1) begin if (d & 9'h100) == 0) begin b = b + 1; end

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end

Code Segment 2
always @a b = ~b; always @b a = ~a; Code Segment 1 hangs when the if test is not true, causing the for loop to infinitely loop at a time step. Code Segment 2 hangs because each always block is triggering the other always block, and neither always block has delay. To debug a hang during simulation, run the simulation until it hangs, and then note the simulation time value on the status bar in the lower right-hand corner of SILOS. Next, kill and restart SILOS, and press the Load/Reload Files button. When SILOS stops at time=0, enter a simulation time to one less then when the simulation hangs in the Command window for the Main toolbar. For example, if the simulation hangs at time=11251ns, enter sim 11250ns so that SILOS stops just before it hangs. Then press the Step button. Keep single-stepping until you find the problem code. If you single-step past the time point where the simulation was hanging, then the time value for the status bar had not yet been updated when SILOS hung. To find the true time value that SILOS hangs at, keep entering short simulation times at the Ready: prompt until the simulation hangs, such as entering sim 10ns or sim 1ns until the simulation hangs. Then restart SILOS, re-simulate to just before the simulation hangs, and single-step until you find the problem.

4.19.7: Sizes Menu Selection

The ReportsSizes menu selection reports the memory usage for SILOS. The memory usage will increase during circuit read-in and preprocessing until simulation starts at time=0. After the simulation starts, the memory usage remains constant. The Code Coverage Plug-in feature reports behavioral lines that did not execute, and operators that are not fully exercised. Code Coverage provides a fundamental functional analysis of the design, it is limited to basic Verilog language constructs, such as behavioral operators, behavioral blocks, and executable lines of code in the design. Code Coverage examines the test bench's ability to fully exercise these language constructs. For example, in the Verilog expression (a | b) which has single bits a and b, Code Coverage examines if the | operator is fully exercised during testbench application. Each operand at some time must individually produce a 1 result, and both operands at some time must be 0 to produce a 0 result.

Code Coverage vs. Fault Simulation

Use Code Coverage to improve your testbench, and report if the language components of your design are fully exercised by the testbench. For example, Code Coverage reports on whether a bit-or | operator and its associated operands are fully exercised by the testbench. Because the Verilog language supports hierarchal constructs, many instances of each operator can be used. However, Code Coverage reports only if all uses combined have fully exercised the operator. Code Coverage does not report on each specific instance of an operator. Fault Simulation should be used to tell you if each operator is fully exercised, and if your testbench would detect chip failures due to specific chip defects.

4.19.8: Enable Code Coverage Menu Selection

The ReportsEnable Code Coverage menu selection enables the saving of line coverage information to an ASCII file project_name.codecov, where project_name is the name of your current project. The project_name.codecov file is then used by the Line report after simulation. The Code Coverage button on the Main toolbar is a shortcut to the Code CoverageEnable Code Coverage menu selection. Code Coverage must be selected before logic simulation begins, such as when you first open a project. If the Code CoverageEnable Code Coverage menu selection or the

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Code Coverage button is selected at simulation time=0 or later, a message box will notify you that the project files will be automatically reloaded before code coverage is set.

4.19.9: Merge Code Coverage Files Menu Selection

The ReportsMerge Code Coverage Files menu selection can be used to merge the code coverage results from simulations using the same design. This option merges the ASCII files project_name.codecov, where project_name is the name of each project. If you do not change the project name for each simulation, then you need to rename the project_name.codecov file before simulating each testbench. The ReportsMerge Code Coverage Files menu selection opens the Select files to merge dialog box. This dialog box is additive, so you can select more than one code coverage results file before closing the dialog box, and you can use this dialog box more than once to add additional code coverage results files. For an example on using this feature, see Section 3.8.3: Merging Code Coverage Reports.

4.19.10: Export Code Coverage Data Menu Selection

The ReportsExport Code Coverage Data allows you to export the code coverage reports to a spread sheet program such as Microsoft Excel. When this menu item is selected, the Export Code Coverage Data dialog pops up, which has options, the type of report, as well as comma or tab separated data. You can also use the ccexport command to export code coverage results.

4.19.11: Code Coverage Line Report Menu Selection

The ReportsCode Coverage Line Report menu selection opens the Code Coverage Line Report list box. This list box reports the execution of individual lines. For example: Module/Task/Function | Hits | Line Number | File Name Alu | 10 | 24 | foo.v Clicking on a heading will sort the displayed lines. If you click on one of the entries in the list box, SILOS will automatically open the source file, and highlight the line of behavioral code. Lines that are not executed have a red text box to the left of the line. Lines that are executed have a green text box to the left of the line. Holding the mouse cursor over a green text box will show the number of times that the line was executed.

4.19.12: Branch Coverage Report Menu Selection

The ReportsBranch Coverage Report menu selection opens the Branch Coverage Report list box. This list box reports the execution of if , case and statements containing ternary (conditional) operators1. The data columns in the report are Module Name, Line Number, File Name, Branch Type, Pass/Fail, Hits, True and False. The pass or fail flag for a branch statement is set depending on the statement type. Statements containing ternary and if statements must be executed at least once with the condition true and once with the condition false and case selectors must be executed at least once to marked as passing. For example: Module | Line | File Name | Branch Type | Pass/Fail | Hits | True | False Alu | 10 | foo.v 24 | Ternary | Pass | 5 | n/a | n/a Clicking on a heading column will sort the displayed lines. If you click on one of the entries in the list box, SILOS will automatically open the source file, and highlight the line of behavioral code. Lines that have incomplete branch coverage have a red text box to the left of the line. Lines that have complete 1. See Verilog LRM IEEE-1364, Section 4.1.13 Conditional Operator for further information on conditional/ternary operators. Silvaco, Inc. 4-77

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coverage of branch conditions have a green text box to the left of the line. Holding the mouse cursor over a text box will show the number of times that the line was executed or the cause of the branch coverage failure.

4.19.13: Code Coverage Operator Report Menu Selection

The ReportsCode Coverage Operator Report menu selection reports exercising of each operator. Only operators which have been executed are reported. Use the line report to locate lines containing operators that have not been executed. Clicking on the heading will sort the contents displayed as follows. If you double click on one of the entries in the list box, SILOS automatically opens the source file and highlights the corresponding line. Lines where an operator fails have a red text box to the left of the line. Lines that have no operators that fail have a green text box to the left of the line. Holding the mouse cursor over the red text box shows one operator that failed on the line. For example: Module/Task/Function | Line Number | File Name | Fails | Operator Failure Cause Alu | 10 | cpu33.v | 1 | never true (1) Module/Task/Function: Alphabetically by name. Line Number: Numerically by line number then by file name. File Name: Alphabetically then by decreasing failure. Fails: Decreasing failure count. Operator: Operator then by decreasing failure count. Failure Cause: Alphabetically by cause.

Operator Coverage Options

When you select the ReportsCode Coverage Operator Report menu selection, the Select Operator Report Option/s dialog box is opened. This dialog box contains six options that determine how the Operator report is displayed. You can select one or more of these options to obtain a combined report for the operators. DEFAULT Operator 1/0 Result reports the result of the operator. For example, if the results for logical operators < and > were both true and false during the simulation, then the operator had no failures and a green text box is placed to the left of the line with the operator. If the results of the operator were only true or only false during the simulation, then the operator had a failure and a red text box is placed to the left of the line with the operator. Logic Operand Independence reports when either operand fails to independently (of the other operand) cause the operator to be true or false. Logic Operand Bit Independence reports when the operands are vectors, report when any bit in either operand fails to independently (of the other operand) cause the operator to be true or false. Bit Operand Independence reports when either operand fails to independently (of the same bit in the other operand) toggle the resulting bit. Math Result Bits reports any bit in the result never 1 or never 0. Reduction Operand Independence reports when operand bits fail to independently toggle the result.

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4.19.14: Restricting Code Coverage Analysis

There are several options which allow you to choose what code coverage analyzes. The default is to analyze all code except for code from libraries. 1. Identify the Device Under Test (DUT) to prevent Code Coverage from including your testbench in the analysis. You can add the following lines to your testbench to identify the Device Under Test: `ifdef silos initial $fs_dut(testbench.chip); `endif 2. To exclude specific lines from code coverage, enclose the lines that you do not want code coverage analyzed for with the directives (for an example, see Section 3.8.3: Merging Code Coverage Reports: `disable_codecoverage `enable_codecoverage 3. To enable code coverage of libraries, use the command line argument +libcodecoverage. The directives `disable_codecoverage and `enable_codecoverage in a library file have precedence over +libcodecoverage. 4. To exclude a module instance and every module instance below from contributing to coverage, use the command (for more information, see Section 6.6: Exclude Code Coverage for Module Instances): "!ccmexclude <verilog instance name> ..." ModuleTask/Function: Alphabetically by name. Hits: Modules with the greatest number of zero hits. Line Number: Numerically by line number then by file name. File Name: Alphabetically by name then by hit.

To include a module instance below one that is excluded, use the command (for more information, see Section 6.7: Keeping Code Coverage for Module Instances): "!ccmkeep <verilog instance name> ..." Note the instance names on these commands must proceed from the top of the design downward. To do the equivalent from the GUI explorer, select a module instance, right-mouse click and go to the properties tab dialog. Check or uncheck Save code coverage data for this entry. Note this information is written into the .cfv file to permit regression (batch) use at a later time.

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4.20: Help Menu

4.20.1: Silos Help Menu Selection
The HelpSilos Help menu selection opens the SILOS USER'S MANUAL.

4.20.2: Release Notes Menu Selection

The HelpRelease Notes menu selection open the release notes for the current version of SILOS.

4.20.3: About Silos

The HelpAbout Silos menu selection opens the About Silos dialog box. This dialog box contains the SILOS version number, copyright notice, and corporate contact information. If you click the More Details button, a list box will appear at the bottom of the dialog. There are version numbers of the different packages used in SILOS.

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Chapter 5: Advanced Topics

This chapter covers some of the more advanced features of SILOS.

5.1: Programming Language Interface (PLI)

SILOS dynamically interfaces user written or vendor supplied Programming Language Interface (PLI) routines with the SILOS executable at runtime. Interfacing the PLI routines at run time has the

following advantages: You do not have to create a new SILOS executable, or have a different executable for each set of vendor supplied PLI routines. Dynamically linking the PLI routines at runtime is faster than having to recompile and create a new executable each time. Upgrading to new versions of SILOS is simple because there is no need to recompile and create a new executable.

The PLI can be used with SILOS on Windows and Linux. Contact Silvaco for an updated list of supported platforms.

5.1.1: Silos PLI Interface on the Windows

To use PLI on the Windows platform: You may need a C compiler, such as the MS Visual C++ compiler, to compile any user written PLI routines and to create a .dll file to link with SILOS. Create one or more .dll files that contain the object code for the PLI. The object code must have been compiled for the type of platform you are using. For example, object code from Sun will not work on Windows. The SILOS pliload command is used to specify the .dll files for SILOS at runtime. The pliload command is cumulative so that one or more pliload commands is allowed before starting simulation. The pliload command can be entered in the Command window for the Main toolbar, from the SILOS command line, or from a file. mypli.dll Example for entering the pliload command in the Command window for the Main toolbar.

pliload

module foo; endmodule `ifdef silos !pliload mypli.dll `endif

Entering the pliload command from a file.

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5.1.2: PLI Interface on Linux

To use the PLI: Create one or more .so files that contain the object code for the PLI. For example, to create a .so file on Linux, enter the following load command. ld -o mylib.so -dy -G *.o The SILOS pliload command is used to specify the .so files for SILOS at runtime. The pliload command is cumulative so that one or more pliload commands are allowed before starting simulation. The pliload command can be entered at the in the Command window for the Main toolbar, from the SILOS command line, or from a file. mypli.so Example of entering the pliload command at the in the Command window for the Main toolbar.

pliload

module foo; endmodule `ifdef silos !pliload mypli.so `endif

Entering the pliload command from a file.

5.1.3: List of Implemented PLI Routines

SILOS uses the IEEE 1364 Standard Verilog Hardware Description Language manual as the specification for the PLI. Many of the tf_ PLI routines for linking user C programs to SILOS have been implemented. C programs can be used for modeling a circuit or for creating test vectors. Selected acc_ PLI routines have also been implemented. Contact Silvaco for the list of implemented PLI routines.

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Advanced Topics

5.2: Standard Delay Format (SDF)

SILOS supports the SDF language as defined by the IEEE 1497 standard for SDF. SILOS also supports a commonly used extension used to specify the SDF file of delay values, the $sdf_annotate system task. Please note that the SDF file can not be input using the EditProject Properties Source Files dialog box (do not input the SDF file, it must be specified with the $sdf_annotate system task). The following contains the format specification for the $sdf_annotate system task and an example for using it to specify the SDF file.

The format specification for the $sdf_annotate system task is: $sdf_annotate(file_name, module_instance); where: file_name: Represents any valid file path and file name specification. module_instance: Represents the name of a module instance. The hierarchical path for all of the instance names in the SDF file are relative to the module_instance argument. For example, if the name top.dff1 is used for the module_instance argument, then the instance names in the SDF file are relative to top.dff1. If you omit the module_instance argument, SILOS uses the hierarchical name of the module containing the $sdf_annotate system task as the default entry for the module_instance argument.

When you run the simulation, you will see the following lines in SILOSS Output window that shows the SDF file has been read in: Beginning '$sdf_annotate(file)' into the hierarchy at 'testbench.design' Done $sdf_annotate. Where file is the name of the SDF file, and testbench.design is the hierarchical name of your design.

Note: If you have selected the Functional simulation check box for unit delays in the Project Settings dialog box for SILOS, then the SDF file is not read into SILOS, and you will not get the above message in the Output window, even though you have specified the $sdf_annotate system task.

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5.2.1: Example of SDF Annotation

The below example and diagram show how to specify the $sdf_annotate system task so that it is correctly positioned in the design's hierarchy.

Test bench

moduletestbench;

Top level of design

design name1 (ports);

mod1 name2 (ports);

mod2 name 3 (ports);

mod2 name4 (IN0, OUT);

mod1 name5 (ports);

SDF file is updating this instance

Figure 5-1: Diagram of the Design Hierarchy for the SDF Example
For the above diagram, the SDF file named filename.sdf contains the instance name name2.name4 as shown below: (INSTANCE name2.name4) (DELAY (ABSOLUTE (IOPATH IN0 OUT (2420:2420:2420) (2420:2420:2420)) The $sdf_annotate system task needed to specify the SDF file and its relative position in the above design's hierarchy would be: module testbench; initial $sdf_annotate(filename.sdf, testbench.name1); ... endmodule When SILOS reads the SDF file filename.sdf to update the design, the path testbench.name1 is concatenated with path name2.name4 in the SDF file to form path testbench.name1.name2.name4. Signals IN0 and OUT are then updated as specified above.

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Advanced Topics

5.3: Inputting Value Change Dump (VCD) Files for Stimulus

VCD files can be used to drive test benches. This is done by creating a simple testbench that instantiates the design, declares the input ports as registers, output ports as wires, and bidirectional ports with some tri-state logic whose inputs are registers. The registers are driven directly from the data in the VCD file by the PLI routine $vcdin as follows: vcdin ( <vcd-file-name>, <done> [ , <local-variable>, <vcd-hierarchal-name> ]+ ); <vcd-file_name>: Is the name of the VCD file surrounded by quotes, e.g. '"myvcd.vcd"'. <done>: Is a one bit register set to '1' when the VCD file has been read. <local-variable>: Is the name of a variable in the test bench that will be driven, e.g. clock. The local variable must be writable, e.g. register, integer, real, time. <vcd-hierarchal-name>: Is the hierarchal name in quotes from the VCD file that will drive the <local-variable>, e.g. '"test234.clock"'.

Typically, the <local-variable> will be the same data type and size as the name driving it from the VCD file. The timescale in the VCD file determines the units for time values read from the VCD file, but never increases the maximum precision determined by the source files. In the absence of a timescale in the VCD file, the time unit of the module containing $vcdin is used as the unit for time values read from the VCD file. The simulation time at which $vcdin is called determines a positive offset for time values from the VCD file.

Example
module top; reg done; reg clock; integer i; initial $vcdin(myvcdfile.vcd, done, clock, test234.clock, i, test234.ival); initial @done #100 $finish; // wait for final input to propagate endmodule Example vcd_input.spjx is provided in the examples subdirectory to demonstrate vcd input for logic simulation and fault simulation.

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5.4: Creating Smaller Save Files for Logic Simulation

SILOS is very efficient in writing the logic simulation results to the simulation history save file,

project_name.sim. The difference in simulation speed between saving everything and saving nothing is a maximum of 10%, so saving information to disk has a minimal impact on simulation speed. However, once the save file size exceeds one or two gigabytes, the waveform display in the SILOS Data Analyzer will be slower. For this reason, and if there is not enough available disk space, you can limit the size of the simulation history save file. The save file for the simulation history is only used by the SILOS GUI. The simulation history save file is not used by regression simulations, so by default it is turned off when running regression simulations. There are two strategies you can employ for limiting the size of the simulation history save file: Saving all of the simulation results for a specified time duration during simulation, such as 4,000 nanoseconds. You would use this strategy to view the simulation results near the end of the simulation. Saving selected wires and selected module instances of the design's hierarchy for the entire simulation. You would choose this strategy to view the simulation results from time=0 to the end of the simulation.

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5.4.1: Using Recirculation to Create a Constant Save File Size

A recirculating save file, similar in concept to a FIFO, can be used to keep the save file size constant. When the current simulation information is written to the save file, the earliest information in the save file is discarded, keeping the size of the save file constant. The recirculating file size is determined by setting a Recirculation start time. Once this time is reached, the save file size will remain constant. To specify the recirculating start time, select the EditProject PropertiesSimulation Data File menu selection. The Maximum File Size Options box at the right of the Project Properties dialog box contains an option to specify the recirculating start time time interval.

Figure 5-2: Set Recirculate Start Time in Project Properties Dialog

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5.4.2: Saving Selected Wires and Instances

Saving selected module instances, and/or excluding selected module instances, can be graphically specified by using the SILOS Explorer. To graphically save or exclude module instances, open the context menu in the left side of the SILOS Explorer by clicking with the right mouse button on the module instance name. Next select the Module Properties menu to open the Module Properties dialog box. When the Save simulation data for this entry in the Module Properties dialog box is enabled, SILOS will save the simulation history for every variable in that module, and for all modules below it. When the Save simulation data for this entry in the Module Properties dialog box is disabled, SILOS will not save the simulation history for any variable local to that module, nor for the modules instances below it. Port variables are still saved if the module instances above it are enabled.

Figure 5-3: Saving Simulation Data for the Instance

Saving selected wires and selected module instances of the design's hierarchy can be specified also with the SILOS keep and mkeep commands (for more information, see Section 6.16:Keeping Simulation Node States and Section 6.19:Keeping Module Instance Simulation Variable Values. You can also exclude parts of the design's hierarchy by using the SILOS mexclude command (see Section 6.13:Exclude Saving Simulation Node States). Usually you put the keep, mkeep and mexclude commands at the very top of the file that contains the testbench, or in a separate file that is read in to SILOS. An example for using these commands follows.

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Advanced Topics

To save only the variables for the testbench for the example, put the commands that follow at the top of the file containing the testbench, or in a separate file. Notice that the mkeep and mexclude commands use a left parentheses (as the SILOS style of hierarchical delimiter. `ifdef silos !control .sav=1 !mkeep (testbench !mexclude (testbench(top `endif module testbench; endmodule To save the variables in the testbench, instance top, but not for instances alu and mem, use the commands that follow: `ifdef silos !control .sav=1 !mkeep (testbench !mexclude (testbench(top(alu `endif module testbench; endmodule

(testbench(top(mem

To save individual wires in the testbench, use the commands that follow (for vectors, each bit to be saved must be specified): `ifdef silos !control .sav=1 !keep (testbench(alu(out[1] `endif module testbench; endmodule

(testbench(alu(out[2]

(testbench(alu(ir

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5.5: How to Simulate Designs that Run on Other Simulators

SILOS supports all of the standard command line arguments used by other simulators. To simulate a design that has been run with another simulator, such as NC-Verilog or VCS use the EditProject PropertiesOther SettingsCommand Line Arguments dialog box to enter the command line arguments used for the other simulator.

Figure 5-4: Other Settings Menu

5.6: Source File Encryption Using Sencrypt

Source files can be encrypted using the Sencrypt encryption utility. The program will automatically detect and decrypt these encrypted source files. Files should be encrypted using the -@ command line option. For example, the command: sencrypt -@ my_source.v my_encrypted_source.v will create an encrypted version of the file my_source.v called my_encrypted_source.v. Please refer to the Sencrypt User's Manual for detailed information regarding the use of the Sencrypt encryption utility.

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Chapter 6: Interactive Commands

6.1: Commands Overview
The Commands section contains a short overview on the interactive command syntax. Most commands are a part of the menu structure. However, a Command window has been provided in the Main output window to allow interactive commands to be entered. The command line mode (silos -b) is also provided to run SILOS for regression tests.

6.2: Stopping Processes

To discontinue or stop an interactive process when running SILOS, such as during a large report that is output to the terminal, enter: Ctrl C: simultaneously hold down the Ctrl key and the C key on the keyboard. Hold down the Esc key on the keyboard.

6.3: Activity Command

The ACTIVITY command is designed for use with gate level simulations. You can use the Code Coverage feature to obtain similar information for Behavioral HDL designs. The ACTIVITY command can be used to pre-grade the test vectors for fault simulation by reporting nodes that have no activity (level transitions) during a logic-simulation for the test vectors. The logic simulation is much faster to run than fault simulation. To obtain a node activity report, enter: TYPE STORE ACTIVITY [t1 TO t2] [ / keywrd=val, keywrd..]

TYPE STORE ... ACTIVITY t1 TO t2

Directs the activity report to standard output. Directs the activity report to a disk file (storeout) Generates a node activity report. Represent the minimum and maximum time point values for reporting node activity. This time point range must be within the logic simulation time point range. If the time points are not specified, the logic simulation times are used. (The TO keyword is optional). Represents an optional keyword used to define a condition or specify a value. The first keyword must be preceded by a slash. Allowed keywords are: Reports the activity only for nodes that are included within fault blocking. Fault blocking is controlled by the keywords .FON and .FOFF. Specifies the lower limit for reporting node activity. Only nodes which have known level transitions greater than or equal to this minimum limit will be reported (Default: MNTRAN=0). Specifies the upper limit for reporting node activity. Only nodes which have known level transitions less than or equal to this maximum limit will be printed (Default: MXTRAN=0). Represents the user-specified numerical value for MNTRAN or MXTRAN. Suppresses output of the activity versus time histogram.

keywrd BLOCK MNTRAN=val

MXTRAN=val

val NOHIST

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NOSUM NOTAB merge=filename

Suppresses output of the activity summary. Suppresses output of the node activity table. Merge activity data from a file into the activity table transition counts.

Application Notes
1. An ACTIVITY report can be very useful for developing input test patterns to detect circuit faults for fault simulation. The number of level transitions at a node indicates an input test pattern's effectiveness. Faults at nodes which make no level transitions cannot be detected. 2. The TYPE/STORE ACTIVITY command can be used to generate the following reports: An activity table that lists the node names and their number of transitions (changes in level). The only nodes listed are those whose transition count falls between the minimum and maximum number of reported transitions specified by the ACTIVITY report MNTRAN and MXTRAN values. Registers are not listed, unless they drive a gate input. The activity table lists the transition count and the node-name for each node. The Legend for the Transition Count column shows that a value is listed when the node has known (definite) transitions from a High to Low or Low to High. The value is enclosed by parenthesis if the node had possible transitions. An H is listed if the node toggled between an Unknown level and a High level. An L is listed if the node toggled between an Unknown level and a Low level. A U is listed if the node is always at an Unknown level. An activity summary that lists totals for the number of nodes at each level of activity count. An activity histogram that shows known and potential level transitions versus time.

3. A known (definite) transition is defined as a change from a Low to High level or High to Low level, even if it goes through an intermediate Unknown level. A possible transition is defined as a change from a High or Low level to the Unknown level or High-Z; or, from the Unknown level or High-Z back to a High or Low level. 4. In the activity histogram, the number of known transitions is displayed first for each bar of the histogram as a column of stars (*), and then the number of possible transitions is shown above the known transitions on each bar as a column of carats (^). For example, if the height of the column of stars for the known transitions on a bar started at zero ended at 100, then there were 100 known transitions for that bar. If the height of the column of carats for the number of possible transitions started at 100 and ended at 159, then there were 59 possible transitions for that bar. 5. The merge=filename option will read node transition counts from an activity data file that was generated from a prior logic simulation and add them to the activity table transition counts reported for the current simulation. The activity data file can be generated either by selecting the menu item ReportActivity ReportsExport Activity Data or by including the $dumpactivity(<filename>) system task in the Verilog source code. Multiple merge=filename options can be included in the ACTIVITY command and the report will include the node transition counts from all the specified activity data files in the activity table.

Examples
1. An example command to generate a merged toggle report is: activity /mxtran=1000 merge=mydata.activity 2. To store the Activity report to a file for nets that do not toggle: disk foo.out // specify file foo.out for the activity report store activity // write the activity report to file "foo.out" 3. To store the Activity report to a file to report all of the nets that toggle: disk test_toggle.out // specify file "test_toggle.out" for the report store activity / mxtran=99 // write the activity report to file "test_toggle.out" 4. The following simple circuit will be used as an example for the activity report: 6-2 Silvaco, Inc.

Interactive Commands

module foo; reg in, in_U, in1_0; wire out_L, out_H, out_U, out1_0; not (out_L,in); buf (out_H,in); buf (out_U,in_U); buf (out1_0,in1_0); initial begin $display("\t\ttime \tin \tin_U \tin1_0 \tout_L \tout_H \tout_U \tout1_0"); in = 1'bx; in_U = 1'b1; in1_0 = 1'b1; #10 in = 1'b1; in_U = 1'bx; in1_0 = 1'bx; #10 in = 1'bx; in_U = 1'b1; in1_0 = 1'b0; #10 in1_0 = 1'bx; #10 in1_0 = 1'b1; #10 $finish; end always @(in or in_U or in1_0 or out_L or out_H or out_U or out1_0 ) $display($time,"\t",in , "\t",in_U , "\t",in1_0 , "\t",out_L , "\t",out_H , "\t",out_U , "\t",out1_0); endmodule `ifdef silos !mkeep (foo // save only the part of the design that is faulted !control .sav=1 // save only what is specified to be saved ("!mkeep") !sim !activity // report all signals that do not toggle !activity / mxtran=99 // report all signals !error !exit `endif The following is a simulation output for the example: time x 0 1 10 1 10 x 20 x 20 x 30 x 30 x 40 x 40 $finish in file "N:\silos-test\try\try4.v" at line 19 26 digital State changes Simulation stopped at the end of time 50. 1 1 x x 1 1 1 1 x x 1 x 1 x x x 1 x 1 x x x 1 0 1 0 x x 1 0 1 0 0 1 x x x x 0 1 x x x x x x 1 1 in 1 in_U 1 in1_0 x out_L x out_H 1 out_U 1 out1_0

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The following report is for the !activity command in the example: //////////////////////// try4.v ///////////////////////// // // A C T I V I T Y T A B L E // // S I L O S ver Development Mon May 02 16:56:46 2005 /////////////////////////////////////////////////////////// Min Max Min Max Time = 0 Time = 50 Transitions (MNTRAN) 0 Transitions (MXTRAN) 0

Legend for TRANSITION COUNT column: value: Number of definite transitions. (value): Number of possible transitions. H: No definite transitions, node High at Min time specified. L: No definite transitions, node Low at Min time specified. TRANSITION COUNT 2) 2) 2)

( ( (

NODE-NAME H foo.out_H L foo.out_L U foo.out_U

//////////////////////// try4.v ///////////////////////// // // A C T I V I T Y S U M M A R Y T A B L E // // S I L O S ver Development Mon May 02 16:56:46 2005 /////////////////////////////////////////////////////////// Min Time = 0 Max Time = 50 Known Transitions Activity always U or L always U always U or H 1 2 3 4 5-9 10-19 20-99 99+ Total Node Count 1 1 1 0 0 0 0 0 0 0 0 4 Percent 25% 25% 25% 0% 0% 0% 0% 0% 0% 0% 0% Possible Transitions Node Count Percent

0 3 0 0 0 0 0 0

0% 75% 0% 0% 0% 0% 0% 0%

//////////////////////// 6-4

try4.v

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// // A C T I V I T Y H I S T O G R A M H I S T O G R A M // // S I L O S ver Development Mon May 02 16:56:46 2005 ///////////////////////////////////////////////////////////

15

10

* = Known transitions ^ = Possible transitions | | | + | | | | + | | | | + | ^ | ^ ^ | ^ ^ | ^ * ^ * +--------------------------------------------------\ | | | | / | 10 20 30 40 | 0 50 Time scale = 1 per bar

ACtivity done The following report is for the !activity/mxtran=99 command in the example: //////////////////////// try4.v ///////////////////////// // // A C T I V I T Y T A B L E // // S I L O S ver Development Mon May 02 16:56:46 2005 /////////////////////////////////////////////////////////// Min Max Min Max Time = 0 Time = 50 Transitions (MNTRAN) 0 Transitions (MXTRAN) 99

Legend for TRANSITION COUNT column: value: Number of definite transitions. (value): Number of possible transitions. 6-5

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H: No definite transitions, node High at Min time specified. L: No definite transitions, node Low at Min time specified. TRANSITION COUNT ( ( ( 2) 2) 2)

NODE-NAME 2 foo.out1_0 H foo.out_H L foo.out_L U foo.out_U

//////////////////////// try4.v ///////////////////////// // // A C T I V I T Y S U M M A R Y T A B L E // // S I L O S ver Development Mon May 02 16:56:46 2005 /////////////////////////////////////////////////////////// Min Time = 0 Max Time = 50 Known Transitions Activity always U or L always U always U or H 1 2 3 4 5-9 10-19 20-99 99+ Total Node Count 1 1 1 0 1 0 0 0 0 0 0 4 Percent 25% 25% 25% 0% 25% 0% 0% 0% 0% 0% 0% Possible Transitions Node Count Percent

0 3 0 0 0 0 0 0

0% 75% 0% 0% 0% 0% 0% 0%

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//////////////////////// try4.v ///////////////////////// // // A C T I V I T Y H I S T O G R A M H I S T O G R A M // // S I L O S ver Development Mon May 02 16:56:47 2005 /////////////////////////////////////////////////////////// * = Known transitions ^ = Possible transitions | | | 15 + | | | | 10 + | | | | 5 + | ^ | ^ ^ | ^ ^ | ^ * ^ * 0 +--------------------------------------------------\ | | | | / | 10 20 30 40 | 0 50 Time scale = 1 per bar ACtivity done

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6.4: Bus Contention Report

The BUSCON command reports the logic simulation time points at which more than one tri, triand, trior, trireg, tri0, or tri1 net types, or an enabled unidirectional device (bufif1, bufif0, notif1, notif0, nmos, pmos, rnmos, and rpmos devices) are simultaneously driving a node (a bus contention). To obtain a bus contention report, enter: TYPE STORE WTYPE NSTORE BUSCON [ t1 TO t2 ]

TYPE STORE ... BUSCON t1 TO t2

(Optional) Directs the bus contention report to standard output or to a disk file.

Generates a summary table of any contentions that have occurred between two time points. Represent the minimum and maximum time point values for reporting node activity. This time point range must be within the logic simulation time point range. If the time points are not specified, the logic simulation times are used. (The TO keyword is optional).

Application Notes
1. Contentions are reported only for nodes where two or more enabled unidirectional devices, or tri, triand, trior, trireg, tri0, and tri1 net types, form a wired connection (often used to form a bus). Bi-directional transistors, non-enabled gates and gates without enable lines are ignored by the BUSCON report. 2. For each contention, the BUSCON command reports the starting and ending time points, the starting and ending node states, and the names of the enabled unidirectional devices or tri, triand, trior, trireg, tri0, and tri1 net types connected to the node.

Examples
TYPE BUSCON nst busco 2K 100K

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6.5: Exporting Code Coverage Results

The ccexport command can be used to export code coverage results to other programs, such as Microsoft Excel. The format for the ccexport command is: ccexport /report_type /operator_report_options /delimiter_option filename

ccexport /report_type

/operator_report_options

/delimiter_option

filename

Specifies exporting of code coverage results for use with another program. report_type can be either /line, which specifies to export a line report, /branch which specifies a branch coverage report or /oper, which specifies to export an operator report. The default is to specify a line report. Only one of these three options can be specified for a ccexport command. Additional options can be specified for operator report. These options are described in Section 4.19.13:Code Coverage Operator Report Menu Selection. /default_operator_result /logic_operand_independence /logic_bit_independence /bit_operand_independence /math_result_bits /reduction_operand_independence The delimiter_option can be either /comma, which specifies a comma delimited report, or /tab, which specifies a tab delimited report. The default is to specify a comma delimited report. Represents the file name the exported results are written to. The default is to write the exported results to standard output.

Example
To specify the ccexport command from a file, enter: !sim !ccexport /line /tab test.out

To specify the ccexport command from the command line, enter: !sim -"!ccexport /line /tab test.out"

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6.6: Exclude Code Coverage for Module Instances

The ccmexclude command disables code coverage for the specified module instance and every module instance below it. The format for the ccmexclude command is: ccmexclude mname ... mname

ccmexclude mname

Specifies module instances that will be disabled for code coverage and any module instance that is hierarchically below the disabled module instance. Represents the name of a module instance in Verilog HDL syntax. The instance names on these commands must proceed from the top of the design downward.

Application Notes
1. The ccmexclude command can be used to specify module instances for which code coverage results are excluded. 2. The effects of the ccmexclude command is cumulative. 3. The equivalent of the ccmexclude command can be specified from the GUI using the SILOS Explorer. To do this, select a module instance, right-mouse click and select to the Properties menu selection. In the Module Properties dialog box, check or uncheck the option Save code coverage data for this entry. Note this information is written into the .cfv file to permit regression (batch) use at a later time.

Example
To specify the ccmexclude command from a file, enter: !ccmexclude !sim m1.alu m1.cpu

To specify the ccmexclude command from the command line, enter: "!ccmexclude m1.alu m1.cpu " -!sim

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6.7: Keeping Code Coverage for Module Instances

The ccmkeep command enables code coverage for the specified module instance and every module instance below it. The format for the ccmkeep command is: ccmkeep mname mname ... mname

ccmkeep mname

Specifies module instances that will be enabled for code coverage and any module instance that is hierarchically below the enabled module instance. Represents the name of a module instance in Verilog HDL syntax. The instance names on these commands must proceed from the top of the design downward.

Application Notes
1. The ccmkeep command can be used to specify module instances for which code coverage results are enabled. 2. The effects of the ccmkeep command is cumulative. 3. The equivalent of the ccmkeep command can be specified from the GUI using the SILOS Explorer. To do this, select a module instance, right-mouse click and select to the Properties menu selection. In the Module Properties dialog box, check or uncheck the option Save code coverage data for this entry. Note this information is written into the .cfv file to permit regression use at a later time.

Example
To specify the ccmkeep command from a file, enter: !ccmkeep !sim m1.alu m1.cpu

To specify the ccmkeep command from the command line, enter: "!ccmkeep m1.alu m1.cpu " -!sim

6.8: Merge Code Coverage Results

The ccmerge command can be used to include code coverage data from a prior simulation of the same design with the current code coverage results.

Note: The code coverage data is saved to an ASCII text file with the default name save.codecov in the batch mode or projectname.codecov for the GUI mode.

The format for the ccmerge command is: ccmerge filename ... filename

ccmerge filename

Specifies merging of prior simulation code coverage data with the current code coverage results. Represents the file name of the prior simulation code coverage data to be merged with the current code coverage results.

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Example
To specify the ccmerge command from a file, enter: !sim !ccmerge test1.codecov To specify the ccmerge command from the command line, enter: !sim -"!ccmerge test1.out"

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6.9: Control Parameters For Logic Simulation

The CONTROL command enables you to modify the parameters that control logic simulation. The general format of the CONTROL command is: CONTROL .COMMENT=c .DISABLECACHE .EUNK=val .MXRECUR=val .SAVCELL=val .SYNONYM=val .CUSTREPORT .DMIN .MXITR=val .NONCON .SAVSIM=val .TPS=qual .DISK=val .DMAX .MXDCI=val .RECIRCULATE .SKIP=val .XL_ORDER=val

val val c string CONTROL .COMMENT .CUSTREPORT .DISK Represents the numerical value assigned to the control parameter. Represents a single character. Represents the prompt string. Indicates that the default simulation control parameters are to be modified. Specifies the comment character. (Default:.COMMENT=$) Specifies that the save-file will be used in a Custom Report. (Default: not specified) Assigns the approximate limit of disk storage in bytes that the simulation save-file can use. When the disk storage limit is exceeded, the simulation will terminate. (Default: .DISK=100M) Specifies that the maximum delay value will be used when parsing the netlist. Specifies that the minimum delay value will be used when parsing the netlist. Turns on/off the caching mechanism for the Data Analyzer. Turning off the caching may reduce the RAM memory used by SILOS, however, it may make the Data Analyzer slower. The cache is used to remember in RAM memory the simulation data that you have viewed with the Data Analyzer. For example, if you do a zoom full, then every change for the displayed signals is stored in memory. If you then zoom in or zoom out for these signals, the redraw time is much faster. If you add additional signals to the Data Analyzer, then the simulation data for the new signals has to be read from the simulation history save file on disk. Defines the conductance for bi-directional transistors and unidirectional transfer gates when there is an Unknown level on the enable: on when .EUNK=1, off when .EUNK=0 or Unknown when .EUNK=*. (Default: .EUNK=*) When no convergence is detected, the default is for SILOS to issue a warning message, pick a possible solution if this is possible, and continue simulation. If the CONTROL .NONCON command is entered before logic initialization begins, then if no convergence is detected, SILOS will issue an error message and stop the logic simulation. Assigns the maximum allowed iterations for each pass during LINIT. (Maximum: .MXDCI=9999) (Default: .MXDCI=100) assigns the iteration limit to reach convergence for each logic simulation time point. (Maximum: .MXITR=100000) (Default: .MXITR=300)

.DMAX .DMIN .ENABLECACHE/ .DISABLECACHE

.EUNK

.NONCON

.MXDCI .MXITR

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.MXRECUR .RECIRCULATE=val

.SAVCELL

.SAVSIM

.SAVSIM=0 .SAVSIM=1

.SAVSIM=2

.SAVSIM=3 .SYNONYM

.SKIP

.TPS .XL_ORDER=val

Increases the parsing depth limit for recursively invoked modules for the generate statement (Default = 32.) This option specifies the maximum time interval for saving the simulation history results. When the simulation time exceeds this interval, the new simulation results are saved and the earliest simulation results are discarded so that the save file interval and file size on disk stay relatively constant, very much like a FIFO. The interval can be specified in time units, such as 100ns for 100 nanoseconds, i.e.: !control .recirculate=100ns. Causes SILOS to not save (.SAVCELL=0) or to save (.SAVCELL=1) the simulation history for variables listed between the `celldefine and `endcelldefine compiler directives. Caution: Saving all variables between `celldefine and `endcelldefine compiler directives may slow down simulation and create larger save files on disk. (Default: .SAVCELL=0) sets the logic simulation save option to determine which simulation node state changes are saved on the SAVE disk file. The .savsim option must be specified before simulation begins (Default: .SAVSIM=0) Specifies that no simulation node values are to be saved. This has limited use, as no data is available. Specifies that node simulation values (logic-type, integer-type and doubletype) are to be saved only for nodes named in the TABLE, PLOT, GNAME, TESTER, KEEP, MKEEP, HEX and OCT commands. Output results can be obtained only for the saved nodes. This option decreases simulation disk file size and reduces execution time. Specifies that all logic-type simulation node states are to be saved for all nodes in the circuit. This option prevents saving integer and floating-point values. Specifies that all (logic-type, integer-type and double-type) simulation node values are to be saved. Output values can be retrieved for any network node. Causes SILOS to retain the hierarchical node names (synonyms) in addition to the real node name for the upper-most level that the node is connected to in the hierarchy. When all synonyms are saved, SILOS will recognize the hierarchical name as well as the real name to each node in the design. Caution: Saving all synonyms may slow down input parsing and memory usage may go up (Default: .SYNONYM=1). .SYNONYM=0 don't save synonyms. .SYNONYM=1 save all synonyms. Causes SILOS to set a skipped port to a level. The default level is High-Z unknown. An allowed level is ground for compatibility with VCS (!control .skip=.gnd). (Default: .SKIP=.gnd) Specifies the default command for redirecting report outputs to standard output or disk file. Allowed qualifiers are: TYPE, WTYPE, STORE, NSTORE. Specifies a switch so that the order of evaluation for always blocks is the same order as for Verilog-XL, where val is 1 for xl_order being on (the same as Verilog-XL) and 0 for xl_order being off (default). This switch may be useful for obtaining the same simulation results as Verilog-XL. This option must be parsed before any modules are parsed. An example would be the order of evaluation for: always @posedge clock .. always @posedge clock ..

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Application Notes
1. When the disk storage limit (set by .CONTROL .DISK) is exceeded during logic, the simulation will stop. A message will be displayed showing the last simulation time point. To continue the simulation, you can increase the disk limit and re-enter the SIMULATE command. Another method would be to report the simulation results, enter RESET SAVFILE to clear the disk file save.sim (saves the simulation history) and then continue from the last simulation time point. RESET ERRORS must be entered before continuing the simulation. 2. .DMAX and .DMIN will not both affect the same simulation. The one that is specified last will remain in effect for all netlist parsing and subsequent SIMULATE commands. The .DMAX or .DMIN scaling factor should be specified before inputting the netlist so that the netlist is parsed correctly. 3. If .CONTROL .EUNK=* has been defined and there is an Unknown level on the gate's enable, MOS transistors will have an uncertain conductance and interval logic will be used to resolve their source and drain. Transfer gates also have an uncertain conductance and their output will be resolved using interval logic. For tri-state gates, the output level will be set to Unknown. The output strength will be defined by the gate definition for a tri-state gate. 4. When the iteration limit is exceeded for .CONTROL .MXDCI or .CONTROL .MXITR, a no convergence error stops execution. No convergence may be due either to circuit path length or problems with designs involving feedback. To eliminate oscillations caused by problems involving feedback, the circuit design must be corrected. When no convergence is due to path length, increasing the iteration limit should enable the circuit to converge. In general, each node in the serial path length requires one iteration to propagate a signal. Arbitrarily increasing the iteration limits is not recommended as it may dramatically increase the execution time necessary to identify oscillating nodes. 5. The NONCONV command can be used to identify which parts of the circuit have caused a logic initialization or logic simulation to stop executing.

Examples
!con .mxd=200 .mxp=200 CON .DISK=2M .MXOSC=30 .EUNK=*

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6.10: Default Device Delay Times

Normally, if a device has no delay specification, the delay times default to zero. The DELAY command allows you to globally redefine the default values. When this command is used, the back annotation of SDF delays is disabled. Default delay times are specified as follows: DELAY .DEFAULT = d1, d2

DELAY .DEFAULT d1 d2

Indicates a default delay time specification. Indicates that the default times for all unspecified delays are to be assigned. Normally, the default delays are d1=d2=0. Represents the nominal rise delay time where: d1 must be an integer between 0 and 1000 Represents the nominal fall delay time where: d2 must be an integer between 0 and 10000

Examples
!DEL !del .DEF = 16,5 .default=0, 0

6.11: Disk File Name Reassignment

The DISK command enables you to change the default file name for the STORE/ NSTORE commands. To change the STORE/NSTORE disk file name, enter: DISK filename

DISK filename

Changes the STORE/NSTORE disk file name. If no file name is specified, the program will tell you the name of the present default disk file name. Represents the name of the disk file to which stored (STORE) output will be written. (Default: filename= store.out)

Application Notes
1. Whenever a DISK command is specified, any stored (STORE) data will be written to that disk file until another file name is specified. 2. Each time a STORE or NSTORE command is specified, any existing data on the DISK file in effect may be overwritten (default), appended, or a new cycle will be created. 3. The file name can be unlimited in length, but must conform to the file name syntax of your operating system. For the Linux operating system, the file name is case sensitive. 4. The FILE.STO= command can also be used to change the default file name.

Examples
DISK sim.results DI PATTERN.INP

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6.12: Error Summary

When the program indicates that errors occurred during read-in, preprocessing or simulation, you should enter the t/s ERRORS command to determine their error level and type. For input errors, the line number and the input file name will also be reported. To check the errors, enter: TYPE STORE WTYPE NSTORE TYPE STORE ... ERRORS LEVEL value ERRORS [ / LEVEL=value ]

(Optional) Directs the bus contention report to standard output or to a disk file.

Reports any error and warning messages. (Optional) Indicates that only those errors with a severity level equal to value are to be output. If not specified, all errors will be output. Represents a value from 1 to 5.

Examples
STOR ERROR ty er / LEVEL=2

6.13: Exclude Saving Simulation Node States

The EXCLUDE command specifies nets whose state values will not be saved during simulation. The format for the EXCLUDE command is: EXCLUDE name name ... name

EXCLUDE name

Specifies nets whose state values will not be saved during simulation. Represents the name of a net whose state changes will not be saved during simulation.

Application Notes
1. The KEEP command can be used to specify nets whose simulation states are to be saved. The MKEEP and MEXCLUDE commands will keep and exclude all variables (including registers and memory variables) within a module or macro instance. 2. The effects to the KEEP and EXCLUDE commands are cumulative. When an identical net name is specified in more than one KEEP or EXCLUDE command, the last KEEP or EXCLUDE command will determine if the simulation states for that net are saved. 3. The KEEP, EXCLUDE, MKEEP and MEXCLUDE commands can be used with the CONTROL .SAVSIM=1 command option to save simulation state values.

Examples
CONTROL .SAVSIM=1 EXCLUDE (REG15(QBAR A15 .exclude (m1(bit0 (m1(bit1 (m1(bit4 (m1(bit5 (iobuf(pin34 (m1(bit6 (m1(bit7 (driver

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6.14: Exiting The Program

The EXIT command is used for normal exit of SILOS. To exit the program, enter: EXIT EXIT Commands the SILOS program to stop execution and exit normally.

Example
EXI Note: This command is not available GUI mode.

6.15: File Name Specification

The FILE command enables you to redefine the default file names used for the SAVE, and STORE commands. The format for the FILE command is: FILE [.SAV=filename] [.STO=filename] [.MODE=.APPEND] [.MODE=.OVERWRITE]

FILE .SAV .STO .MODE filename

Redefines the file name defaults. Changes the file name prefix save to a user specified name for all of the save files, including the save.dictionary file. Changes the file name for subsequent STORE and NSTORE commands. Specifies whether a report stored (STORE) will either append to the existing .STO file (or DISK command file) or overwrite the .STO file. (Default: .MODE=.OVERWRITE) Represents the redefined name of the file. A file name can be unlimited in length. However, the name must conform to the syntax of your operating system.

Application Notes
1. The FILE .SAV command must be entered before using a FSIM command. Do not specify a file name extension; the program will automatically provide the correct extensions. (Default: filename=SAVE) 2. The FILE .STO command is equivalent to the DISK command. (Default: filename=STORE.OUT or STORE OUTPUT)

Example
file .sav=run5

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6.16: Keeping Simulation Node States

The KEEP command specifies wires whose state values will be saved during simulation. To save state values to registers, see Section 6.19:Keeping Module Instance Simulation Variable Values. The format for the KEEP command is: KEEP name name ... name

KEEP name

Specifies wires whose state values will be saved during simulation. Represents the name of a wire whose state changes will be kept during simulation.

Application Notes
1. The EXCLUDE command can be used to specify wires to be excluded from the saved simulation results. 2. The MKEEP and MEXCLUDE commands will keep and exclude all variables (including registers and memory variables) within a module. 3. The effects to the KEEP and EXCLUDE commands are cumulative. 4. The KEEP, EXCLUDE, MKEEP and MEXCLUDE commands can be used with the CONTROL .SAVSIM=1 option.

Examples
CONTROL .SAVSIM=1 KEEP (MAC15(REG08 (MAC1(MEM(ADDR01 .keep (m1(bit0 (m1(bit1 (m1(bit2 (m1(bit3 (m1(bit4 (m1(bit5 (iobuf(pin34 (m1(bit6 (m1(bit7

6.17: Warning Message Limit

The MAXWRN command specifies the limit for the number of warning messages displayed in the Output window for SILOS. The format for the MAXWRN command is: MAXWRN = value

MAXWRN value

Specifies the limit for the number of warning messages displayed in the Output window for SILOS. Represents limit for the number of warning messages displayed in the Output window for SILOS (Default: 50)

Examples
The MAXWRN command should be specified in one of your input files by preceding the command with an exclamation mark (!), and placing it outside of any module boundary, for example: !maxwrn = 80 module testbench; endmodule

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6.18: Exclude Saving Module Instance Variable Values

The MEXCLUDE command excludes the internal variable values from being saved during logic simulation for module instances and any variable that is hierarchically below the excluded module instance. The format for the MEXCLUDE command is: MEXCLUDE mname mname ... mname

MEXCLUDE

mname

Specifies module instances that will not have their internal variables and any variable that is hierarchically below the excluded module instance saved during logic simulation. Represents the name of a module instance.

Application Notes
1. The MEXCLUDE command can be used to specify module instances whose internal variables will not be saved during logic simulation. 2. The effects to the MKEEP and MEXCLUDE commands are cumulative. 3. The KEEP, EXCLUDE, MKEEP and MEXCLUDE commands can be used with the CONTROL .SAVSIM=1 option.

Examples
CONTROL .SAVSIM=1 MKEEP (mac1(a MEXCLUDE (mac1(a(c !mexclude (m1(bit0 (m1(bit1 (m1(bit2 (m1(bit3

(m1(bit4 (m1(bit5 (m1(bit6 (m1(bit7 (driver (iobuf(pin34

6.19: Keeping Module Instance Simulation Variable Values

The MKEEP command saves the logic simulation state values for all variables in the specified module instances, and the state values for all variables hierarchically below each specified module instance. The format for the MKEEP command is: MKEEP mname mname ... mname

MKEEP

mname

Specifies module instances whose logic simulation state values will be saved for all variables in the specified module instance, and for all variables hierarchically below each specified module instance. Represents the name of a module instance.

Application Notes
1. The MKEEP command can be used to specify module instances for which the simulation state values to all variables are saved. 2. The effects to the MKEEP and MEXCLUDE commands are cumulative. 3. The KEEP, EXCLUDE, MKEEP and MEXCLUDE commands can be used with the CONTROL .SAVSIM=1 option.

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Examples
CONTROL .SAVSIM=1 MKEEP (mac1(a(b .mkeep (m1(bit0 (m1(bit1 (m1(bit2 (m1(bit3 (m1(bit4 (m1(bit5 (m1(bit6 (m1(bit7 (driver (iobuf(pin34

6.20: No Convergence Summary

The t/s NOCONV command generates a report of any no converged nodes and their oscillating states for the time point that no convergence occurred. To obtain a no convergence summary for nodes and devices, enter: TYPE STORE WTYPE NSTORE NOCONV [ / INPUT ITER=val ]

TYPE STORE ... NOCONV INPUT ITER=val

(Optional) Directs the no convergence table to standard output or to a disk.

Reports the oscillating states for no converged nodes. (Optional) Reports the states for all inputs of devices which drive the oscillating nodes. (Optional) Specifies the iteration number to the first of eight states for each node reported for no convergence. The default iteration for val is computed such that the last of the eight states reported corresponds to the last iteration simulated before no convergence halted the simulation.

Application Notes
1. The t/s NOCONV command can be used to identify which parts of the circuit have caused a logic initialization or logic simulation to no converge. 2. The t/s NOCONV command reports the following information: Names of the unresolved devices and nodes. The type of device and node as either a .type data keyword, NODE for a wired connection with at least one bi-directional device, or BUS for a wired connection between two or more unidirectional enabled gates. The node state values for the no convergence time point. State values reported are preceded by a ... to indicate possible previous states.

The first character is the strength and the second character is the level. First Character: S = supply strength D = driving strength R = resistive strength W = weak strength Z = high-z strength 0 = low

Second Character:

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* = unknown 1 = high UN: unset, the state of this node has not been evaluated yet. OF: OFF, this node is connected to a tri-state or transfer device that is off (high-z).

There are two special states:

3. No convergence only occurs when gate delays are zero. Zero-delays occur during logic initialization, which forces delays to be zero; during zero-delay logic simulation; or when either zero delay or no delay is specified for devices (the default delay for Verilog HDL devices is zero). 4. When the iteration limit is exceeded while resolving node states at a time point, a no convergence error stops execution. No convergence may be due either to the circuit path length or problems with designs involving feedback. The circuit design must be corrected to eliminate oscillations caused by problems involving feedback. When no convergence is due to path length, increasing the iteration limit should enable the circuit to converge. In general, each node in the serial path length requires one iteration to propagate a signal. 5. The maximum iterations per pass for logic initialization can be redefined by the CONTROL .MXDCI command. The maximum iterations at a time point for logic simulation can be redefined by the CONTROL .MXITR command. Arbitrarily increasing these parameters is not recommended as it may dramatically increase the execution time necessary to identify oscillating nodes. 6. The maximum number of passes for logic initialization is defined by the CONTROL .MXPAS command. When this limit is exceeded, the error message specifies the required number of passes to complete logic initialization. To reduce the number of passes and execution time, use .INIT to preset the state for critical nodes. Although arbitrarily setting CONTROL .MXPAS to a large value will very likely converge a circuit that is theoretically solvable, this is not recommended as the problem is usually due to incorrect circuit design.

Examples
ty noc nocon /iter=43

6.21: Narrow Storing Outputs

When a command that generates a report is preceded by the NSTORE command, the report output will be directed to a disk file. To specify the NSTORE command, enter: NSTORE command ...

NSTORE command

Directs the output to a 79 column disk file. As a default, this file is named store.out. Represents a command structure which defines the type of data to be output. These commands are described within this section of the manual.

Application Notes
1. If a command that generates a report is not preceded by the NSTORE command, then the default output device is specified by the CONTROL command. 2. To respect the page width for the NSTORE command, use the FORMAT .NSTORE command. 3. The default file name for the NSTORE command may be redefined using the DISK command or the FILE.STO= command.

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Examples
nstore output on change NSTO NETWORK /FDD

6.22: Preprocessing Data

Normally, data preprocessing is automatically performed prior to initialization or simulation (i.e., when the SIMULATE command are entered). However, you may wish to use the PREPROC command to check for syntax errors without simulating. To preprocess data, enter: PREPROC

Application Notes
1. During data preprocessing, the program resolves and checks all gate input connections, calculates fan-out connections and creates implicit nodes. Generally, the data is reformatted for more efficient simulation. 2. Once preprocessing has been performed, additional topological data cannot be entered. 3. Note that at least the first three letters of this command must be specified (i.e. PRE). 4. If serious errors occur during a phase of the preprocessing, you should correct the errors before proceeding. If the errors were corrected interactively, enter RESET ERRORS and then reissue the PREPROC command to continue preprocessing.

6.23: Probing Node States

The probe command reports the value of variables and expressions in tabular format. The format for the probe command is: STORE STORE STORE probe probe probe ITER STEP dt t1 t2 t1 t2 t1 t2 "format" "format" "format" (expression), expression (expression), expression (expression), expression ... ... ...

STORE probe STEP dt ITER

(Optional) Directs the probe output to a disk file. Use the DISK command to specify the file name for the stored output. Reports the value of variables and expressions in tabular format. (Default: report the on change values) (Optional) Causes the values to be reported between time t1 to time t2 at intervals of dt. (Optional) Causes values of variables and expressions to be reported for each iteration at a time point.

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t1 t2

format expression

(Optional) Represents an optional time point range over which the values will be reported. When t1 and t2 are not specified the probe command will use the simulation time values or the time values specified on the last probe command. (Optional) Specifies the format for reporting the expressions. Any of the format specifications for $display and $monitor are allowed (Default radix: %h) Specifies any legal Verilog HDL expression. The parentheses around the first specified expression are not required when it is just a single variable. Full hierarchical path names can be used, otherwise the module instance selected by the SCOPE command will be used. A ,, can be used instead of a name to insert a blank column in the report. When an @ sign is used in front of any expression, then values are reported when those expressions change.

Examples
A typical way the probe command can be used is to declare the scope for a module instance, and then list variables in the module that you want to report on. Using two commas between variables would leave a blank column between variables: scope main pro a,,b,,c // declare module instance "main". // blank column between variables.

The probe command can be used to report the value for any expression, such as, you could use the following probe command to report the value for the assignment out= (a+b) | (c+d) for each change of variable clock: probe @clock,, "out=", (a+b) | (c+d)

The STORE command can be used to store the probe report to a file: store probe a,b // stores the probe report to a file.

Some additional examples for the probe command are listed below: probe main.i1.a // report variable "a" inside instance "main.i1" // use string and octal radix formats. // report concatenated variables as octal // vary the radix for reporting values.

probe "output result = %o", out probe 0 100 %o{a,b,c} store probe %b a[0:2], %h a[3:6]

6.24: Quitting Execution

The QUIT command enables you to terminate an unwanted session without that session affecting any active SAVE files. To quit program execution, enter: QUIT

Application Notes
1. The QUIT command aborts execution of the program and all program results since the last SAVE command are lost. Note: This command is not available GUI mode.

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6.25: Resetting Selected Data

The RESET command can be used to reset (i.e. delete) selected data information for the command line version of SILOS. For the graphical interface version, SILOS, use the Load/Reload Files button. The form of the command is: ALL ERRORS RESET

OUTPUTS PATTERN SAVFILE

RESET ALL ERRORS

SAVFILE

Resets selected program counters and/or flags as specified by the below options. Resets everything (as if you just began execution). The program will not issue a warning. Deletes data error flags and messages up through level 4. This can be used to continue a simulation after errors have been corrected, and to clear unnecessary warning and error messages. Resets the logic simulation save file data to eliminate disk storage.

Application Notes
1. For RESET OUTPUTS, new output commands can be entered from the menu selections or input from a file. 2. Before using RESET SAVFILE, reports should be generated and/or the SAVE files should be copied to tape. After RESET SAVFILE, logic simulation can be continued from the last simulation time point but output reports are not available for simulation results prior to the last simulation time point.

Examples
RES res ERR savfile

6.26: Scope For Printing Module Variables

The SCOPE command declares the module instance used when the PRINT or probe commands reports the values for variables and expressions in a module. The format for the SCOPE command is: SCOPE instance_name

SCOPE instance_name

Declares the module instance used by the PRINT or probe command. Represents the instance name for the module whose variables will be reported by the PRINT or probe commands.

Example
SCOPE main.cpu.cache

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6.27: Logic Simulation Specification

Logic simulation can be performed by entering the SIMULATE command. To initiate the logic simulation, enter: SIMULATE t1 [ TO t2 ]

SIMULATE

t1 TO t2

Performs time-response logic simulation that can use both finite and zero delay specifications. Preprocessing (PREPROC) and logic initialization will be automatically performed if they have not been previously. Represent the values of the first and last simulation time points. The keyword TO is optional.

Application Notes
1. When specifying the simulation time point range, the following items apply: Specifying neither t1 nor t2 or setting t2 to an arbitrary large number will cause SILOS to simulate until $stop or $finish is encountered in the netlist. You can stop the simulation by clicking-on the STOP button or holding down the Escape key (Esc) on the keyboard for Windows and Ctrl C on Linux. Specifying a single time point indicates that simulation will be incrementally continued for that amount of time. At time=0, this will start the simulation from time=0 for the specified amount of time. Specifying t1 and t2, with t1=0, runs the simulation from time=0 to time=t2. Specifying t1 and t2, with t1 greater than zero, continues the simulation from the last specified time point. Specifying TO t2 will continue the simulation until time=t2. This can be useful to continue a simulation that was halted due to a breakpoint.

2. The SIMULATE command will automatically invoke the PREPROC command (if PREPROC has not already been performed) and no further topological data can be entered. 3. Simulation can either be continued from the last time point or restarted from time=0. 4. The SIMULATE command uses inertial delays, which do not propagate level changes that occur faster than the gate output can change (spike condition).

Examples
simul 0 to 22k SIM 5KGG 10K SIM 5K sim 0 15k SI TO 5K

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6.28: Size-Of-Data Reprint

The SIZES command reports the memory usage for SILOS. To report the network size information, enter: TYPE STORE WTYPE NSTORE SIZES

TYPE STORE ... SIZES

(Optional) Directs the size information to standard output or to a disk file.

Generates memory usage information.

Application Notes
1. Items reported include the total number of devices, network names, etc. 2. The memory usage may be different after read-in, preprocessing and simulation.

Examples
NSTO SIZ TY SIZ

6.29: Spike Summary Output

The t/s SPIKES command allows you to view all the nodes on which spikes were made observable during logic simulation (see Section 6.27:Logic Simulation Specification). To generate a node spike summary, enter: TYPE STORE WTYPE NSTORE TYPE STORE ... SPIKES t1 TO t2 SPIKES [t1 TO t2]

(Optional) Directs the spike summary to standard output or to a disk file.

Lists a summary table of all spikes between two time points. Represent the minimum and maximum time point values over which the spike output is to be generated. This time point range must be within the logic simulation time point range. If the time points are not specified, the logic simulation times are used. (The TO keyword is optional.)

Application Notes
1. A spike occurs when the gate input level changes faster than the gate output can change. 2. Setting the criteria for spike conditions is controlled by the +pulse_e, +pulse_r, and +pathpulse command line arguments. For additional information, see Appendix B: Command Line Arguments. 3. To enable spike recording during logic simulation for the SPIKE report, use the +silos_spike command line option. For additional information, see Appendix B: Command Line Arguments.

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Examples
ty spikes NSTO SPIKES 4.2K 4.8K

6.30: Storing Outputs

When a command that generates a report is preceded by the STORE command, the report output will be directed to a disk file. To specify the STORE command, enter: STORE command ...

STORE command

Directs the output to a 132 column disk file. As a default, this file is named store.out. Represents a command structure which defines the type of data to be output. These commands are described within this section of the manual.

Application Notes
1. If a command that generates a report is not preceded by the STORE command, then the default output device is specified by the CONTROL command. 2. To respect the page width for the STORE command, use the FORMAT .STORE command. 3. The default file name for the STORE command may be redefined using the DISK command or the FILE .STO command.

Examples
store output on change STO NETWORK /FDD

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6.31: Strength Specification For Gates

The STRENGTH command allows you to modify the default strength types. To re-specify default strength types for gate devices, use: STRENGTH .device/strg .device/strg ...DEFAULT/strg

STRENGTH .device DEFAULT strg

Indicates that default strength-types are to be assigned to unidirectional gate devices. Represents a device keyword. If no device/N, device/P or device/strg keyword is specified for an individual gate device, the program defaults to a CMOS strength type. Sets the strength for all devices that do not have the strength explicitly specified. The default is CMOS strength type. Represents any combination of D, R or Z. The first character indicates the strength of the Low level. The second character indicates the strength of the Unknown level. The third character indicates the strength of the High level. D represents Strong strength, R represents Pull strength, and Z represents High-Z strength. Alternatively, the characters N, P or C can be used by themselves to indicate NMOStype (DRR), PMOS-type (RRD) or CMOS-type (DRD) defaults.

Application Notes
1. The device keyword can be any of the combined gate devices. 2. Supply-strength cannot be defined.

Examples
!strength !strength .nor/n .nand/n default/ddd .not/c

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6.32: Symbol Modification For Output

The SYMBOL command allows you to use a unique symbol for each possible logic state. To modify the output state symbols, use: SYMBOL sc=char sc=char sc=char ...

SYMBOL sc

Specifies that the state code symbols are to be redefined. Represents one of the state-type codes for the OUTPUT, POUTPUT and probe reports and for the .CLK and .PATTERN stimulus specifications:

State Symbols S0 S* S1 SHV

State Supply Low Supply Unknown Supply High Supply High-Voltage

Default Report Symbol 0 * 1 1

Default Stimulus Char 0 * 1

D0 D* D1 DHV

Driving Low Unknown High High-Voltage

0 * 1 1

R0 R* R1 RHV

Low Unknown High High-Voltage

0 * 1 1

Z0 Z* Z1 ZHV

Low Unknown High High-Voltage

Z Z Z Z Z

(sc)

The following symbols are used only in the output reports. No symbol can be defined to input these states for .CLK or .PATTERN stimulus:

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State Symbols *0 ** *1 *HV

State Uncertain Low Uncertain Unknown Uncertain High Uncertain High-Voltage

Default Report Symbol * * * *

Default Stimulus Char 0

0D *D 1D HVD

Decaying Low Decaying Unknown Decaying High Decaying High-Voltage

D D D D

*S

Spike

char

Represents the single character you want to be used to indicate the state. The comment character (default a $) cannot be used as a char symbol.

Application Notes
1. Enter the SYMBOL command before the .PATTERN and .CLK specifications are entered to redefine symbols used for stimulus state values. 2. The SYMBOL command can redefine node state symbols either before or after simulation for the t/s OUTPUT, probe, and t/s POUTPUT reports. 3. When the same symbol is used to represent the different states (as in the defaults of 0,*,1) for the input stimulus for a .CLK or .PATTERN specification, the program resolves the ambiguity in the following order: The most recent symbol specified by the most recently entered SYMBOL command is used. For the default symbols not specified by a SYMBOL command, the higher strength is used and within a strength, the higher level is used.

For example, if SYMBOL D1=+ R0=+ is entered, then the symbol + would mean Resistive Low. If SYMBOL D1=+ D*=+ is entered, then the symbol + would mean Driving Unknown. 4. Note that the Unset state symbol cannot be changed; it will always be a question mark (?).

Examples
SYMBOL Z0=- Z*=# Z1=+ .symbol r*=U z*=U d*=U r0=L z0=L SYM 0D=L r1=H z1=H d1=H d0=L S1=I !SYM D0=O D*=X D1=I *S=^

*D=U

1D=H

S0=O

S*=X

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Chapter 7: Linting Capabilities

7.1: What Silos Lint Does
SILOS LINT is a system for statically analyzing an electronic circuit design written in hardware

description language (HDL) code, either written by hand or generated by some other software tool .
SILOS LINT reads in Verilog (IEEE-1364) source code, performs an accurate analysis, and produces a report detailing what you can expect of your design.

There are different ways to use the information produced by SILOS LINT. You can check the integrity of your synthesizer by comparing its results with SILOS LINT'S. You can avoid incorrect simulator results by allowing SILOS LINT to identify and locate potential problems (see Figure 7-1).

HDL Design

Pre-Simulation Screening (Silos Lint)

Simulation

Clean Results

Figure 7-1: Simulation Verification Using Silos Lint

You can speed up the verification cycle by allowing SILOS LINT to find design problems (as well as potential design problems) early. You can enforce coding styles based on policies your company sets by allowing the software flag violations of your policies (see Figure 7-2).

Finite State Machines

Syntax

Semantics Race Conditions Silos Lint Design Policy Synthesis Verification Simulation Pre-Screen

Figure 7-2: Capabilities of Silos Lint

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7.2: Why You Need Silos Lint

Verification is a major bottleneck in integrated circuit design. Design engineers need useful software to verify their designs effectively and efficiently, and given the increase in circuit densities, verification requirements have increased to the point where it's a very complex task. Engineers need adequate software to manage the complexity, and reduce the verification cycle. Different methods are used to verify (e.g., simulation, equivalence checking). As a general rule, the sooner verification is done in the design cycle, the less total time verification will take throughout the entire cycle. Thats where SILOS LINT comes into operation.
SILOS LINT provides you with the means to start verification as early as possible. You can use SILOS LINT

as soon as you write any HDL code, and continue to use it throughout your design process. Because SILOS LINT is so fast, there's very little time lost, but a tremendous amount of confidence gained from putting your design through the thorough processing of SILOS LINTS analysis engines. Simulators and equivalency checkers cannot enter this domain because they are not designed perform the early stage verification that SILOS LINT can. With SILOS LINTs analysis, you will find many early design problems (as well as potential design problems) that normally would be found much further downstream without SILOS LINT. This enables you to proceed through the design process with higher confidence that your final design will verify correctly. The following sections provide more details on some (although, not all) reasons why you would want to use SILOS LINT.

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Linting Capabilities

7.2.1: Race Conditions

The way Verilog was specified, race conditions can occur in your design, meaning different simulators running your design can produce different values at specific points (see Figure 7-3).

Figure 7-3: Verilog Race Conditions

Moreover, your own simulator can become nondeterministic in that part of your design (i.e., you will get different results running the same vectors through the same design at different times).
SILOS LINT identifies parts of your Verilog design for race conditions. Once flagged, they can usually be

eliminated quickly.

7.2.2: Hardware Analysis

The software informs you where registers, latches, state-machines and other sequential elements are inferred, so you can check that you do not get extra synchronous hardware synthesized where you don't want it. It will tell you how many flip-flops you have in your design, whether or not they are enabled, and if they are missing asynchronous resets.

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7.2.3: State Machines

Part of your design may be a finite state machine (FSM). SILOS LINT can extract your FSM from your design, and tell you whether or not you have any redundant or unreachable states (see Figure 7-4).

Figure 7-4: Example of a Finite State Machine

7.2.4: Design Policies

The Software enforces restrictions on identifiers, and other style items to be sure your code conforms to various reuse standards. There are built-in rules to be sure your code conforms to the Design Reuse Methodology Manual. With SILOS LINT'S unparalleled functionality and flexibility, you can enforce just about any style policy you create (see Figure 7-5).

Figure 7-5: Benefits of Policy Checks

7.2.5: Syntax and Semantics

SILOS LINT performs full syntactic and semantic checking of Verilog, and is much more efficient than

simulators, so it will process your design more quickly.

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Linting Capabilities

7.2.6: Design for Testability

SILOS LINT will assist you in keeping your design testable during the RTL design phase. It will catch any issues that will create problems further downstream when testing your design in a packaged device. Testing problems not caught at this early stage will make your design difficult or impossible to fully test. SILOS LINT will catch these design-for-testability problems and save you time and costly development iterations, thereby improving your productivity.

7.3: How to run Lint in Silos

In SILOS, there are three ways to run Lint:

Run Lint From Object File

Once SILOS is started follow the three following steps to run LINT: 1. Load the project to be worked on, 2. Load the lint option file if needed, 3. Click Run Lint on Project Files from the File menu.

Run Lint From One or More HDL Source Files

Once SILOS is started: 1. Click Run Lint On File/s from the File menu, 2. Choose HDL source files from the pop-up window, 3. LINT will run automatically after the files are chosen.

Run Lint in Batch Mode

Without starting SILOS GUI, LINT can also be run in batch mode: silos.exe -b -lint [option] [source]

Example
silos.exe -b -lint -f option_file test.v A Lint report will also be saved as lint.lst for your convenience. In GUI mode, to load the lint option file, choose Project Properties from the Edit menu, and then Lint Option File from the list of left hand items. The file can be added from the dialog. In GUI mode, Lint messages will be shown in the output window with a hypertext link. Clicking a link will lead to the source code that triggered the message.

Lint Option File Example

lint_op.f --no_lib_warns //turn off following messages --msg_off=0xc300 // on length of a line; --msg_off=0x7a00 // hard-coded numeric constant in the design; --msg_off=0x7c00 // should have header

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7.4: Lint Options

-b
Suppress the printing of messages, such as found compiler directive ....

-f <file>
Process additional options and source files from the file named <file>.

-m <num>
Print out at most <num> errors, warnings or notes (default is 1000 for each); a message will be printed if this limit is exceeded for any severity level

-n
Dont print out note (low priority) messages.

-q
Suppress printing of any output to the screen (however, all output will still be printed to lint.lst).

-v <file>
Scan for designs in the library file <file>.

-w
Dont print out warning (med priority) messages.

-y <dir>
Scan for additional source files in the library directory <dir>.

+incdir+<dir1>+ +incdir+<dir1>+<dir2>+<dir3>+
Search directories (<dir1>, <dir2>, <dir3> etc.) for files included with the `include compiler directive.

+<opt>+<val>+
Other plus options normally specified for simulators.

--add_carry
Check for a carry bit in each add operation, and print a warning if the carry is ignored.

--blackbox=<val>
Specify a blackbox for <val>; assume that a (Verilog) module named <val> exists to prevent the missing module ... error message from appearing.

--char_pos
print out character positions for messages, if applicable (e.g., line 21.4 means line 21, character 4). Not all messages will print character positions.

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--clk_domain_sync=<val>
Require that signals passing from 1 clock domain to another be buffered (sampled) through at least <val> flip-flops clocked within the new domain. Default is 0 (no requirement)

--clk_edge=<val>
Require that clocks are active on the edge specified by <val> (either posedge or negedge). If this option isnt specified, either edge can be used in the design

--clk_prefix=<val>
On flip-flops and latches, check that clock signal names have <val> as a prefix; quotes are not needed (see also description of the --rst_prefix option).

--comment_coverage=<num>
Sets the minimum comment coverage for source files, measured by characters. If the percentage of comments goes below this value for any file, a warning is printed (e.g., --comment_coverage=25 means at least 25 percent of the code must be comments).

--condense_msgs
Print out messages in condensed format; identical messages for different lines or files are printed out together.

Note: Cannot be used with --one_line_per, which has higher priority.

--emacs
Print out messages in a format that emacs can parse.

--error=<val>
Reclassify message <val> so that its printed out as an ERROR (highest priority) message; <val> is a hexadecimal code that is printed for every message in the log file (e.g., 0x5080).

--filter_errs
Allow filtering of ERROR (highest priority) messages from the the message_off source code directive, or msg_off command line option. This is generally discouraged, but may be useful under certain circumstances.

--fpga
Turn on checks that are specific to FPGA design. Default is off.

--help
Print out the help summary. It is also optional that no options specified will print this summary as well.

--just_top_level
Print out messages for top-level modules only.

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--just_warnings
Print out only errors, warnings and notes. Specifically, it prevents printing of the SILOS LINT header, version number, copyright notice and so forth; however, it doesnt suppress printing of the error count summaries after the design files are read.

--line_length=<num>
Sets the line length for msg 0xc300. This message is printed for lines longer than this value. Default is 72.

--little_endian
Enforce little-endian (e.g., [0:3]) order for ranges. Default is big-endian (e.g., [3:0]).

--max_if_depth=<num>
check for if statements nested deeper than <num> levels. Default is 0 (i.e., doesn't check for deeply nested if statements ).

--max_logic_levels=<val>
Check that logic between primary inputs/outputs/inouts and flip-flops, and between successive flipflops, is no greater than <val> levels. Default is 0 - no check done.

--msg_file=<file>
Print messages (errors, warnings and notes) to the file specified (<file>). No header information will be included in this file, and no options will be echoed either. The lint.lst file will still be generated, and will have a copy of the same messages.

--msg_off=<num>
Globally suppress printing of message <num>, where <num> is a message number obtained from the messages printed in the log file lint.lst.

--msg_on=<num>
Globally enable printing of message <num>, where <num> is a message number obtained from the messages printed in the log file lint.lst. This option is useful if you specify --msgs=off as well.

--msgs=on/--msgs=off
By default, this option is on, which means that messages will be printed, unless filtered out by the -msg_off command line option, or the message_off source code directive inside of your Verilog design file. If this option is set to off, messages will not be printed unless enabled by the --msg_on command line option, or the message_on source code directive inside of your HDL file.

--no_comment_checks
Turn off rule checking for comments.

--no_lib_warns
Suppress printing of all messages generated from code in library files (from the -v option) and library directories (from the -y option).

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Linting Capabilities

--no_lst
Prevent the file lint.lst from being created.

--note=<val>
Reclassify message <val> so that it is printed out as a NOTE (lowest priority) message; <val> is a hexadecimal code that is printed for every message in the log file (e.g., 0x5080).

--one_line_per
Print out just 1 line per message (error, warning or note) including the file name and line number.

Note: This option will override --condense_msgs.

--project=<val>
Set the initial project to <val>.

--reg_suffix=<val>
Check that the output signal names of flip-flops and latches have <val> as a suffix. If this is set to nothing (i.e., --reg_suffix=), the check isnt performed. Quotes are un-necessary and should not be used.

--rmm=off/--rmm=on
Turn off or on checks to ensure compliance to the coding rules of the Reuse Methodology Manual. Default is on.

--rst_prefix=<val>
On flip-flops and latches, check that asynchronous reset signal names have <val> as a prefix. Quotes are not needed (see the description of the --clk_prefix option).

--sort
Sort design files so that messages appear in a fixed order, regardless of what order the files are specified in on the command line or in a control file (-f option).

--sort_by_priority
Sort messages by priority (Errors, Warnings, Notes).

--tag_report
Give a summary report on message tags. Message tags are used to limit the printing of messages.

--v_design=<val>
Use when --no_lib_warns is used as well. Look for design (as opposed to library) data in the file <val>; design data found in <val> will still be checked even though library data (from -v) will not (assuming --no_lib_warns).

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--warning=<val>
Reclassify message <val> so that it is printed out as a WARNING (medium priority) message; <val> is a hexadecimal code that is printed for every message in the log file (e.g., 0x5080).

--yd=<val>
Use when --no_lib_warns is used as well. Look for design (as opposed to library) files in the directory <val>. Design files found in <val> will still be checked even though library files (from -y) will not (assuming --no_lib_warns).

7.4.1: Lint Option Example

lint_op.f --no_lib_warns //turn off following meggages --msg_off=0xc300 // warn on length of a line; --msg_off=0x7a00 // hard-coded numeric constant in the design; --msg_off=0x7c00 // should have header

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Appendix A: Frequently Asked Questions (FAQ)

Q: I renamed my group/bus but it reverted to the previous name. How do I prevent this? A: Unless you hit Enter after typing in the new name, the tool will ignore the change.

Q: If my compiler directives on the same line why doesn't my code to compile? A: Compiler directives need to be on separate lines.

Q: Why can't I rename a signal in the Data Analyzer by double clicking on it? A: Select the signal and press F2 to rename the signal.

Q: The following pop-up appeared, what does it mean?

A: If simulation data is not being saved, then for performance reasons the GUI is polled less often. This means the GUI will appear less responsive until the simulation is complete. It does not effect the simulation results.

Q: How can I create a Save and restore file (.cmm) from my Verilog code? A: Use the Verilog extension system task $save( ). For more information regarding the use of this extension system task, see Section E.5:$save( ) Extension to Create a .cmm File.

Q: How do I select the delay case for timing simulations? A: Use the EditProject PropertiesOther Settings menu option and use the Delay Selection drop down menu to select Min, Typ or Max delays.

Q: How do I execute the commands from Chapter 6: Interactive Commands without using the GUI? A: You need to place them at the end of the first module listed in the project (usually the top level), preceeded by an exclamation mark (!). ... ... endmodule !mKeep (foo Q: Can I use the same .cmm file on different operating system platforms? A: No. The .cmm file will only work on similar platforms (i.e., a .cmm file on Windows will not work on Linux).

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Q: What are the flashing red dots that appear in the Analyzer window? A: These are State Change Hazards. They occur when a signal has more than one state change per simulation event. They are often a source of design problems. These events are flagged using flashing red dots. They can be hidden by unchecking the Display State Change Hazard checkbox in the EditPreferencesAnalyzerOptions dialog.

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Appendix B: Command Line Arguments

The syntax for the the program command line is: silos [command_line_arguments] [<path/>input_filename] Examples of command line arguments are: -y ./lib/vfl +libext+.v +incdir+../shared-hw/svy_backplane/rtl -f svybus.vc Supported command line arguments are: -"!system" -b Execute a system command: -"!system \"ls -lt\"" Run in interactive mode without starting the GUI. In this mode the commands described in Chapter 6, Interactive Commands, can be used. This option compiles the source files and then exits. Convert a .spj formatted project file to XML format and exit: silos -converttoxml myproj.spj This option instructs the program to get the command line arguments from a file. The program has the ability to nest the command files. For example, command file logicsim, could contain the name of another command file logicsim1 that has additional - command line arguments. The program style commands can be used in a command file by enclosing the command with double quotes -!silos_command, i.e. -!control .sav=2. This option saves the text that has been entered from standard input to a file. Write the standard output from the program to a log file. This option appends the standard output from the program to a log file instead of over writing the log file, and also to standard output. This option must appear before the -l <fn> option.

-c -converttoxml

-f file_name

-k file_name -l file_name -la

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-nospec

The -nospec command line option eliminates all specify blocks. Eliminating the specify blocks will reduce the memory used and increase the simulation speed. However, eliminating the specify block delays may cause race conditions and non-convergence due to zero delays. If this happens, the rise and fall delays for all gates (whose delays are not explicitly specified) can be set to 1 with the following the program command: -"!delay .default =1,1" This option restores the program to the last saved simulation state from a previous the program save command. This option causes the program to enter the interactive mode after executing any commands that have been input to the program. This option converts every name to upper case. This option specifies a library file name. Specifying -w means that the program will not display any warning messages. This option specifies a directory of library files. This option modifies the return value of the program from '0' (good) and '1' (error/s) to '+1' (no major errors) and '-1' (major error occurred). This option allows you to specify `define macros from the command line. The text_macro_name is the macro identifier, and the macro_text is the text substitution. Double quotes ( ) must be used around the macro_text if the macro_text contains white space. For example: +define+sdf=test.sdf is equivalent to: `define sdf test.sdf and: +define+declare="reg a;" is equivalent to: `define declare reg a;

-r save_file_name

-s

-u -v file_name -w -y directory_path +alt_return_value

+define+text_macro_name=macro_text

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Command Line Arguments

+delay_mode_distributed

This command line argument specifies the distributed delay mode for all modules in the source description. This means that the distributed delays for gates connecting the module input to the module output will always be used as the pin-to-pin delay for the module input to output. This command line argument specifies the path delay mode for all modules in the source description. This means that the path delays specified in the specify blocks for delays from the module input to the module output will always be used as the pin-to-pin delay for the module input to output. This command line argument sets all gate and specify block delays to one. This command line argument sets all gate and specify block delays to zero. This command line option works with the $vcdin() system +task. The GHDL simulator may include 'U' value characters in the 4 state VCD files it can generate, this is not a legal 4 state value character as specified in the IEEE 1364 LRM. The +ghdl_format option will translate the illegal 'U' value characters to 'X' value characters. If the program can not find a file name that is specified on your `include in the current directory, then it will search the directories specified by the +incdir command line option for the file. Specifies that SDF INTERCONNECT delays will not be used. This can be useful for reducing the runtime and memory usage for fault simulation. Specifies that SDF PORT delays will not be used. This can be useful for reducing the runtime and memory usage for fault simulation. This option enables code coverage for libraries. This option enables code coverage for line reporting. This option selects the maximum delay specification for delays (min:typ:max).

+delay_mode_path

+delay_mode_unit +delay_mode_zero +ghdl_format

+incdir+directory1+directory2

+ignore_sdf_interconnect_delay

+ignore_sdf_port_delay

+libcodecoverage +linecov +maxdelays

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+memsave

By default does not save data for large memories and prints out a warning to output. Use +memsave[+<module_name>.<memory_variable _name>] to save memory data (e.g., +memsave + foo.mem). This option selects the minimum delay specification for delays (min:typ:max). This option causes the delayed reference and delayed data of $setuphold and $recrem to be delayed according to the limit data from the timing check and from SDF. When +neg_tchk is not used, the reference or data signal are copied to the delayed reference or delayed data without delay. This option issues an error message when a variable is used without first specifying the type of variable that it is. Since wire is the default type for variables, this assists you with finding variables that were automatically set to wire where a register was intended. This option suppresses all messages from $display, $write, etc. system tasks to standard output. This can be used to prevent these messages from cluttering the log file during logic simulation. Automatically inserts `suppress_faults and `enable_portfaults, and `nosuppress_faults and `disable_portfaults around every module in a library file. The library file can be specified using the -y and -v command line options, the !library command, or the EditProject PropertiesLibrary Files dialog box. The command line option +no_notifier turns off the notifier variable for the timing checkers. This will prevent UDP primitives in your libraries from using the notifier variable to set the output of the UDP to x, such as for a flip flop. The command line option +no_pulse_msg turns off the +pulse messages. This does the same thing as the +pulse_quiet command line option. This option will suppress SDF zero delay annotation warnings.

+mindelays +neg_tchk

+no_default_variables

+nodoldisplay

+nolibfaults

+no_notifier

+no_pulse_msg

+no_sdf_zero_delay_msg

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Command Line Arguments

+notimingchecks

This option deletes the timing checking operation, it does not delete the entire timing check which previously included the delayed reference and delayed data signals. Using this option can improve speed and reduce the memory used. This option suppresses timing check violation messages. Timing checks are still processed, but no messages are printed to standard output if there is a timing check violation. Use alternate virtual memory allocator. This option may allow a greater amount of virtual memory to be allocated by the program. Using this option will disable the Save/ Restore Simulation feature.

+no_tchk_msg

+nosave

+nowarntfmpc

This option suppresses the warning message for a mismatch in the number of port connections. This option enables code coverage for operator reporting. This option may slow simulation speed, you may not want to use it unless you wish to obtain a code coverage report for operators. You can enter + command line arguments that are project specific, such +compare, +sdf, .etc. For example, suppose you wanted to specify the SDF file only when you entered +sdf in the plusargs box for the Project Properties dialog box. Then your test bench may look like: module test_bench; initial if ( $test$plusargs( "sdf")) $sdf_annotate("test.sdf"); // only execute if "+sdf" is an argument endmodule

+oprcov

+plusargs

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+protect

This option encrypts source code that is bounded by the `protect and `endprotect compiler directives. The `protect and `endprotect compiler directives can be placed inside of or outside of a module or a user defined primitive. The `protect and `endprotect compiler directives can not be nested. The source file is not modified when it is encrypted. Instead, +protect creates an encrypted file with a p appended to the source file's name. To specify the extension that +protect adds to the end of the source file's name, use the command line option +protect.ext, where extension .ext will be added to the file. Multiple files can be encrypted using a single +protect command. These command line arguments specify a range of pulse widths that will propagate to the path destination. For +pulse_r/<n>, n specifies a number in the range 0-100. This will reject any pulse whose width is less than n percent of the module path delay. For +pulse_e/<n>, n specifies a number in the range 0-100. This will flag as an error and drive unknown (x) any path pulse whose width is less than n percent of the module path delay, but whose width is greater than pulse_r/<n>. For more information, see PATHPULSE$ in the IEEE 1364 Verilog HDL manual. This command line argument suppresses warning messages generated by pulse_e command line argument. This option will change the format of the simulation data file that the program uses to store event data from the .sim format used by the 'Analyzer' waveform viewer to the rawd format that can be read by SMARTVIEW.

+pulse_r/<n> and +pulse_e/<n>

+pulse_quiet

+rawd

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Command Line Arguments

+save_data_interval+n

Simulation event data is buffered before being written to the data file (.sim or .rawd). If the saved events are infrequent due to a small number of saved nodes or low activity on the saved nodes, the buffer may not be flushed for some time. This option will create a timer with a period of 'n' minutes that will force a running simulation to pause and restart. The pause and restart will cause any buffered simulation data to be written to the simulation data file. If "n" has a value of zero, this option is disabled. This option is active for the GUI version of the program only and is disabled by default. This option will suppress the warning message for redefinition of `define macros. This option will suppress the warning message for floating nodes, which may be caused by a gate input not having a driver, or by declaring a variable as a wire and then never assigning a value to it. This option turns on all timing checks for fault simulation. This will slow down the fault simulation and increase the memory used by fault simulation. This option turns on transport delays for SDF INTERCONNECT delays. This option selects the typical delay specification for delays (min:typ:max). (Default: +typdelays) This option will issue a warning message if the widths for variables in an expression or assignment are inconsistent, i.e: wire [3:0] a4; wire [2:0] a2; assign a4 = a2 & a4; // caught assign a4 = a2; // caught assign a4 = a2 & a2; // caught Specifies a switch so that the order of evaluation for always blocks is the same order as for Verilog-XL. This switch may be useful for obtaining the same simulation results as Verilog-XL. This option must be parsed before any modules are parsed. This option automatically enters `define xl_order 1. An example would be the order of evaluation for: always @posedge clock .. always @posedge clock ..

+suppressredef +suppressfloat

+timing_checks

+transport_int_delays +typdelays

+width_mismatches

+xl_order

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B.1: Command Line Argument Notes

Environment variables are expanded by the program. For example, the environment variable OPTION can be set by: setenv OPTION nowarntfmpc or set OPTION=nowarntfmpc (Windows) (Linux)

If the program is started with a command file that contains the line: +$OPTION nowarntfmpc would be substituted for the string $OPTION in command file and the program would be run with the option: +nowarntfmpc Command line arguments can also be entered in the EditProject PropertiesOther SettingsCommand Line Arguments edit box.

Figure B-1: Other Settings Menu

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Appendix C: Example Projects

The install/examples/silos subdirectory has a number of examples to assist you. Before using these examples it is recommended that you copy them to your personal directory, and if necessary change the file permissions.

Web Examples
001_verilog_hdl 004_vpi 007_command_line_options 011_encryption012_lint 015_command_entry 018_run_pause 022_source_breakpoints 025_analyzer 029_analyzer_bookmarks 032_analyzer_groups 035_analyzer_symbols 039_analyzer_expressions 002_sdf_annotation 005_vcd_out 008_vcd_in 013_project_file 016_source_edit 020_reload_and_go 023_watch_window 026_drag_and_drop 030_analyzer_markers 033_analyzer_vectors 036_analyzer_colors 040_digital_display 003_pli 006_command_line 009_code_coverage 014_output_window 017_module_explorer 021_single_step 024_smartview 027_analyzer_zoom 031_analyzer_scan 034_analyzer_radix 038_analyzer_source_trace 041_analyzer_analog_display

Tutorial Projects
analog analog.spjx: Project file for Analog to Digital converter circuit that models the analog portion at the behavioral level and the digital portion at the gate level. code_coverage code_coverage.spjx: Project file for demonstrating code coverage for the Line report and Operator report for Verilog HDL behavioral code. To run this example, see Section 3.8:Tutorial 5: Code Coverage. code_coverage2.spjx: Project file for merging code coverage results from two different simulations using the same behavioral model and different testbenches. To run this example, see Section 3.8:Tutorial 5: Code Coverage. gate gate.spjx: Project file for circuit that demonstrates traceback at the gate level. Traceback is useful for finding problems after synthesis. To run this example, see Section 3.9:Tutorial 6: Gate Level Debugging Using Trace Inputs. rtl rtl_.spjx: Project file for circuit that demonstrates features for debugging an RTL design. To run this example, see Section 3.3:Tutorial Topics. rtl_err rtl_err.spjx: Project file for circuit that shows how to automatically open the source file for displaying a syntax error. To run this example, see Section 3.10:Tutorial 7: Error Reporting. vcd_input vcd_input.spjx: Project file for circuit that shows how to input a Value Change Dump (VCD) file to be used as stimulus for the design. To run this example, see Section 5.3:Inputting Value Change Dump (VCD) Files for Stimulus.

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Appendix D: File Extensions Used by Silos

The following is a list of file extensions used by SILOS. .cfv .cfv.orig .cmm .codecov .err .log This is the cfv (Command File Verilog) file. It is created each time the tool is run. This file is created by renaming the existing .cfv file when the tool is run. This is the Save and Restore File. See Section 4.13.17:Save Simulation and Section 4.13.18:Restore Simulation. Code coverage data file This file contains a list of warnings and errors. This is the optional .log file that contains the contents of the Output Window. See Section 4.14.13:Project Properties Menu Selection, Other Settings to find out how to set this option. This is the SILOS history file. Original format project file, this format is superceded by the XML project file format. XML format project file, contains project settings.

save.hist .spj .spjx

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Appendix E: Non-Standard Verilog HDL Extensions

E.1: Expected Values and Stimulustable
The IEEE Verilog specification does not describe any syntax for tabular representation of input data, nor expected value information. The stimulustable statement is a SILOS enhancement which provides tabular format for input data. The stimulustable statement also can combine expected value information with the tabular format for input data.

E.1.1: BNF
stimulustable <id> ; table <# delay-expression>? <probe> <,<probe>>* ; <delay-constant>? <data>+ ; <delay-constant>? <data>+ ; ......... endtable endstimulustable probe ::= <data-format>? <variable> <(variable)?@ <strobe>>? if <data-format> is omitted then %h is assumed. data-format::= %h ||= %o ||= %b For replacing an existing stimulus table after prep: stimulustable <id> ; table <# delay-expression>? ; <delay-constant>? <data>+ ; <delay-constant>? <data>+ ; ......... endtable endstimulustable

E.1.2: Stimulustable
stimulustable is a behavioral statement and can be located anywhere any statement can be placed, for example: for (i=1; i<=8; i = i+1) // repeat 8 times the input pattern stimulustable ... endstimulustable There is no limit to the number of stimulustable statements. They are not required to be located in top-level modules. The syntax for the stimulustable keywords must be lower case. Such as, the keyword table must be lower case. Variable names are upper/lower case sensitive. Any number of input or expected value columns may appear in a stimulustable. Each input column is identified by a variable which is driven by the data in the column. Each expected value column is identified by an @ sign. The variable on the left side of an @ sign is verified against the data in the column. The variable on the right side of the @ sign is used as a strobe. Variables used in the table can be a wire, register, memory element, integer or real variable of any width and they can have any valid Verilog name.

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In the example below for stimulustable s1, register variable in1 and memory element in2 are driven by the data in the table. Wire out1 is verified against the data in the table whenever the variable strobe1 is high. To prevent possible race conditions, the rising or the falling edge of the strobe signal strobe1 should not coincide with a change in the expected output for out1 in the stimulustable. !control .ext=stim `timescale 1ns/100ps module test; reg [7:0] in1, in2[1:0]; wire[7:0] out1 = ~in1 | in2[0]; reg strobe1; initial strobe1 = 0; always @out1 begin #0.1 strobe1 = 1; #0.1 strobe1 = 0; end initial begin #5; stimulustable s1; table #1.2 in1, in2[0], out1@strobe1; 00 00 ff; 0e 0a f6; ff ff 00; endtable endstimulustable end endmodule

E.1.3: Radix
Data in the table can be in hexadecimal (%h is the default), octal (%o), or binary (%b) for register datatypes, and integer or floating point for integer and real data types. There must be one or more blank spaces between the radix symbol and the variable name it refers to, such as %h in2. Each row of values in the table is terminated by a semicolon ;. Blank spaces and tabs (not carriage returns) can be used to delineate the values between different variables, however, white space is not allowed between the values for a vector variable. An example for specifying the radix is shown below: table #1.2 %b 0000000000 000011100a 11111111ff in1, in2, out@strobe; ff; f6; 00;

For single bit wires, SILOS state symbols may be used to enter states other than 1, 0, x, z. For further information, see Section 6.32:Symbol Modification For Output.

E.1.4: Delay Time

The delay time for a constant increment of time (delta time) between application of subsequent table lines can be specified as a single expression: table #delta .... ; When the delta delay is specified on the table header, then the first table line is applied immediately upon execution of the stimulustable statement. The delay time can also be specified on each table line. When no # sign is specified on the table header, then the delay values are added to the simulation time as the stimulustable is read. The delay is applied prior to the application of the table line. The time units for the delay value can be specified by

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Non-Standard Verilog HDL Extensions

preceding the module containing the stimulustable statement with a `timescale statement. Below is an example: #10 table 1.2 1.6 2.1 `timescale 1ns / 1ns // time=10 out@strobe ff; // time=11.2 f6; // time=12.8 00; // time=14.9

in1, 00 0e ff

in2 00 0a ff

If two ## signs are specified on the table header, then the delay values are relative to the time the stimulus table is started (very much like delay values in a fork/join statement). For example: #10 table 1.2 1.6 2.1 // out@strobe // // // time=10 time=11.2 time=11.6 time=12.1

## 00 0e ff

in1, 00 0a ff

in2 ff; f6; 00;

To have each delay value represent absolute time, start the stimulustable at time=0. For example: initial stimulustable table ## 1.2 00 1.6 0e 2.1 ff s1; in1, 00 0a ff in2 ff; f6; 00; begin

out@strobe // time=1.2 // time=1.6 // time=2.1

Note that mixing of both delay styles in the same stimulus is not allowed.

E.1.5: Memory Utilization

Data specified in tables is not stored in RAM, so as to reduce memory used when there is a large pattern.

E.1.6: Strobe
Expected value information is conditioned by a strobe. When the strobe is high, the variable must agree with the data in the column as follows: 1 0 x z <==> <==> <==> <==> 1 0 don't care High impedance strength (0,1, or x)

The expected value check is engaged when the stimulustable statement begins execution, and persists through one strobe cycle following the conclusion of the stimulustable statement. During engagement of the expected value check, a high (positive) strobe is required to check that the variable agrees with the expected value data. To prevent possible race conditions, the rising or the falling edge of the strobe signal should not coincide with a change in the expected output signal in the stimulustable. For example, in stimulustable s1 (shown below) variable strobe1 strobes out1 every 0.2 nano seconds. This is faster than the input values change (every 1.2 nano seconds) for variables in1 and in2. When the second entry in the table is executed the calculated value for out1 (f6) does not equal its expected value. The violation is recorded at the next high pulse for variable strobe1 and then is not recorded again until after the next entry in the table occurs.

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!control .ext=stim `timescale 1ns/100ps module test; reg [7:0] in1, in2[1:0]; wire[7:0] out1 = ~in1 | in2[0]; reg strobe1; initial strobe1 = 0; always @out1 begin #0.1 strobe1 = 1; #0.1 strobe1 = 0; end initial begin #5; stimulustable s1; table #1.2 in1, in2[0], out1@strobe1; 00 00 ff; 0e 0a f6; ff ff 00; endtable endstimulustable end endmodule Using the disable statement to disable the block containing the stimulustable statement immediately terminates expected value checking. Each expected value column has one strobe, however multiple columns may each have different strobes.

E.1.7: I/O Pad

The stimulustable can be used to model a bi-directional I/O pad. In the example below for stimulustable s1, variable enable controls the bi-directional I/O pin bi_pad. When enable is high (1), pin bi_pad acts as an output pin, and expected value checking is performed every time strobe1 goes high. The stimulustable also ignores any values in the table for pin bi_pad when enable is high. When enable is low (0), pin bi_pad acts as an input pin and the stimulustable applies the values in the table for pin bi_pad as input stimulus. Expected value checking is ignored for pin bi_pad when enable is low. !control .ext=stim `timescale 1ns/100ps module test; wire chipside, bi_pad, enable, out; buf(chipside, bi_pad); // buf(out, in); bufif1(bi_pad, chipside, enable); // bufif1(out, in, enable); buf(out, chipside); reg strobe1; initial strobe1 = 0; always @bi_pad begin #8 strobe1 = 1; #1 strobe1 = 0; #1; end initial begin #5; stimulustable s1; table #10 chipside, enable, out@strobe1, bi_pad(enable)@strobe1; 1 1 1 1; // output cycle 0 1 0 0; // output cycle 1 0 1 1; // input cycle 0 0 0 0; // input cycle endtable

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Non-Standard Verilog HDL Extensions

endstimulustable end endmodule

E.1.8: Expected Value Error

Expected value errors trigger a global register named ExpectedValueError. This register is simultaneously set with specific information about the expected value violated. The ExpectedValueError variable can be accessed either: From the data file to cause immediate interaction with the simulation, for example: always @ExpectedValueError $stop; From the $monitor system task or the SILOS probe command the variable prints a terse string indicating the stimulus name and column name violated, for example: $monitor($time,,ExpectedValueError); To obtain all violations at a single time-point: probe iter ExpectedValueError To obtain time points for which there is at least one violation: probe ExpectedValueError Note other variables may simultaneously be probed, for example: probe out,,ExpectedValueError When the ExpectedValueError signal is displayed in the Data Analyzer, value for the ExpectedValueError signal is none when there is no violation, and x when there is a violation. The Scan T1 Right and the Scan T1 Left buttons on the Analyzer toolbar can be used to scan to expected value violations. If the ExpectedValueError signal shows a series of contiguous none values, then the rising and falling edge of the strobe signal may be coincident with the changes for the expected value signal in the stimulustable. For example, the rising and falling edge of the strobe signal strobe1 does not coincide with expected output signal out1 in the following example. The below example shows how to use the ExpectedValueError variable with $monitor: !con .ext=stim //title example with $monitor `timescale 1ns/100ps module test; reg [7:0] in1, in2[1:0]; wire[7:0] out1 = ~in1 | in2[0]; reg strobe1; initial strobe1 = 0; always @out1 begin #0.1 strobe1 = 1; #0.1 strobe1 = 0; end initial begin $timeformat(-9,3,"ns",-15); $monitor("%t",$realtime,, ExpectedValueError); #5; stimulustable s1; table #1.2 in1, in2[0],out1@strobe1; 00 00 ff; 0e 0a f6; ff ff 00; endtable endstimulustable

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#10 $finish; end endmodule The output from the $monitor is shown below: 6.300ns :s1 out1 fb != f6: 6.400ns 7.500ns :s1 out1 ff != 00: 7.600ns For the first line: 6.300ns :s1 out1 fb != f6: The 6.300ns is the time the difference occurred, the s1 is the instance name for the stimulustable, the fb is the simulation value for variable out1, and the f6 is the expected value for out1.

E.1.9: Expected Value Error Storage

The expected values are stored in variables that use the root name of the variable whose value is checked with an <expected><number> appended to the name. These variables can be accessed with the probe or print commands, or viewed in the Data Analyzer.

E.1.10: Incremental Update

stimulustable data can be incrementally replaced without having to re-input all the files in the design. This allows quick iteration of different stimulus/expected-value patterns. The incremental stimulustables can be specified at any time after preprocessing (the !prep command). When specifying the incremental stimulustables, each incremental stimulustable must be specified outside of any module, and the variable names can not be put on the table line. The name of the stimulustable is used to determine which stimulustable is updated. The file below, test.v, shows the top level module with a stimulustable that is simulated until the $finish is encountered: File test.v: !con .ext=stim `timescale 1ns/100ps module main; reg [8:0] r9; reg r1; initial begin stimulustable s1; table #10 %b r9, 000000000 000010000 111111111 100000001 endtable endstimulustable #10 $finish; end endmodule !sim `include "test1.v"

r1; 1; 0; x; 0;

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The next file, test1.v shows the new stimulustable values. To simulate the new values, use `include to input file test1.v. Notice that the delta delay value was changed from #10 for the first version of stimulustable s1 to #20 for the second version of stimulustable s1. The command !sim 0 2100m will restart the simulation at time=0 and simulate until the $finish in file test.v: File test1.v: stimulustable s1; table #20; 001100000 011010000 111111111 100010001 endtable endstimulustable !sim 0 2100m 0; x; x; 1;

E.1.11: Changing Behavioral Stimulus to a stimulustable Format

Using a stimulustable statement instead of behavioral stimulus has the following advantage: The stimulustable is input in chunks so it requires less memory.

To change behavioral stimulus to a stimulustable format, you can simulate the behavioral stimulus with SILOS and then store the results from the probe command as a file of tabular ones and zeros. The file can then be edited to remove the title for the probe command report. Each line of tabular values in the file must end with a semicolon ;. To add a semicolon at the end of each line, put a ; at the end of the probe state, i.e.: !store probe in1,,in2,,bi1_,,bi2_,";" For example, for file stimulus.v: `timescale 1ns / 100ps module foo; reg in1, in2; reg bi1_, bi2_; wire bi1 = bi1_; // bi-directional inputs wire bi2 = bi2_; // bi-directional inputs initial begin in1=0; in2=0; bi1_=0; bi2_=0; #10 in1=1; bi1_=1; #10 bi2_=1'bz; #10 $finish; end endmodule The following commands would be used from a file to simulate the stimulus: `include "stimulus.v" !control .savsim=2 !sim !disk stim.v !scope foo !store probe in1,,in2,,bi1_,,bi2_,";" Next, edit file stim.v and remove the report header for the probe report and any messages from the probe report.

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Then, include file stim.v into a stimulustable statement: !control .ext=stim `timescale 1ns / 100ps module foo; reg in1, in2; reg bi1_, bi2_; wire bi1 = bi1_; // bi-directional inputs wire bi2 = bi2_; // bi-directional inputs initial begin `timescale 100ps / 100ps // timescale for stimulustable stimulustable s1; table ## in1, in2, bi1_, bi2_; `include "stim.v" endtable endstimulustable `timescale 1ns / 100ps // respecify the circuit's timescale #10 $finish; end endmodule When converting behavioral stimulus to tabular stimulus, you need to ensure that timescale for the tabular stimulus is correct. The units for the time values from the probe command are equal to the smallest resolution for the simulation. This may require a `timescale compiler directive before the stimulustable statement so that the delay values are scaled correctly. In the above example, the resolution of the `timescale 1ns/100ps compiler directive for the circuit is 100ps, so a `timescale 100ps/100ps compiler directive must be used before the stimulustable statement. Notice that the stimulustable for the above example also uses the ## delay notation, so that the time values are relative to the time that the stimulustable statement is started. Notice also that you may need to be careful when applying the stimulus for inout (bi-directional) pins in the circuit. The inout pins bi1 and bi2 are defined as the left hand side of continuous assignments. For this circuit, the stimulustable values should be applied to the registers bi1_ and bi2_. Otherwise, registers bi1_ and bi2_ will remain at an Unknown level, and will continue to drive wires bi1 and bi2 to an Unknown level due to the continuous assignments.

E.2: Analog Extensions

Silvaco has added extensions to the Verilog Hardware Description Language (HDL) that allow SILOS to model analog circuits at the behavioral level.

E.2.1: Real and Integer Data Types

SILOS supports real and integer data types as defined by the IEEE P1364 Standard Verilog HDL Language Reference Manual. To facilitate analog behavioral modeling, SILOS also supports the

following unique extension to the Verilog language: real (floating point) and integer variables can be passed between module ports.

The advantages of directly passing real and integer variables between modules are: Ease of programming style. No loss of information (as occurs with other Verilog simulators).

Passing numerical values between behavioral modules is particularly useful when modeling analog behavior for circuits, such as analog to digital converters, phase lock loops, charge pumps, etc. For an

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example of an analog to digital converter, see file analog.v in the examples subdirectory of the installation directory.

E.2.2: Utility Transcendental Functions

To simplify the implementation of analog models, SILOS supports a full range of transcendental math functions. The following functions accept a single floating-point argument x, and return a floatingpoint value (except for pow, which has two floating point arguments x and y): Function Name sin(x) cos(x) tan(x) asin(x) acos(x) atan(x) sinh(x) cosh(x) tanh(x) sqrt(x) exp(x) log10(x) log(x) pow(x,y) Description sine cosine tangent inverse sine inverse cosine inverse tangent hyperbolic sine hyperbolic cosine hyperbolic tangent square root exponential common logarithm natural logarithm xy

E.2.3: Examples for Transcendental Math Functions

The transcendental functions are used in the same way as any other Verilog function. The module below illustrates a simple use of displaying values for the math functions: module math03; initial begin real pi; pi = 3.14159; $display ( "sin(0.0) = 0:", sin(0.0)); $display ( "sin(0.5 * pi - 0.01) = 0.99995:", sin(0.5 * pi - 0.01)); $display ( "cos(0.00234) = 0.999997:", cos(0.00234)); end endmodule The next example shows how to generate a sine wave using the sin function: //title example for generating a sine wave // The example below generates a sine wave "y" based on the value of "x". module sine_wave; real x, y; Silvaco, Inc. E-9

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initial begin x = 0; #1000 $finish; end always begin #1 x = x + 0.1; y = sin(x);// Built-in Silos "sin" function end endmodule

E.3: silos Keyword

SILOS has a reserved keyword silos that is always true. The silos keyword allows you to enclose

silos specific code or commands within a `ifdef/`else/`endif compiler directive so that it will be available for SILOS but not other Verilog simulators, for example: `ifdef silos initial $stopsave(); initial #1000000 $resetstartsave(); `endif When running SILOS, the reserved keyword silos is always true so that you can enclose code or commands that are specific to the GUI within a `ifdef/`else/`endif compiler directive.

E.4: Extensions to Turn-off, Reset and Turn-on Saving of Simulation Data

When running a simulation that creates a large save file, the $stopsave system task can be used to turn off saving to the save file. This can be used to keep the save file size fixed during the portion of the simulation that is of no interest to you. The $resetstartsave system task can be used to reset the save file, and then start saving the simulation history. After the simulation is complete, the simulation history that has been saved after resetting the save file will be available for display with the Data Analyzer. The below example stops saving at time=0, and starts saving at time=1000000: `ifdef silos initial $stopsave(); initial #1000000 $resetstartsave(); `endif

E.5: $save( ) Extension to Create a .cmm File

The $save( ) file Verilog extension system task can be used to save the current state of the simulator in a projectname.cmm file. This allows the simulation to be saved and restored. Saving the simulation can also be invoked from the GUI (see Section 4.13.17:Save Simulation).

Example
always @(posedge trigger) begin $save( ); end

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E.6: Allowing Non-Standard Extensions to Verilog HDL

SILOS has a switch to issue syntax errors for non-standard extensions to the IEEE Standard 1364

Verilog HDL Language Reference Manual. The default setting for the switch is to check for IEEE compliance. To allow all extensions, enter !control .ext=all before inputting your model. The parameters to allow individual extensions are reported in the syntax error for each extension. The following is a sample list of extensions that will be flagged as syntax errors:

E.6.1: Global Variables

Example
wire xx; module ... endmodule
SILOS command to allow this extension:

!control .ext=gvar

E.6.2: Procedural Assignment to Wires:

Example
module foo; wire w; initial w = 1;
SILOS command to allow this extension:

!control .ext=paw

E.6.3: Continuous Assignments to Register and Memory Variables

Example
reg r; assign r = in;
SILOS command to allow this extension:

!control .ext=aar

E.6.4: Continuous Assignments Using Intra-assignment/non-blocking Delays

Example
module foo; wire o, o1; assign o = #4 i; assign o1 <= #4 i;
SILOS command to allow this extension:

!control .ext=assign

E.6.5: Default State Value for UDP

The default keyword for the UDP specifies the state value for the UDP's output when UDP input levels and transitions do not match any of the entries in the UDP table. When the default keyword is not used, the UDP default output state is x.

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Example
primitive udp1 (out, in); output out; input in; table // in out 0 : 1; default: 0; endtable endprimitive
SILOS command to allow this extension:

!control .ext=udpdefault

E.6.6: UDP Additional States for High-Z on Inputs or Output

Example
for row states other than 0, x, 1, such as: Z : 1; <?HV> : 1;
SILOS command to allow this extension:

!control .ext=udpstate

E.6.7: UDP Edge for High-Z

Example
for edges to High-Z, such as: (0Z) : 1;
SILOS command to allow this extension:

!control .ext=udpstate

E.6.8: UDP Multiple Edges in a Row

Example
(01) (01): 1;
SILOS command to allow this extension:

!control .ext=udpstate

E.6.9: Non-Constant Specify Block Delays

Example
for non-constant specify block delay, such as: (in => out) = delay_var;
SILOS command to allow this extension:

!control .ext=ncsd

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E.6.10: Parameter for Specify Block Delays

Example
To support parameters used to specify block delay, such as parameter dly=8 (in => out) = dly;
SILOS command to allow this extension is:

!control .ext=psd

E.6.11: Stimulustable Extension

Example
To support the stimulustable statement, such as: stimulustable ... endstimulustable statement
SILOS command to allow this extension is:

!control .ext=stim

E.6.12: "input/output/inout" Declarations After the Variable's Declaration

Example
module foo (in); wire in; input in;
SILOS command to allow this extension:

!control .ext=inout

E.6.13: Using Registers as Module Inputs

Example
module xx(in); input in; reg in;"
SILOS command to allow this extension is:

!control .ext=rsink

E.6.14: Duplicate Variable Definitions

Example
module foo; wire a; wire a;
SILOS command to allow this extension is:

!control .ext=dvd

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E.6.15: Parameter Used for Sizing Numbers

Example
module foo; reg[7:0] xx; parameter size=8; initial xx = size'b010;
SILOS command to allow this extension is:

!control .ext=psize

E.6.16: Null Statements

Example
module foo; initial begin ;
SILOS command to allow this extension is:

!control .ext=nstmt

E.6.17: Timing Checks Without Edge Specifications for Selected Variables

Example
$recovery( CLR, ...
SILOS command to allow this extension is:

!control .ext=neref

E.6.18: More Precision in "$timeformat" than "`timescale"

SILOS command to allow this extension is:

!control .ext=tfmt

E.6.19: Missing Port Connections Connected to GND for VCS Compatibility

Missing port connections are set to ground for VCS compatibility.
SILOS command to allow this extension is:

!control .skip=.gnd Note: Wires which are otherwise floating still remain HiZ, regardless of !control .skip.

E.6.20: VCS Compatibility Extension

VCS compatibility extension for comma at the end of the port list, i.e.: module (xx(a,):
SILOS command to allow this extension:

!control .ext=portcomma

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E.7: $dumpactivity System Task Extension

The $dumpactivity(<filename>) Verilog extension system task can be used to save node activity count data to file. The activity data file is written at the end of the simulation time. Creating an activity data file allows transition data from multiple simulations to be merged into a single Activity report. Writing the activity data file can also be invoked from the GUI (see Section 4.19.1:Activity Reports Menu Selection). The format of the activity data file is similar to the VCD file format specified the IEEE1364 LRM. The format changes are: The identifier_code used is the Extended VCD format (<integer) The simulation_keyword $dumpactivity has been added. The value_change section has been replaced with the node transition count data.

Example Activity Data File

$date Wed Nov 02 07:53:32 2011 $end $version Silos 4.10.126.C Activity Format 1.0.0 $end $timescale 1ns $end $scope module stimulus $end $var wire 1 <17 newspaper $end $var wire 1 <18 pad $end $scope module vendY $end $var wire 1 <19 coin[1] $end $var wire 1 <20 coin[0] $end $var wire 1 <21 clock $end $var wire 1 <22 reset $end $var wire 1 <17 newspaper $end $var wire 1 <18 pad $end $var wire 1 <23 enable $end $var wire 1 <24 NEXT_STATE[1] $end $var wire 1 <25 NEXT_STATE[0] $end $var wire 1 <26 clock_ $end $upscope $end $upscope $end $enddefinitions $end #1460 $dumpactivity <17 0 0 1 1 N <18 0 0 1 1 N <25 0 0 1 1 N <24 0 0 1 1 N <26 0 0 2 2 N $end

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E.8: `uselib Compiler Directive

For library searching, the program also supports the `uselib compiler directive. The format for `uselib is: `uselib where: filename is the full path name for a file containing one or more module definitions that are searched to complete unresolved instantiations. directory_name is the full path name for a directory of files whose names are a concatenation of the name of a module definition and a file extension, such as dff.v. file=filename dir=directory_name

Some examples of `uselib are: This example uses `define to specify macros for the `uselib. This makes it easier to change the library paths. `define `define `uselib asic1 dir=c:\actel\lib\vlog asic2 file=d:\library\udp.v `asic1 `asic2 libext=.v

This example uses specifies the same `uselib without using a `define. Notice that the libext keyword for the library file name extensions is required when specifying a directory dir specification for a directory of library files. `uselib file=\test\lib\udp.v dir=\test\lib2 libext=.v

E.9: System Commands Passed as Command Line Arguments

The program allows system commands to be passed as command line arguments (i.e., -"!system \"ls -lt\"" ).

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Appendix F: Message Codes for Lint

Message Code 0x200 0x400 0x500 0x502 0x540 0x580 0x5c0 0x5e0 0x5f0 0x600 0x680 0x690 0x700 0x760 0x800 0x900 0x1000 0x1800 0x1c00 0x1e00 0x2400 0x2600 0x2700 Message Content If a case item appears after the default item, the case item will not be processed. The value for an alias must be either a simple identifier, or an identifier with an index or range constraint (e.g. x y(1) z(3 downto 0)). Blocks should always start with an event statement. Two or more clock edges are used in an always construct. Didn't find any architectures for an entity. The architecture type should be one of the following: rtl (synthesis), sim (behavioral), str (structural), tb (testbench) (RMM1-5.2.3). The operand is not of the right type. The index dimension size does not match its declared dimension size. Non-blocking assignment (<=) should not be used in function. Assigning to a supply net. Continuous assignments require '='. 'x' is used for assignment (Do not assign 'x' except for the default clasue of a case statements). The signal for a reg is not an input to the module. reg has both asynchronous and synchronous reset. The operands of an expr have unequal sizes; leading zeros will be padded. In the conditional(?) expression, the left and right operands of the colon (:) have unequal sizes; leading zeros will be padded. Couldn't open the initialization file; couldn't open the configuration file; are you sure you have write permission in the current directory? Couldn't invoke ATMEL component generator; check that it exists on your search path. Set the environment variable to the directory where the Atmel technology libraries are located The event appears inside a process that doesn't have it in its sensitivity list. The parameter doesn't exist in module: defparam. The size of the address for ram is too large. Changing size of constant; extending bit value to accommodate the change.

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Silos Users Manual Message Code 0x2720 0x2740 0x2780 0x27c0 Message Content The bits' of a reg is multiply driven. The bits' of a reg is unset. The bits' of a reg is unused. Avoid using the BIT and BIT_VECTOR types because many simulators do not provide built-in arithmetic functions for these. Use STD_LOGIC and STD_LOGIC_VECTOR instead, and remember to add use ieee.std_logic_arith.all; to your code. A reg is assigned values with both blocking and non-blocking assignments. A reg is assigned values with multiple nonblocking assignments. A block appears to have substantial logic in it; you may want to re-partition the block. A blocking assignment is used in an always construct which generates a flip-flop. A reg has an unknown value in an expression. Found a task enable in a sequential/combinational block. Boolean expr is more than 1 bit wide. Boolean (truth table) coding will make your code more difficult to read, so you may want to avoid using it. A branch is always false. Expected an expression to evaluate to a constant, but it didn't. Function call is used as an asynchronous reset in an always construct. division/trigger/ will be ignored during synthesis. Synthesis may prefer the logical comparison over the case comparison. The case expr is too large for its case selector. The case expr is not the same size as case selector. The X/Z bit in the statement is not a don't care bit. The clk signal is an expr (rather than a single variable). Use the same name for all clock names derived from the same source. The clock signal is connected to clock port of an instance (RMM1-5.2.1). Clock is used as D input of a flip-flop. Found a comparison between 0 and a reg (non-negative value). The variable is in a combinational loop. Found a nonblocking assignment within a combinational always block. The port/genetic of a component doesn't exist in the entity.

0x2800 0x2900 0x2a00 0x2b00 0x2c00 0x2d00 0x2e00 0x2e80 0x2f00 0x3000 0x3100 0x3200 0x3280 0x3300 0x3400 0x3420 0x3440 0x3450 0x3455 0x3460 0x3480 0x3500 0x3600

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Message Codes for Lint Message Code 0x3800 0x3840 0x3850 0x3852 0x3856 0x3860 0x3880 0x3900 0x3a00 0x3a80 0x3b00 0x3b80 0x3b90 0x3c00 0x3d00 0x3e00 0x4100 0x4200 0x4600 0x4800 0x4a00 0x4c00, Message Content All constants specified in a concatenation expression must have a specified size; one of your concat exprs has an unsized constant. Found a constant conditional expr for case/for/if/while. A reg is assigned with 'x' while used in a condition expression of an if statement A reg is assigned with 'x' while used as a case selector, which does not assign 'x' in default clause. A reg is assigned with 'x' while used as casex selector. Cannot find an architecture for the entity. Case item expr is not constant. Delay value is not constant. The repeat value in a multiple concatenation must be a constant. The bit constant has an 'x' bit. The bit constant has a 'z' bit. The asynchronous reset value for reg is not a constant. Bit width is not specified for a constant used in a conditional exprssion. Cannot assign to a reg in a continuous assignment. The synthesis will infer a counter for a register. Found control character. Macro string is defined outside its module by "define". The macro is not used before its removal. A delay is not always used in a construct that generates a flip-flop. Found an 'x' or 'z' bit in a delay expression. A module has more than 1 clock; your design may be unstable. The reg expressions, and the reset expression for the reg appears in different statements; you may have different simulation results before and after synthesis. The clock signal isn't clocked directly by a chip pin when the scan control is active. Found assignments to the same register in different always blocks. Use $strobe instead of $display for displaying a variable in a nonblocking assignment. Put the combinational part of the state machine into a separate always block (this is generally required in the Design Compiler). Arithmetic or logical expression is used as operand of divide (or modulus) operation

0x4c80 0x4d00 0x4d40 0x4d80 0x4d90

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Silos Users Manual Message Code 0x4da0 0x4db0 0x4dc0 0x4e00 0x4e10 0x4e20 0x4e40 0x4e50 0x4e60 0x4e80 0x4ec0 0x4ee0 0x4f00 0x5000 Message Content The size of the left hand of the division (or modulus) operator exceeds 12 bits. The size of the right hand of the division (or modulus) operator exceeds 8 bits. The signal passes from one clock domain to another through too many synchronizers. The library doesn't have a flip-flop with both asynchronous set and asynchronous reset; it will construct one. Found a dubious bit-select or part-select. The block is empty. Found a big-endian declaration (if this is what you want, remove the "-little_endian" command line option) (RMM1-5.2.1). Characters other than alphanumeric and underscore are used Found an event variable in the expression. To avoid different simulations results before and after synthesis, use "or" rather than "||" in sensitivity lists. A variable in a sensitivity list is being modified inside the event stmt. Cannot use an event in this context; events can be used only in trigger stmts and event control exprs. To avoid different simulation results before and after synthesis, avoid using operators other than "or" in event controls. If you currently use a '|' symbol in an event list, it is recommended that you change this to an "or" to avoid simulation mismatches before and after the synthesis. The range is specified for a variable in a sensitivity list. An event is never triggered. The expression is being assigned to an lval with different sizes; some bits may be dropped. Redundant default clause in a case stmt. Cannot specify more than 1 edge symbol (r, R, f, F, p, P, n, N, *) per sequential UDP table row; the remaining symbols must be level symbols (0, 1, x, X, b, B,?). Too many arguments specified to the function; extra arguments will be ignored. Too many parameters specified. Too many instance exprs specified. Cannot specify drive strengths for instances of module. Drive strengths can be specified only for gate and primitive (UDP) instances, but not module instances.

0x5040 0x5060 0x5080 0x50c0 0x5100

0x5300 0x5500 0x5a00 0x5c00

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Message Codes for Lint Message Code 0x5c80 0x5d00 0x5e00 0x5f00 0x6000 0x6010 0x6020 0x6040 0x6080 0x6100 0x6180 Message Content It's not necessary to specify the reduction-or operator '|' in event stmt. Cannot specify bit-select or part-select for a scalar. Cannot specify task enables inside functions. No clock pin found on a module. Cannot open file. Output port is connected to a fixed value. The file was mapped to multiple libraries. Error (highest priority) message was filtered out via --filter_errs. Arrays are faster to simulate than FOR loops. You may want to consider using array assignment rather than a FOR loop. Index of the FOR loop is not an integer. Avoid using FOR loops in sequential blocks for synthesis; if possible, use array assignment instead. If this isn't possible, put your FOR loop into a function and call the function. The synthesis cannot process the FOR statement because the conditional expression is not constant. The synthesis will infer a state machine for a reg. The values for the state vector should be set using `define (e.g. `define STATE0 0). FSM will have a latch synthesized before its state register. All cases are not covered in a "full_case". A full "case" stmt has a "default". Illegal assignment to a reg; the reg should be defined in the function context. Cannot declare inouts or outputs in functions. A variable is used in an expression in function. You are advised to make this an input to the function to prevent mismatches in the simulations before and after synthesis. The expr connected to port of function have unequal sizes. The last statement in the function should be an assignment to itself. The function is not fully specified; there may be some combinations of inputs that will cause a variable to be unassigned. The function output is not assigned yet. Assigning more than once to the function reg. Event triggers are not allowed in function definitions. The function is unused.

0x6200 0x6240 0x6260 0x6270 0x6280 0x62c0 0x6300 0x6500 0x6a00

0x6b00 0x6d00 0x6e00 0x6e80 0x6f00 0x7000 0x7400

Silvaco, Inc.

F-5

Silos Users Manual Message Code 0x7600 0x7800 0x7880 Message Content Avoid making instances of gates in the design because they make it hard to read, and difficult to maintain and reuse. The gate output (left-most expression in instance of gate) must be a single-bit. Avoid gating the reset signal of flip-flops and latches. If you are adding a test control signal, you can omit it because DFT tools will automatically insert test signals for you. Found an unrecognized keyword in one of your perl programs; check the spelling. Avoid using the hard-coded numeric constants in the design. Instead, define a constant with this value and use the constant. Have a header at the top of every source file (RMM1-5.2.4). The same name is declared as different type, which will cause visible problems. The hierarchical (dotted) name will be ignored during synthesis. Identical identifiers are used (only different in capitalization). The first character of an identifier should be a letter [a-zA-Z]. The identifier contains some of the words (VDD, VSS, VCC, etc.). Arithmetic operation is used in the conditional expr of the if statement. The if stmt is nested too deeply. You don't need to specify "if (expr)" because a prior "if" expr has the negation of the expr. Found an "if ... else if" stmt; perhaps you should consider changing this to a "case" construct (RMM1-5.5.7). Found an implicit net. Include an absolute file name path (better to use a relative path). Indent 2 spaces at a time to make the code more readable. The loop index is being modified. The index expr has too many bits for a variable. The selected expr doesn't have enough bits for a variable. Found an 'x' or 'z' in an index expr. Wrong component name for instance. Inout is connected to output/input. An instance already exists, or the instance name used again. You may want to consider selecting an instance name that contains the name of the module in it.

0x7900 0x7a00 0x7c00 0x8000 0x8400 0x8420 0x8450 0x8480 0x8490 0x8500 0x8580 0x8600 0x8800 0x8840 0x8880 0x8900 0x8980 0x8a00 0x8c00 0x8e00 0x8f00 0x9000 0x9100

F-6

Silvaco, Inc.

Message Codes for Lint Message Code 0x9180 0x9300 0x9400 0x9600 0x9800 0x9900 0x9c00 0x9d00 0x9e00 0xb000 0xb300 0xb400 0xb600 0xb900 0xba00 0xbb00 0xbc00 0xbe00 0xbf00 0xc000 0xc100 0xc200 0xc300 0xc380 0xc390 0xc400 Message Content Specify the instance name for the instance of a module. Illegal connection to a port of instance. The clock name should have a "CLK_" prefix (or user specified) (RMM15.2.1). Not enough arguments specified to function. Inexact number of arguments specified in an instance. The number of instance parameters specified is less than the number of module parameters declared. Inexact number of arguments specified in an instance. The port connections to instance are by position (and hence not by name). Assigning a real (floating point) number to an integer. Assigning a 0/1 (32 bits) to a single bit object. Inferring a variable for undefined module. The input is declared as an integer. The levels of logic for fanin of output/input/ are too many. The flag value is unrecognized for "lint_info()". The library directory was not needed. The library file has at least 1 syntax error that's been disabled by -no_lib_warns. The library file was scanned but not used. The module from the library file was not used. The only module in the file doesn't have the same name as the root of its file name. The module name same as a library cell name. The library specified in a "use" clause is not declared. The signals and ports that are connected should have similar names (RMM1-5.2.1). Found a long line; you may want to keep the source line lengths shorter to increase readability and reusability (RMM1-5.2.7). The operand to bit-not operator "~" is a single bit; consider using the logical-not operator "!" instead. Some logic is located between flip-flops with different asynchronous clocks, which may cause metastable issues. The parameter is rather long; you may get long design unit names during elaboration in synthesis (RMM1-5.2.1).

Silvaco, Inc.

F-7

Silos Users Manual Message Code 0xc500 0xc600 0xc800 0xcc00 0xd000 0xd020 0xd040 0xd080 0xd120 0xd100 0xd180 0xd200 0xd500 Message Content There are more than 10 loops in the for loop which contain logical/relational operations. The logical-or operator "||" appears inside of a sensitivity list; did you perhaps mean the keyword "or"? This is just an advisory. lsb is out of range. found scan clk. Couldn't find macro library; check that EDS_LIB is set properly, and make sure that the library exists. The module appears to have both mapped and unmapped parts in it. You may get suboptimal results synthesizing the arithmetic operator. The index for memory is out of declared range. The identifier in generate loop assign does not match the identifier in loop initial assign. No architecture exists for entity. Cannot find block. The output not found in the module port list. Cannot mix named and positional port connections in structural instances, they must either be all named or all positional (e.g., X Y( A, B ) is Ok , X Y( .A(A), .B(B) ) is Ok, but X Y( .A(A), B ) is not. Signal is used as clock and reset at the same time. Avoid using both positive-edge and negative-edge triggered flip-flops within a module. The module expression doesn't evaluate to a constant. Module/instance name should has characters in length between 2 and 32. You need more comments in your design file. Part/bit select out of the declared range. There are at least 2 edges in an event statement, but the synthesis may require only 1 of those edges. Multiple if/case statements found in an always construct. The integer is declared again. Found multiple connections to a port. More than 1 module defined in a file. Multiple reset signals for a reg. The identifier is not completely lowercased; use lowercase for all signal, variable and port names (RMM1-5.2.1).

0xd550 0xd600 0xd700 0xd750 0xd800 0xda00 0xdb00 0xdb50 0xdc00 0xdd00 0xdd40 0xdd80 0xddc0

F-8

Silvaco, Inc.

Message Codes for Lint Message Code 0xdde0 0xde00 0xdf00 0xdf20 0xdf80 0xe000 0xe040 0xe080 0xe0c0 0xe100 0xe120 0xe140 0xe180 0xe1a0 0xe1a4 0xe1b0 Message Content The identifier is not completely uppercased; use uppercase for all constants and user-defined types (RMM1-5.2.1). Need an expression for each gate terminal. A variable is used in an event stmt but not listed in the sensitivity list. The identifier must be declared as "genvar". The argument to function is an expression (as opposed to a single identifier or constant). The expected constant expression. The module should have synopsys template in a comment within its definition, according to instance its instance. The task is not defined. The delay value is negative. Although negative ranges and bus indices are supported in Verilog simulators, they are not supported in synthesis. A negative value is assigned to the integer. Synchronizing a flip-flop (sampling a signal from a different clock domain) is clocked on the negative edge of the clock. The expression following "posedge"/"negedge" must be a single bit expression. The event control has a nested event control. The loop index is nested in generate-loop. Could not process attribute; you may need to restructure your expression so that the attribute (e.g. for clock signals) can be properly processed. No default clause for case stmt. Couldn't find the definition for the module specified in dp_bind directive. No "else" clause for the "if" stmt. Cannot find entity for architecture. No field has a specific name for a variable. The undefined function is used in expr. The declared function doesn't have a corresponding function body. No inputs declared for module. Cannot find instance in architecture. Cannot use the integer in this context. The port is not found on the module.

0xe1c0 0xe400 0xe480 0xe500 0xe580 0xe600 0xe700 0xea00 0xea80 0xeb00 0xec00

Silvaco, Inc.

F-9

Silos Users Manual Message Code 0xec80 Message Content Cannot infer memory macros yet in this version. You can still use memories, provided you specify addresses that evaluate to constants (e.g. parameters, integers, etc.). Couldn't find the definition for instance. No outputs declared for the module. Cannot use a real number in a memory or range index. Found a delay within a non-blocking assignment. The identifier cannot be accepted by the IDL reader; it will be renamed to unless you make it start with a letter [a-zA-Z]. Not of a RECORD type. Your VHDL design cannot be transferred to Verilog; there is no Verilog equivalent. Found a null stmt. Be conservative in the number of subtypes defined. You've defined too many subtypes in an entity. Found the numerical type that may not be synthesizable. The output port isn't registered (RMM1-5.6.1). The output is tied to SUPPLY0. The case item value appears more than once. Found a parameterized macro definition. The parameter is declared more than once. The parameter value should be clarified by 'b, 'o,'h,'d The parameter is unused. The bit width of parameter is greater than 32, you should specify the bit width. The polarity on the reset signal doesn't seem right. The instance expressions connected to the port of instance have incompatible sizes. The port declaration order is not ideal; recommended ordering is: 1) inputs 2) outputs 3) inouts. The range for port is not consistent between the port declaration and the input/output declaration. Leave a blank line between ports to improve readability of your code. casez may be preferable over casex. The primitive is a top-level module (i.e., is not used as an instance anywhere).

0xed00 0xee00 0xee80 0xeec0 0xef00 0xef20 0xef40 0xef80 0xf400 0xf480 0xf500 0xf600 0xf800 0x10100 0x10200 0x10620 0x10600 0x10640 0x106c0 0x10700 0x10780 0x10800 0x10900 0x10b00 0x10c00

F-10

Silvaco, Inc.

Message Codes for Lint Message Code 0x10d00 0x10d80 0x10e00 0x11300 0x11700 0x11a00 0x12000 0x12400 0x12500 0x12600 0x12680 0x126c0 0x12700 0x12800 0x12900 0x12a00 0x12a40 0x12a60 0x12a80 0x12c00 0x12c40 0x12c80 0x12c90 0x12c96 0x12ca0 0x12cc0 0x12cd0 0x12d00 0x12d80 0x12d86 Message Content The system task argument number is mismatched. Name the process using a label that has the "_PROC" suffix. Skipping over protected region. Pullup and pulldown instances should not have 2 drive strengths specified. Detected a potential race condition. The direction of the range is not correct. The range expression is not a constant expression. The order of left and right indices in part-select is backwards. Reading from output port. Cannot use a real (floating point) operand in the expr. The delay value is real (a non-integer constant). Assigning the integer to a real variable. The function is used recursively in itself. The module has an instance of itself. The alias is declared again. The function is already defined; redundant definition. The identifier is declared more than once. The macro is redefined. The module is declared more than once. A variable can't be declared as an input port because it's already declared as an output port. Re-declaration of reg. Re-declaration of task. The operation is redundant (i.e., will not do anything). Signal (output of a flip-flop) is used as a clock of a reg. The synthesis will infer an enabled flip-flop. The synthesis may infer a flip-flop for a reg. A reg is generated as a flip-flop with non-changing input. Declaration inconsistency; inputs cannot be declared as regs also. The synthesis will infer a latch for a reg. Some bit of a reg will be synthesized into latch with asynchronous reset/ set.

Silvaco, Inc.

F-11

Silos Users Manual Message Code 0x12d90 0x12e00 0x12f00 0x12f20 0x12f40 0x12f80 0x12fc0 0x12fd0 0x12fe0 0x13000 Message Content Flip-flop inferences with and without asynchronous reset are mixed. The range of a reg is not consistent with the range of output port. A reg will be synthesized into a flip-flop that doesn't have an asynchronous set or reset signal. The signal (output of a flip-flop) asynchronously sets or resets. A reserved Verilog keyword shouldn't be used as an identifier in your design for portability reasons (RMM1-5.2.9). Using reset signal as a data input. The same identifier is used as different types; change one so that you have unique names in your design. The synthesis may infer a ROM structure for reg. The blocking assignment to the identifier will not trigger the event statement it is in. Couldn't find a signal in the event list for an event statement. Add it to the event list, otherwise you may have differing simulation results before and after synthesis. Found a blocking assignment within a sequential always block. The synthesis will infer a shift reg. The shift value is not constant. The right operand of a shift-left operator (<<) is non-constant, and has a large bit width. This could lead to either a very large expr or overflow. Have a short description for every signal you define; moreover, the description should appear on the same line as the signal. The signal name should have a specific (user defined) prefix/suffix (RMM1-5.2.1). Potential write-write/read-write race condition detected. Not enough bits in an the expression. More than two ports are declared on the same line; you're recommended to declare them on separate lines (RMM1-5.2.10). Found white space between the size and base specifier of constant. Found paralell in a comment; should this be spelled parallel? Found more than 1 stmt on a single line (RMM1-5.2.6). Avoid using the STD_ULOGIC and STD_ULOGIC_VECTOR types because resolution functions required for three-state buses are generally not provided for these types in the IEEE standard library. Use STD_LOGIC and STD_LOGIC_VECTOR instead. Un-terminated string.

0x13200 0x13280 0x13300 0x13320 0x13340 0x13380 0x133c0 0x13400 0x13600 0x13700 0x13800 0x13840 0x13860

0x13870

F-12

Silvaco, Inc.

Message Codes for Lint Message Code 0x13880 0x13900 0x13980 0x13a00 0x13b00 Message Content A reg doesn't have a synchronous set or reset. `ifdef may not be supported by all synthesizers. Using "full_case" may cause mismatches in simulation before and after synthesis. The system task enable will be ignored during synthesis. Found a tab character. Avoid using tabs because they make the appearance of code unpredictable in different editors and different user setups (RMM1-5.2.8). Found an extra text following a message tag. Incorrect number of arguments in task enable. Found assignment to reg (global variable) inside a task. The task enable will be ignored during synthesis. Top level module/port name has 16 or more characters. Top level module/port name has upper and lower case letters. The task is unused. Too many bits specified for a bit constant. More than one top-level module. Couldn't find corresponding translate_on for translate_off. The signal name should have a specific (user defined) prefix/suffix (RMM1-5.2.1). Tristate buffers can degrade design performance. Triggering reg (as opposed to an event). Synthesis will infer a tristate. The tristate signal is not a single variable. Tristate is found in the module (not a top-level module). The `timescale value must be either 1, 10 or 100. Found a double-negative (~ ~) in an expr. The output port not assigned any value. By default, it will be assigned 0. The port is not connected. The function not declared. Top level module/port name end with '_'. Top level module/port name has consecutive '_'. Undeclared identifier OR variables is genvar type, which cannot be accessed here. F-13

0x13b80 0x13c00 0x13d00 0x13e00 0x13e60 0x13e80 0x13f00 0x13f80 0x14100 0x14200 0x14400 0x14600 0x14500 0x14800 0x14a00 0x14c00 0x14d00 0x14e00 0x15000 0x15200 0x15300 0x15400 0x15500 0x15600

Silvaco, Inc.

Silos Users Manual Message Code 0x15900 0x15c00 0x15c40 0x15c60 0x15c80 0x15d00 0x15d80 0x15e00 0x16000 0x16100 0x16300 0x16400 0x16450 0x16500 0x16800 0x16c00 0x17000 Message Content A variable is not declared as an assignable net; it must be of a wire type. The port appears in the port list of module, but isn't defined as an input, inout or output. Attempting to `undef the macro (not defined yet). The system task is not recognized. Some bits of a variable listed in a sensitivity list were not used within the event stmt (this is generally Ok). A variable is declared in an event list, but not used in the event statement. The macro module is not used in any other module. Cannot open file for writing. Use signals (as opposed to variables) when writing synthesizable VHDL code. Assigning reg to itself (this may cause problems in your design or may not be needed). Ambiguous (non-blocking) assignment to reg. Arithmetic operator aside from loop variables is used in a for statement. Signal/port/function/parameter name should has characters in length between 2 and 40. Place entity, architecture and configuration sections of your design into the same file to make the design easier to maintain. Cannot have a null expr. Cannot use a wait stmt within a process that has a sensitivity list. Net declarations that also have continuous assignments cannot have a concatenation as the lval, each net must be declared and assigned individually. The wire declared after it's used. An identifier cannot be declared as wire/reg because it's already declared as a reg/wire. Found positive edge clock. Potential write-write/read-write race condition detected. The result of comparison to 'Z' is considered false. Avoid using zero-delay (#0) assignments. Dividing by zero.

0x17400 0x17c00 0x17e00 0x17f00 0x19c00 0x1a400 0x1a800

F-14

Silvaco, Inc.

Message Codes for Lint Message Code 0x103000 Message Content The case item expr doesn't have the same number of bits as the case selector. The case will never be executed unless you make the size the same. Couldn't invoke macro binder. Too many clock signals for a reg. Expected a variable to be a reg. The clock isn't specified in an event expr. Couldn't open temporary file. Check that you have free space in that directory. Bad bit in constant. Didn't find a closing quote for module name in dp_bind compiler directive. An acceptable value for the charge strength of a TRIREG net; it must be either small, medium or large. Found the non-decimal bit in the decimal number. Found "endif" inside of an "if" statement; did you mean "END IF" (two words)? The event controls are not allowed in functions. Extraneous `else found. Extraneous `endif found. Missing `endif; make sure you have an `endif for each `ifdef. Delays are not allowed in functions. Missing name of a variable in `ifdef. `include is recursive. Problem with an `include directive in your source; syntax for the `include directive is: `include "foo.v". The initial statement will be ignored during synthesis. The delay will be ignored during synthesis. Couldn't find the specified file in the `include directive. The text macro was not defined prior to usage. The number of input symbols you specified in a UDP table entry is not correct. The named block was already defined; you cannot redefine the named block. This word is a reserved word that's used internally, please select a different identifier so that the software will not be confused.

0x10d000 0x10d800 0x10e000 0x10e800 0x10f000 0x202000 0x202800 0x203800 0x204000 0x204400 0x204800 0x205000 0x205500 0x205a00 0x206800 0x209000 0x209180 0x209200 0x209500 0x20e200 0x20e400 0x20e600 0x20f000 0x20f800 0x210000

Silvaco, Inc.

F-15

Silos Users Manual Message Code 0x210f00 0x211000 0x2f0000 0x302000 0x305000 0x30e000 0x315000 0x315500 0x316000 Message Content Illegal symbol in UDP table; a table symbol must be one of the following: 0, 1, x, X,?, b, B, r, R, f, F, p, P, n, N, *, -. Illegal symbol in UDP table; an output symbol must be one of the following: 0, 1, x, X. The sized constant has zero size. The identifier is currently used by VRC to break out a bit of bus; please change the name of the net declaration to something else. The expr connected to output port must be either a single identifier or a concatenation of identifiers; please check your HDL source. Couldn't find an appropriate D flip-flop for a reg in the current library. Looking for a cell with the following attributes: muxed input. A reg (derived from a RECORD structure) is not assigned any value. Found an unknown bit in an expression. Cannot write an out module (an FSM implementation) in Verilog format; either select a different format, or disable the FSM extraction in your input source.

F-16

Silvaco, Inc.

Appendix G: STARC Rule Message Codes for Lint

STARC Rule Number 1.1.1.2

Rule Content Only alphanumeric characters and the underscore '_' should be used, and the first character should be a letter of the alphabet. Key words in Verilog-HDL(IEEE1364), VHDL(IEEE1076.X) must not be used. Names containing "VDD ", "VSS", "VCC", "GND" or "VREF" must not be used (upper case or lower case). Do not distinguish names by using upper or lower case English letters (Abc, abc). Do not use the same instance name or cell name as the ASIC library being used. Module names and instance names should be between 2 and 32 characters in length. Signal names, port name, parameter name, define names and function names should be between 2 and 40 characters in length. Specify the bit width if it is greater than 32 bits (Verilog only). Do not use feedback in combinational circuits. Do not have both asynchronous reset and synchronous reset on the same reset line. To avoid meta stable conditions, do not locate logic betweenasynchronous clocks. Describe every case statement expressions in a functionstatement. The function statement should not be used for asynchronousreset line logic in an always construct for FF inference. A non-blocking assignment (<=) should not be used in function statements (Verilog only). All arguments are defined as function statement inputs. Clock edge descriptions should not be used in task statements (Verilog only). Match the argument bit width with the bit width of the function statement input declaration (Verilog only). Match the return value bit width with the bit width of the assignment destination signal (Verilog only).

Lint Message Codes 0x8450, 0x4e50

1.1.1.3 1.1.1.4 1.1.1.5 1.1.1.10 1.1.2.1 1.1.3.3

0x12f40 0x8480 0x8420 0x12f40 0xd750 0x16450

1.1.4.9 1.2.1.3 1.3.1.6 1.5.1.1 2.1.1.2 2.1.2.1

0x10640 0x3480 0x760 0xc390 0x6e00 0x3100

2.1.2.2 2.1.2.3 2.1.2.5 2.1.3.1 2.1.3.2

0x5f0 0x6a00 0x3200 0x6b00 0x13400

Silvaco, Inc.

G-1

Silos Users Manual STARC Rule Number 2.1.3.5 2.1.6.5 2.2.1.1 2.2.2.1

Rule Content In a function statement, global signal assignment should not be performed (Verilog only). For an array index, 'x' and 'z' should not be used. Latches are generated unless all conditions have been described. All signals at the right of the conditional expression andthe assignment statement in the always constructs of the combinational circuit must be defined in the sensitivity list. Multiple event expressions should not be described withalways constructs (at least one event expression is required). Do not mix blocking assignments (=) andnon-blocking assignments (<=) in combinational always construct. Do not assign over the same signal usinga non-blocking assignment for combinational circuit. Do not assign over the same signal in an always construct for sequential circuit. Use non-blocking assignment in FF inferences. Do not use unsynthesizable FF inference styles. Specify delay values with integral numbers and do not use negative delay values. In FF inference with asynchronous reset, pay attention to the negedge or the posedge of the reset signal. Do not use both asynchronous set and reset. Do not mix blocking and non-blocking assignments inFF inference always construct (Verilog only). Do not use two or more different clock edges within a single always construct. Do not use two or more identical clock edges within a single always construct. Do not specify FF initial values explicitly in initial constructs (Verilog only). Logic synthesis ignores initial constructs, so it should not be used. Do not connect two or more outputs other than tri-state buffers, even under the same conditions. inout should not directly be connected to input/output.

Lint Message Codes 0x6300 0x8c00 0x12d80 0xdf00

2.2.2.3

0xe1a0

2.2.3.1 2.2.3.2 2.2.3.3 2.3.1.1 2.3.1.2 2.3.1.5 2.3.1.6 2.3.1.7 2.3.2.2 2.3.3.1 2.3.3.2 2.3.4.1 2.3.4.2 2.5.1.5 2.5.1.6

0x2800 0x2900 0x2900 0x2b00 0x3200 0xe0c0, 0x12680 0x106c0 0xdd80 0x2800 0x520 0x520 0x209500 0x209500 0x2720 0x8f00

G-2

Silvaco, Inc.

STARC Rule Message Codes for Lint STARC Rule Number 2.6.2.1 2.6.2.2

Rule Content Do not describe more than one if or case in one always construct. Signals assigned in always construct should not be described on the sensitivity list in the same always construct. Do not use fork-join in RTL descriptions (Verilog only). Describe a default clause at the end of a case statement (Verilog only). Do not describe variables (or the expression: a+b) in the clause of a case statement (Verilog only). Initial value and conditions of for statement should be constant; in addition, do not change the values within a loop variable. Do not describe any arithmetic operations other than with loop variable and constant. Do not compare with x or z. Do not assign x except for the default clause of a case statement. Do not use values including x or z. Specify bit width for constants used in conditional expressions (Verilog only). Do not assign negative value to integer. Do not use division. For component instantiations, connect ports by name connections, not by ordered list. Match the bit width of the component port and the bit width of the net to be connected. The clocks must be able to be controlled directly from external input ports. The reset for the FFs must be able to controlled directly froman external input port. A clock must not be connected to the D input of a FF. Do not mix clock lines and reset lines. Do not connect the output of a FF directly to the asynchronous set or reset pin of a FF. Do not connect the output of a latch directly to the asynchronous set or reset pin of a FF.

Lint Message Codes 0xdb50 0x4ec0

2.7.4.3 2.8.3.5 2.8.5.3 2.9.1.2

0x3200 0xe1c0 0x3880 0x6100, 0x6200

2.9.2.1 2.10.1.4 2.10.1.5 2.10.1.6 2.10.3.6 2.10.4.5 2.10.6.6 3.2.3.1 3.2.3.2 3.3.1.1 3.3.1.4 3.3.3.1 3.3.6.2 3.3.6.3 3.3.6.4

0x16400 0x3200 0x690 0x3a80 0x3b90 0xe120 0x3200 0x9d00 0x10700 0x700 0x700 0x3455 0xd550 0x12f20 0x12f20

Silvaco, Inc.

G-3

Silos Users Manual STARC Rule Number 1.1.1.6 1.1.1.9

Rule Content Do not use an _ at the end of the primary port name or module name, and do not use _ consecutively . At the top level, module names and port names should consist of 16 or fewer characters and should not be distinguished by upper or lower case alphabet letters. Use `define definitions declared in the same module only (Verilog only). Fixed values should not be connected directly to output ports. Clarify <value>b,h, d, o specification for parameters (Verilog only). Designs should use a single clock/single edge as much as possible. Do not use asynchronous set/reset pins for anything other than initial reset. Do not use a FF with both asynchronous set and asynchronous reset. Do not insert logical operands in a reset line at the local module. Do not insert signals other than initial reset to FF asynchronous reset pins. Creating modules for circuits that supply clocks separately. Do not input a FF output pin to other FF clock pins. Do not supply clock signals to pins other than FF clock input pins. Do not use FFs with inverted edges. task statements should not be used (Verilog only). A function statement should end with a return value assignment. Logical operator should not be used for vector (Verilog only). Do not use delay values which infer FFs except in always constructs. Do not use descriptions which to generate FFs having fixed input values. Do not mix FF inference with and without asynchronous resets in the same always construct.

Lint Message Codes 0x15400, 0x15500 0x13e60, 0x13e80

1.1.4.4 1.1.4.6 1.1.4.8 1.2.1.1 1.3.1.3 1.3.1.7 1.3.2.1 1.3.2.2 1.4.1.1 1.4.3.2 1.4.3.4 1.4.3.6 2.1.2.4 2.1.3.4 2.1.4.5 2.3.1.4 2.3.5.1 2.3.6.1

0x4100 0x6010 0x10620 0x4a00, 0xd600 0x7880, 0x12f20 0xdd80 0x7880 0x12f20 0x700 0x12c96 0x3455 0xd600 0x13e00 0x6d00 0x2e00 0x4600 0x12cd0 0x12d90

G-4

Silvaco, Inc.

STARC Rule Message Codes for Lint STARC Rule Number 2.4.1.1 2.4.1.3 2.7.1.3 2.7.2.2 2.8.1.3 2.8.1.4 2.8.3.4 2.8.3.6

Rule Content Clearly distinguish a latch inference from the logic in other combinational circuits. Do not use latches with an asynchronous set/reset. if statement in combinational circuit ends with else (not with else if). Avoid describing conditions that will not be executed. Avoid the overlapping of case items. Always add default clauses. Do not use the signal to which a dont-care condition is assigned for a conditional expression of if statement. Do not use the signal to which dont-care condition is assigned for selection expression of case statement which does not assign x in default clause. Do not use the signal to which dont-care condition is assigned for selection expression of a casex statement. Do not force parallel_case in a case statement directives that depends on a particular logic synthesis tool (Verilog only). Do not describe fixed values in the selection expression of a case statement (Verilog only). The range of the number of loops is up to 10 if operating logically or relationally other than with loop variable and constants. Match the bit width of assignment signal and operand of logical operator (Verilog only). The bit width of the right-hand side assignment should not be wider than the left-hand side of the assignment (Verilog only). Pay attention to bit widths when assigning integer to reg or wire (Verilog only). Do not use arithmetic operation in the conditional expression of if statement. Make the file names specified by `include should be made into relative paths (../include/common.h) (Verilog only). Do not use defparam statements (Verilog only).

Lint Message Codes 0x12d80 0x12d86 0xe480 0x3840 0xf800 0xe1c0 0x3850 0x3852

2.8.3.7 2.8.5.1

0x3856 0x13980

2.8.5.2 2.9.2.3

0x3840 0xc500

2.10.3.2 2.10.3.3

0x800 0x5080

2.10.4.3 2.10.7.1 3.2.2.4

0x13400 0x8490 0x8840

3.2.4.3

0x3200

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Appendix H: XML Project File Format

The XML-based format for project files was introduced in Version 4.12.1 of the program. The same format is used for all programs that use the SILOS GUI (SILOS, HYPERFAULT and HARMONY). Project files in the original (.spj) format, selected as the current project file, will be automatically converted to the XML project file format (.spjx). The program will only save project files in the XML format. The command line option (-converttoxml) can be used to do a batch conversion of an existing project file. Running the program with this option will convert a .spj formatted project file to the XML project file format and exit (e.g., silos -converttoxml myproj.spj).

H.1: XML Project File Example

========================= <!DOCTYPE SilvacoProject> <project version="1" name="vend_tb" > <products> <product name="SILOS" > <settings> <setting value="No" name="DebugEnable" /> <setting value="N" name="UseCommonDir" /> <setting value="silos_010" name="OpenFileDir" /> <setting value="Silvaco4.10.96.A" name="Version" /> <setting value="Yes" name="LogFile" /> </settings> <analyzer> <settings> <setting value="121" name="C0Width" /> <setting value="127" name="C1Width" /> <setting value="20" name="C2Width" /> <setting value="N" name="ShowYaxis" /> </settings> <views> <view value="0.000us 1.460us 0.067us 0.000us 0.000us" name="Last" /> </views> <groups> <group open="no" name="Default" show="yes" > <signals> <signal name="clock" scope="vend_tb.XvendY" /> <signal name="reset" scope="vend_tb.XvendY" /> <signal radix="Binary" name="coin[1:0]" scope="vend_tb.XvendY" /> <signal name="newspaper" scope="vend_tb.XvendY" /> </signals> </group> </groups> </analyzer> <sourcefiles> <sourcefile name="vend_tb.v" /> </sourcefiles> <libraryfiles> <libraryfile name="abc_100.v" /> </libraryfiles> </product> Silvaco, Inc. H-1

Silos Users Manual </products> </project>

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Index
Symbols
`timescale ...................................................................... E-14 $resetstartsave system task ............................................... E-10 $stopsave system task ...................................................... E-10 $timeformat .................................................................... E-14 Code Coverage ................................................................3-59 Line Coverage Reports ...................................................3-59 Merging Code Coverage Reports ......................................3-65 Operator Coverage Reports .............................................3-62 Code Coverage Line Report ................................................4-77 Code Coverage Operator Report ..........................................4-78 Collapse All Analog Signals .................................................4-23 Command Line Arguments ..................................................4-47 command line option -"!delay .default =1,1" ...................................................... B-2 -"!system" ..................................................................... B-1 +alt_return_value ........................................................... B-2 +define+text_macro_name=macro_text ............................... B-2 +delay_mode_distributed ................................................. B-3 +delay_mode_path ......................................................... B-3 +delay_mode_unit .......................................................... B-3 +delay_mode_zero ......................................................... B-3 +ghdl_format ................................................................. B-3 +ignore_sdf_interconnect_delay ........................................ B-3 +ignore_sdf_port_delay ................................................... B-3 +incdir+directory1+directory2 ............................................ B-3 +libcodecoverage ........................................................... B-3 +linecov ....................................................................... B-3 +maxdelays .................................................................. B-3 +memsave .................................................................... B-4 +mindelays ................................................................... B-4 +neg_tchk ..................................................................... B-4 +no_default_variables ..................................................... B-4 +no_notifier ................................................................... B-4 +no_pulse_msg ............................................................. B-4 +no_sdf_zero_delay_msg ................................................ B-4 +no_tchk_msg ............................................................... B-5 +nodoldisplay ................................................................ B-4 +nolibfaults ................................................................... B-4 +notimingchecks ............................................................ B-5 +nowarntfmpc ................................................................ B-5 +oprcov ........................................................................ B-5 +plusargs ..................................................................... B-5 +protect ....................................................................... B-6 +pulse_quiet ................................................................. B-6 +pulse_r/ and +pulse_e/ ................................................... B-6 +rawd .......................................................................... B-6 +save_data_interval+n .................................................... B-7 +suppressfloat ............................................................... B-7 +suppressredef .............................................................. B-7 +timing_checks .............................................................. B-7 +transport_int_delays ...................................................... B-7 +typdelays .................................................................... B-7 +width_mismatches ........................................................ B-7 +xl_order ...................................................................... B-7 -b ................................................................................ B-1 -c ................................................................................ B-1 -converttoxml ................................................................. B-1 -f ................................................................................ B-1 -k ................................................................................ B-1 -l ................................................................................. B-1 -la ............................................................................... B-1

A
About Silos ......................................................................4-80 Add One Bit ...................................................................4-23 Add Zero Bit ..................................................................4-23 Add Bookmark .................................................................4-26 Add Signals .....................................................................4-16 Add Signals to Analyzer Menu Selection ................................4-16 Alternate behavioral evaluation order ....................................4-46 Analog Behavior Modeling Analog Extensions .......................................................... E-8 Tutorial example .............................................................3-1 Analog Display Options ......................................................4-23 Analog Overlay Expanding ...................................................................3-39 Analog Overlays ...............................................................3-39 Analog Signal Scale ..........................................................4-50 Analog Signals as a Digital Bus ............................................3-46 Analog Signals as Digital Signals ..........................................3-45 Analog to Digital Conversion Threshold ..................................4-50 Analog Waveforms ............................................................3-34 Analyzer Settings ..............................................................4-50 Analyzer symbol table file ...................................................4-47 Annotated Timeline ...........................................................3-19 Auto text file save .............................................................4-46

B
Behavioral Stimulus ............................................................ E-7 Behavioral Traceback ........................................................3-49 BNF ................................................................................ E-1 Bookmark .......................................................................3-29 Breakpoints .....................................................................3-57 bus ................................................................................3-23 BUSCON command .........................................................6-8 creating in Data Analyzer ................................................3-23 Bus Contention ...................................................................6-8 Buses ...................................................................3-21, 3-23

C
ccexport command ..............................................................6-9 ccmexclude command .......................................................6-10 ccmkeep command ...........................................................6-11 celldefine ........................................................................6-14 Clear Signal List ...............................................................4-24

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-r ................................................................................ B-2 -s ................................................................................ B-2 -u ................................................................................ B-2 -v ................................................................................ B-2 -w ............................................................................... B-2 -y ................................................................................ B-2 common logarithm .............................................................. E-9 Continuous Assignments ................................................... E-11 Control Parameters ...........................................................6-13 .COMMENT .................................................................6-13 .CUSTREPORT ............................................................6-13 .DISABLECACHE ..........................................................6-13 .DISK ..........................................................................6-13 .DMAX ........................................................................6-13 .DMIN .........................................................................6-13 .ENABLECACHE ...........................................................6-13 .EUNK ........................................................................6-13 .MXDCI .......................................................................6-13 .MXITR .......................................................................6-13 .MXRECUR ..................................................................6-14 .NONCON ...................................................................6-13 .RECIRCULATE ............................................................6-14 .SAVCELL ...................................................................6-14 .SAVSIM .....................................................................6-14 .SKIP ..........................................................................6-14 .SYNONYM ..................................................................6-14 .TPS ...........................................................................6-14 XL_ORDER .................................................................6-14 Copy Scope .....................................................................4-12 cosine function .................................................................. E-9 Creating Groups ...............................................................3-22 Current Module .................................................................4-30

E
Enable Code Coverage ..................................................... 4-76 Enable code coverage for library modules .............................. 4-46 Enable log file ................................................................. 4-46 Enable Single Step ........................................................... 4-70 Enable trace source .......................................................... 4-46 encryption ........................................................................ B-6 error Tutorial example ........................................................... 3-70 Error Reporting ................................................................ 3-70 Error Summary ................................................................ 6-17 errors ............................................................................ 6-17 Errors and Warnings ......................................................... 4-73 Example Projects ...............................................................C-1 EXCLUDE ...................................................................... 6-19 Exclude Saving Simulation Node States ................................ 6-17 exit ............................................................................... 6-18 Exiting ............................................................................. 2-7 Expand All Analog Signals ................................................. 4-23 Expanding Analog Waveforms ............................................ 3-34 Expected Value ................................................................. E-5 Expected Values ................................................................ E-1 expected values ................................................................. E-6 Explorer Add Signals ................................................................. 4-15 Explorer window ............................................................. 3-8 Go to Definition ............................................................ 4-15 exponential function ............................................................ E-9 Export Code Coverage Data ............................................... 4-77 extensions ...................................................................... E-11 save file size ................................................................ E-10 Verilog HDL ................................................................. E-11

D
Data Analyzer expressions ..................................................................4-23 Goto Timepoint .............................................................4-25 Time Scale dialog box ....................................................4-26 Data Tip Radix ....................................................... 4-29, 4-70 Data Tips .............................................................. 3-30, 4-29 Default Device Delay Times ................................................6-16 Delay selection .................................................................4-46 Delay Time ....................................................................... E-2 Delete Bookmark ..............................................................4-26 Delete Group ...................................................................4-22 Delete Item/s ....................................................................4-24 Disable floating node warnings .............................................4-46 DISK command ................................................................6-16 Disk File Name Reassignment .............................................6-16 Display as Digital ..............................................................4-23 Display Group as Analog Overlay .........................................4-22 Display Group as Digital Bus ...............................................4-22 Display Type ....................................................................3-36 Do Not Display Group ........................................................4-22 Downscope to ..................................................................................4-30

F
fault simulation .................................................................. 6-1 File Extensions ..................................................................D-1 File Name Specification ..................................................... 6-18 Finish Current Timepoint .................................................... 4-69 Fixed Scale ..................................................................... 3-41 Frequently Asked Questions (FAQ) ........................................ A-1 Functional simulation ........................................................ 4-46

G
gate MOS .......................................................................... 6-15 Gate Level Debugging ....................................................... 3-68 Global Variables .............................................................. E-11 Go to ................................................................................................4-12 Go to Definition ....................................................... 4-16, 4-30 Goto Definition ................................................................. 4-21 Goto Timepoint ....................................................... 3-29, 4-25

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Index

Graphical User Interface .......................................................4-1 Groups ...........................................................................3-21

H
hyperbolic cosine function .................................................... E-9 hyperbolic sine function ....................................................... E-9 hyperbolic tangent function .................................................. E-9

Merge Code Coverage .......................................................4-77 MEXCLUDE .......................................................... 6-19, 6-20 MKEEP ..........................................................................6-20 Move Item Down ..................................................... 3-22, 4-24 Move Item Up ........................................................ 3-22, 4-24

N
Name Filter ......................................................................4-17 Narrow Storing .................................................................6-22 natural logarithm function ..................................................... E-9 New Group ............................................................ 3-22, 4-22 No Convergence ...............................................................6-21 NOCONV ........................................................................6-21 Non-Constant Specify ....................................................... E-12 Nonconvergence ...............................................................4-74 Nonconvergence (Hanging) for Behavioral Designs ..................4-75 Nonconvergence For Gate Designs .......................................4-74 Non-Standard Extensions .................................................. E-11 Non-Standard Verilog HDL Extensions .......................... 4-46, E-1 NSTORE .........................................................................6-22 Null Statements ............................................................... E-14

I
I/O Pad ............................................................................ E-4 implicit nodes ...................................................................6-23 Inactivity .........................................................................4-72 Include Directories ............................................................4-44 Incremental Update ............................................................ E-6 Insert Group ....................................................................3-22 Insert/Remove Breakpoint ..........................................4-29, 4-71 Instance Name Filter .........................................................4-12 Integer ............................................................................ E-8 Interactive Commands .........................................................6-1 Intra-assignment/non-blocking Delays .................................. E-11 inverse cosine function ........................................................ E-9 inverse sine function ........................................................... E-9 inverse tangent function ...................................................... E-9 Iteration ..........................................................................4-73

O
On-line Help ......................................................................2-7 Other Settings ..................................................................4-46 Other Simulators ...............................................................5-10 Output Window ...................................................................3-6

K
KEEP .............................................................................6-17 KEEP command ...............................................................6-17 Keeping Simulation Node States ..........................................6-19

P
Pan Last ............................................................... 4-26, 4-67 Pan T1 ................................................................. 4-26, 4-67 Pan T2 ................................................................. 4-26, 4-67 Parameter for Specify ....................................................... E-13 Platforms Supported ............................................................1-1 PLI Library Files ................................................................4-45 PLI on Windows ..................................................................5-1 PlusArgs .........................................................................4-48 PlusDefines .....................................................................4-49 power function ................................................................... E-9 PREPROC ......................................................................6-23 Preprocessing Data ...........................................................6-23 Print Analyzer ..................................................................4-38 Print Menu .......................................................................4-38 Probing Node States ..........................................................6-23 Procedural Assignment ..................................................... E-11 Programming Language Interface (PLI) ....................................5-1 Project Properties .............................................................4-40 Properties .......................................................................4-13 PWL ..............................................................................3-36

L
Library Directories .............................................................4-43 Library Files .....................................................................4-42 Load/Reload Input Files ......................................................4-69 Logic Condition ................................................................3-25 logic initialization ...............................................................6-21 Logic simulation ................................................................6-26 control ........................................................................6-13 delay ..........................................................................6-13 iteration limit .................................................................6-13 save file ......................................................................6-25 XL_ORDER .................................................................6-14

M
math functions .................................................................. E-9 Mathematical Operations ....................................................3-44 MAXWRN .......................................................................6-19 memory size ............................................................................6-27 stimulustable ................................................................. E-3 Memory Utilization ............................................................. E-3

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Q
Quitting ...........................................................................6-24

R
Radix .............................................................................. E-2 Data Analyzer ...............................................................4-22 Radix menu .....................................................................4-22 Real ................................................................................ E-8 Recirculation ......................................................................5-7 Regular Expressions ..........................................................4-17 Reload and Go .................................................................4-70 Reports ...........................................................................4-71 reports narrow store to disk ........................................................6-22 no convergence ............................................................6-13 size information .............................................................6-27 spike ..........................................................................6-27 RESET ...........................................................................6-25 errors ..........................................................................6-25 everything ....................................................................6-25 Resetting Selected Data .....................................................6-25 Resize the Name list box ....................................................3-11 Restricting Code Coverage Analysis ......................................4-79 Reverse Bit Order .............................................................4-24

S
save .............................................................................. E-10 simulation results ...........................................................6-25 save file size ......................................................................5-6 Saving of Simulation Data .................................................. E-10 Reset ......................................................................... E-10 Turn-off ...................................................................... E-10 Turn-on ...................................................................... E-10 scanning to edge ..............................................................3-26 Scan-to-Change ...............................................................3-26 Scan-to-Value ..................................................................3-26 SCOPE ...........................................................................6-25 Select Scope .......................................................... 4-12, 4-30 Show Groups ...................................................................3-22 Signal Color .....................................................................4-23 Signal Groups ..................................................................4-21 Signals ...........................................................................3-21 Silos Explorer Window .........................................................3-8 Silos Help ........................................................................4-80 silos keyword .................................................................. E-10 SIMULATE ......................................................................6-26 Simulation Data File ..........................................................4-47 sine function ..................................................................... E-9 Single Stepping ................................................................3-53 SIZE ..............................................................................6-27 Size-Of-Data ....................................................................6-27 Sizes ..............................................................................4-76

Sizing Numbers ............................................................... E-14 Smaller Save Files ............................................................. 5-6 Sort by Name .................................................................. 4-18 Source Files .................................................................... 4-41 specify blocks .................................................................... B-2 eliminating the specify block .............................................. B-2 Spike Summary ............................................................... 6-27 SPIKES ......................................................................... 6-27 square root function ............................................................ E-9 Standard Delay Format (SDF) ............................................... 5-3 Status Bar ...................................................................... 4-31 Step .............................................................................. 3-36 stimulus ........................................................................... E-8 converting behavioral to tabular ......................................... E-8 tabular ......................................................................... E-8 Stimulustable .................................................................... E-1 stimulustable ............................................................. E-4, E-7 I/O pad ......................................................................... E-4 Stimulustable Extension ..................................................... E-13 stop an interactive process ................................................... 6-1 STOP button ..................................................................... 4-2 Stopping Processes ............................................................ 6-1 STORE ................................................................... 6-1, 6-28 Storing Outputs ................................................................ 6-28 STRENGTH .................................................................... 6-29 Strength Specification ....................................................... 6-29 Strobe ............................................................................. E-3 SYMBOL ........................................................................ 6-30 Symbol Modification .......................................................... 6-30 Symbolic Names .............................................................. 3-16

T
tabular probe command ........................................................... 6-23 tangent function ................................................................. E-9 Technical Support .............................................................. 1-2 test pattern activity report ..................................................... 6-2 Time Scale dialog box ....................................................... 3-30 Timescale .............................................................. 3-29, 4-26 timing check ...................................................................... B-5 Timing Markers ................................................................ 3-25 Title Tips ........................................................................ 3-11 Toggle ........................................................................... 4-72 Toolbar zoom buttons ............................................................... 3-28 Trace Inputs ........................................................... 3-68, 4-21 Trace Source ......................................................... 3-47, 4-67 Transcendental Functions .................................................... E-9 Transcendental Math Functions ............................................. E-9

U
UDP .................................................................... E-11, E-12

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Index

default value ............................................................... E-11 High-Z ....................................................................... E-12 Unset state symbol ............................................................6-31 Upscope to .......................................................................................4-30

V
Value Change Dump (VCD) ..................................................5-5 Variable ..........................................................................3-41 VCS Compatibility ............................................................ E-14 Vector Expanding and Collapsing ...............................................3-15 Vectors ...........................................................................3-21 Verilog HDL extensions ....................................................... E-8 analog ......................................................................... E-8 View Breakpoints ..............................................................4-70 Visual Debug ...................................................................3-49

W
warning +suppressfloat ............................................................... B-7 +suppressredef .............................................................. B-7 Warning Message Limit ......................................................6-19 Warning message limit .......................................................4-46 Waveform Colors ..............................................................3-14

X
X-Axis Area .....................................................................4-25

Y
Y- Axis ...........................................................................3-41

Z
Zoom .............................................................................3-28 Zoom Markers ..................................................................4-67

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