What are FPGAs?

FPGAs are programmable digital logic chips. What that means is that you can program them to
do almost any digital function.

Here's the general workflow when working with FPGAs:

 You use a computer to describe a "logic function" that you want. You might draw a
schematic, or create a text file describing the function, doesn't matter.
 You compile the "logic function" on your computer, using a software provided by the
FPGA vendor. That creates a binary file that can be downloaded into the FPGA.
 You connect a cable from your computer to the FPGA, and download the binary file to
the FPGA.
 That's it! Your FPGA behaves according to your "logic function".

Keep in mind that

 You can download FPGAs as many time as you want - no limit - with different
functionalities every time if you want. If you make a mistake in your design, just fix your
"logic function", re-compile and re-download it. No PCB, solder or component to change.
 The designs can run much faster than if you were to design a board with discrete
components, since everything runs within the FPGA, on its silicon die.
 FPGAs loose their functionality when the power goes away (like RAM in a computer that
looses its content). You have to re-download them when power goes back up to restore
the functionality.

Who makes FPGAs?

There are (at least) 5 companies making FPGAs in the world. The first two (Xilinx and Altera)
hold the bulk of the market.

 Xilinx invented the FPGA and is the biggest name in the FPGA world. It tends to be the
density and technology leader.
 Altera is the second FPGA heavyweight, also a well-known name.
 Lattice, Actel, Quicklogic and SiliconBlue are smaller players.

Xilinx

Xilinx has traditionally been the silicon technology leader. Xilinx general philosophy is to
provide all the features possible, at the cost of extra complexity.

 Biggest and most flexible (feature-full) devices.

  Complex architecture, powerful devices.

Altera

Altera philosophy is to provide the features that most people want while keeping their devices
easy to use.

 Lean and efficient devices architecture.

 Powerful devices.

FPGAs vs. CPLDs

Are FPGAs and CPLDs the same thing? No

Both are programmable digital logic chips and are made by the same companies. But they have
different characteristics.

 FPGAs are "fine-grain" devices - that means that they contain a lot (up to 100000) of tiny
blocks of logic with flip-flops. CPLDs are "coarse-grain" devices - they contain relatively
few (a few 100's max) large blocks of logic with flip-flops.
 FPGAs are RAM based - they need to be "downloaded" (configured) at each power-up.
CPLDs are EEPROM based - they are active at power-up (i.e. as long as they've been
programmed at least once...).
 CPLDs have a faster input-to-output timings than FPGAs (because of their coarse-grain
architecture), so are better suited for microprocessor decoding logic for example than
FPGAs.
 FPGAs have special routing resources to implement efficiently arithmetic functions
(binary counters, adders, comparators...). CPLDs do not.

In general, FPGAs can contain large digital designs, while CPLDs can contain small designs
only.

FPGAs vs. microcontrollers

Are FPGAs and microcontrollers the same thing? No

 FPGAs implement programmable logic elements running in a parallel fashion.

 Microcontrollers are based on a CPU architecture (executes a set of instructions in a
sequential manner).

Microcontrollers have on-chip peripherals that also execute in parallel with their CPU. But they
are still much less configurable than FPGAs.
How FPGAs work

Logic-cells

FPGAs are built from one basic "logic-cell", duplicated hundreds or thousands of time. A logic-
cell is basically a small lookup table ("LUT"), a D-flipflop and a 2-to-1 mux (to bypass the
flipflop if desired).

The LUT is like a small RAM and has typically 4 inputs, so can implement any logic gate with
up to 4-inputs. For example an AND gate with 3 inputs, whose result is then OR-ed with another
input would fit in one LUT.

Interconnect

Each logic-cell can be connected to other logic-cells through interconnect resources

(wires/muxes placed around the logic-cells). Each cell can do little, but with lots of them
connected together, complex logic functions can be created.

IO-cells

The interconnect wires also go to the boundary of the device where I/O cells are implemented
and connected to the pins of the FPGAs.
Dedicated routing/carry chains

In addition to general-purpose interconnect resources, FPGAs have fast dedicated lines in

between neighboring logic cells. The most common type of fast dedicated lines are "carry
chains". Carry chains allow creating arithmetic functions (like counters and adders) efficiently
(low logic usage & high operating speed).

Older programmable technologies (PAL/CPLD) don't have carry chains and so are quickly
limited when arithmetic operations are required.

Internal RAM

In addition to logic, all new FPGAs have dedicated blocks of static RAM distributed among and
controlled by the logic elements.
Internal RAM operation

There are many parameters affecting RAM operation. The main parameter is the number of
agents that can access the RAM simultaneously.

 "single-port" RAMs: only one agent can read/write the RAM.

 "dual-port" or "quad-port" RAMs: 2 or 4 agents can read/write. Great to get data across
clock domains (each agent can use a different clock).

Here's a simplified drawing of a dual-port RAM.

To figure out how many agents are available, count the number of separate address buses going
to the RAM. Each agent has a dedicated address bus. Each agent has also a read and a write data
bus.

Writing to the RAM is usually done synchronously. Reading is usually done synchronously but
can sometimes be done asynchronously.

Blockram vs. Distributed RAM

Now there are two types of internal RAMs in an FPGA: blockrams and distributed RAMs. The
size of the RAM needed usually determines which type is used.
  The big RAM blocks are blockrams, which are dedicated areas in the FPGA. Each FPGA
has a limited number of these, and if you don't use them, you loose them (they cannot be
used for anything but RAM).
 The small RAM blocks are either in smaller blockrams (Altera does that), or in
"distributed RAM" (Xilinx does that). Distributed RAM allows using the FPGA logic-
cells as tiny RAMs which provide a very flexible RAM distribution in an FPGA, but isn't
efficient in term of area (a logic-cell can actually hold very little RAM). Altera prefers
building different size blockrams around the device (more area efficient, but less
flexible). Which one is better for you depends on your FPGA application.

FPGA pins

FPGAs tend to have lots of pins...

Dedicated and user pins

FPGA pins fall into 2 categories: "dedicated pins" and "user pins".

About 20% to 30% of the pins of an FPGA are "dedicated pins", which means that they are hard-
coded to a specific function.
The dedicated pins fall into the 3 following sub-categories.

 Power pins: ground and core/IO power pins.

 Configuration pins: used to "download" the FPGA.
 Dedicated inputs, or clock pins: these are able to drive large nets inside the FPGA,
suitable for clocks or signals with large fan-outs.

The rest are user pins (called "IOs", or "I/Os", or "user I/Os", or "user IOs", or "IO pins", or ...
you get the idea). IO stands for "input-output".

 You usually have total control over user IOs. They can be programmed to be inputs,
outputs, or bi-directional (tri-statable buffers).
 Each "IO pin" is connected to an "IO cell" inside the FPGA. The "IO cells" are powered
by the VCCIO pins (IO power pins).

An FPGA has many VCCIO pins, usually all connected to the same voltage. But new
generations of FPGAs have a concept of "user IO banks". The IOs are split into groups, each
having its own VCCIO voltage. That allows using the FPGA as a voltage translator device,
useful for example if one part of your board works with 3.3V logic, and another with 2.5V.

FPGA power

FPGAs usually require two voltages to operate: a "core voltage" and an "IO voltage". Each
voltage is provided through separate power pins.

 The internal core voltage (called VCCINT here) is fixed (set by the model of FPGA that
you are using). It is used to power the logic gates and flipflops inside the FPGA. The
 voltage was 5V for older FPGA generations, and is coming down as new generations
come (3.3V, 2.5V, 1.8V, 1.5V, 1.2V and even lower for the latest devices).
 The IO voltage (called VCCIO here) is used to power the I/O blocks (= pins) of the
FPGA. That voltage should match what the other devices connected to the FPGA expect.

The internal voltage is named "VCC" for Xilinx and "VCCINT" for Altera.
The IO voltage is named "VCCO" for Xilinx and "VCCIO" for Altera.

Clocks and Global lines

An FPGA design is usually "synchronous". Simply put, that means that the design is clock based
- each clock rising edge allows the D-flipflops to take a new state.

In a synchronous design, a single clock may drive a lot of flipflops simultaneously. That can
cause timing and electrical problems inside the FPGA. To get that working properly, FPGA
manufacturers provide special internal wires called "global routing" or "global lines". They allow
distributing the clock signal all over the FPGA with a low skew (i.e. the clock signal appears
almost simultaneously to all the flipflops).

When you feed a clock signal to your FPGA, you shouldn't use any FPGA pin, but use a
dedicated input clock pin. Usually, only such pin has the ability to drive a global line. FPGA
software are aware of these dedicated input pins, and will automatically assign clocks to them if
given the choice.

Clock domains

An FPGA can use multiple clocks (using multiple global lines and dedicated input pins). Each
clock forms a "clock domain" inside the FPGA.

Flipflops and combinatorial logic in each clock domain

For each flipflop inside the FPGA, its clock domain is easy to determine. Just look at the flipflop
clock input.
But what about the combinatorial logic that sits in between flipflops?

 If there is some combinatorial logic in between "same clock domain" flipflops, the logic
is said to be part of the clock domain too.
 If there is some combinatorial logic in between "different clock domains" flipflops, the
logic is not owned by any clock domain. But in a typical FPGA design, there is no such
logic; the only paths from different clock domains are synchronizers.

Clock domain speeds

For each clock domain, the FPGA software will analyze all flop-to-flop paths and give you a
report with the maximum allowed frequencies. In the general case, only the paths from within
each clock domains are analyzed. The synchronizer paths (from different clock domains) usually
don't matter and are not analyzed.
One clock domain may work at 10MHz, while another may work at 100MHz. As long as each
clock uses a global line, and you use clock speeds that are lower than the maximums reported by
the software, you don't have to worry about internal timing issues, the design is guaranteed to
work internally timing-wise.

There may still be some timing issues from the FPGA input and output pins though. The
software will give you a report about that. See also the next section.

Signals between clock domains

If you need to send some information across different clock domains, special considerations need
to apply.

In the general case, if your clocks have no relationship with one another, you cannot use a signal
generated from one clock domain into another as-is. Doing so would violate setup and hold
flipflop timings (in the destination clock domain), and cause metastability.

Crossing clock domains requires special techniques, like the use of synchronizers (that's simple),
or FIFOs (that's more complicated). See the fpga4fun's Crossing clock domains project to get
some practical ideas, or these external links here, here and here

FPGA download cables

FPGA vendors provide many ways to "configure" (i.e. download) their devices. One way is
using a cable that connects from your PC to the FPGA board. The most popular cables connect to
your PC's parallel or USB interface.

These cables are sometimes called "JTAG cables" (because they often connect to the JTAG pins
of an FPGA).

FPGA cables are vendor specific

The FPGA configuration interface from all the FPGA vendors are very much alike. That doesn't
prevent each vendor to have their own proprietary connectors and cables.

 The complete list of Altera cables can be found here.

o The most popular one is the USB-Blaster.
o Altera parallel cable are the ByteBlasterMV and ByteBlaster II.

 The complete list of Xilinx cables can be found here.

o The most popular one is the Platform Cable USB (and its PDF).
o Xilinx parallel cable is called Parallel cable III. See also the cables Hardware user
guide and the Parallel Cables page.
About parallel cables: a parallel cable connects to your PC's parallel (printer) port. It buffers a
few pins of the PC parallel interface, and connects to the target board using a flat cable or flying
leads. The parallel cable is an active device and needs power. It is usually powered from the
target FPGA board. FPGA vendors sometimes provide the schematic of the cable, which is
valuable if you want to build a cable yourself.

FPGA configuration

An FPGA can be into 2 states: "configuration mode" or "user mode". When the FPGA wakes up
after power-up, it is in configuration mode, sitting idle with all its outputs inactive. You need to
configure it.

Configuring an FPGA means downloading a stream of 0's and 1's into it through some special
pins. Once the FPGA is configured, it goes into "user-mode" and becomes active, performing
accordingly to your programmed "logic function".

There are 3 classical ways to configure your FPGA:

 You use a cable from your PC to the FPGA, and run a software on your PC to send data
through the cable.
 You use a microcontroller on your board, with an adequate firmware to send data to the
FPGA.
 You use a "boot-PROM" on your board, connected to the FPGA, that configures the
FPGA automatically at power-up (FPGA vendors have such special boot-PROMs in their
catalogs)

During development, the first method is the easiest and quickest. Once your FPGA design works,
you probably don't need the PC anymore, so the other 2 methods come in use.

FPGA configuration can quickly become a complex subject, so you might want to skip this
section, especially if you intend to use an already-made FPGA development board. Development
boards usually come with a special cable that you can use to configure the FPGA from your PC
with no knowledge of the underlying interface.
But if you want to learn a little more, read-on.

FPGA configuration of Xilinx and Altera devices

Configuration works in a surprisingly identical way between Xilinx and Altera devices. The
differences is mostly in the naming (pin names and modes of operation are named differently),
but the functionality provided is similar.

FPGAs provide 2 interfaces that can be used for configuration:

 The JTAG interface.

 The "synchronous serial" interface.
The JTAG interface (or JTAG "port")

JTAG was originally designed for test and manufacturing purposes. As electronic boards became
more and more compact, testing that a board was "good" became more and more difficult.

JTAG primary purpose is to allow a computer to take control of the state of all the IO pins on a
board. In turn, this allows each device connectivity to other devices on the board to be tested.
Standard JTAG commands can be used for this purpose.

FPGAs are JTAG-aware and so all the FPGA IO pins can be controlled from the JTAG interface.
FPGAs add the ability to be configured through JTAG (using proprietary JTAG commands).

How JTAG works

JTAG consists of 4 signals: TDI, TDO, TMS and TCK.

A fifth pin, TRST, is optional.

A single JTAG port can connect to one or multiple devices (as long as they are all JTAG-aware
parts). With multiple devices, you create what is called a "JTAG chain". The TMS and TCK are
tied to all the devices directly, but the TDI and TDO form a chain: TDO from one device goes to
TDI of the next one in the chain. The master controlling the chain (a computer usually) closes the
chain.

TCK is the clock, TMS is used to send commands to the devices, and TDI/TDO are used to send
and receive data. Each device in the chain has an ID, so the computer controlling the JTAG chain
can figure out which devices are present.

For more info, check the JTAG project.

The "synchronous serial" interface

It is a simple one-bit data/clock interface. It is synchronous and you provide one bit at a time to
the device.

Here's a description of the 5 most important pins of this interface:

Xilinx
Altera pin
pin Direction Pin function
name
name
input to the
data data0 configuration data bit
FPGA
input to the configuration clock, the configuration data bit is shifted in the
clk dclk
FPGA FPGA at the clock rising-edge
input to the when asserted (i.e. when it goes low - this is an active low
prog_b nConfig
FPGA pin), the FPGA is reset-ed and looses its configuration. If the
 FPGA was in user-mode, it stops operation immediately, and
all IOs go back into tri-state mode.
This pin indicates when the FPGA is ready to start the
configuration process, soon after prog_b is de-asserted. It is
output from useful in combination with prob_b because it takes a few
init_b nStatus
the FPGA milliseconds for the FPGA is get into a "clean state of mind",
once prog_b is de-asserted, after which pumping
configuration data can actually start.
output from When high, indicates that the FPGA is configured (in user-
done ConfDone
the FPGA mode).

Note: the init_b and done pins are actually open-collector pins, so pull-up resistors are required
on these. Also if multiple FPGAs are to be configured, these pins are usually connected together
on all FPGAs, so that all the FPGAs switch into "user-mode" together. There is many more
details, so for a complete description, check the FPGA vendors application notes.

Learn more

If all that didn't discourage you, the next step would be to read some FPGA datasheets.

Good candidates are (in order of complexity):

 The Altera ACEX family datasheet (1.2MB), or the Cyclone family.

 The Xilinx Spartan-II family datasheet (0.8MB), or the Spartan-3 family.

After that, get dirty, buy an FPGA development board and build something!