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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 41, NO. 5.

MAY 1994

405

Transactions Briefs
Temperature Stable Voltage Controlled Current Source
J. Choma Jr., Fellow, IEEE
Abstract- T h i s paper proposes a complementary bipolar junction transistor circuit that supplies a nominally temperature invariant output current whose value is linearly related to a user defined static control voltage. The circuit developed herein is a true current source, as opposed to a current sink. It effectively functions as a static transconductor in that the controlling voltage is not Limited to small signals, very little current is conducted by the controlling port, and very high static output resistance characterizes the controlled port. Moreover, the effective inputto-output transconductanceis virtually independent of the absolute values of transistor parameters. Instead, its value is determined by a designable circuit resistance.

vK

I. INTRODUCTION Voltage controlled static current sources appear in a variety of monolithic electronic circuit applications. The most notable of these applications is the vehicle for implementing voltage controlled manual or automatic gain control in radio and intermediate frequency amplifiers embedded in communication chips [ l ] - [6]. Other examples of the utility of controlled static current sources include the frequency select mechanism in relaxation oscillators and multivibrators [7], current sinking in charge and current scaling digital-to-analog converters [8], and parametric tuning of integrated filters [9]. In these and related requirements, the utilized voltage controlled static current source (VCSCS) must supply a current that is nominally independent of operating temperature. Moreover, the value of the controlled output current must be a predictable and generally linear function of an applied control voltage. The design of a VCSCS in bipolar technology must circumvent three fundamental shortcomings. The first of these is the temperature dependence of the saturation current, I S , of a bipolar junction transistor. Typically, this device parameter doubles-to-quintuples its room temperature value for each 10C rise in junction operating temperature. The circuit level impact of the temperature sensitivity of IS is a negative temperature coefficient ascribed to the voltage that forward biases the intemal base-emitter junction of the considered transistor. Unfortunately, the precise value of the temperature coefficient of the corresponding base-emitter terminal voltage is obscured by monolithic processing uncertainties, as well as by ill defined and poorly controlled second-order parametric phenomena. A significant problem in complementary bipolar processes is the fact that the temperature coefficient of the forward biasing voltage applied to the base-emitter terminals of an NPN transistor is not well matched to that of the voltage that forward biases the emitter-base terminals of its PNP complement. A second shortcoming is an uncertainty in the static ratio, FE, of transistor collector current-to-base current. Although FE 's among Manuscript received June 14, 1993; revised December 20, 1993. This work was supported by the Radar Systems Group of GM-HughesAircraft Company, El Segundo, CA, under Purchase Order No. SR-526682-SCT.This paper was recommended by Associate Editor David Haigh. J. Choma Jr. is with the University of Southem Califomia, Department of Electrical Engineering-Electrophysics University Park, MC: 027 1, Los Angeles, CA 90089-0271 USA. IEEE Log Number 9401186.

Fig. 1. The circuit diagram of a commonly used voltage controlled static current source (VCSCS). like transistors on a monolithic chip are well matched, the uncertainty in the absolute value of FE from chip-to-chip can be as much as &300%. Additionally, h FE has a temperature dependence that increases its room temperature value by 3%'-to-7% for every 10C rise in junction temperature. As is the case with the temperature coefficient of the base-emitter voltage, the precise value of the thermal coefficient of FE is not a predictable function of processing and device model parameters. The matchability afforded among homologous device parameters in a monolithic fabrication process is typically exploited to offset the foregoing electrical shortcomings. But when parametric matchability is an implicit design tool, several fundamental design issues must be considered. The first of these is the fact that the temperature coefficients of the forward biasing voltages applied across the baseemitter terminals of two matched transistors are nominally identical only if the densities of collector currents flowing through the two subject transistors are the same. A second design-oriented issue is that despite similar processing characteristics and identical cross section and surface feature sizes, an NPN bipolar junction transistor and its PNP counterpart do not share matched electrical and thermal properties. This fact implies an inequality between the temperature coefficients of their respective forward biasing base-emitter voltages, even if identical current densities prevail in the two devices. It also suggests that the temperature coefficient of the current gain parameter, FE, as well as the value of hFE: itself, differs between the two transistor types. Indeed, FE in a PNP device is normally 15%-to-40% smaller than is h F E in a counterpart NPN transistor. 11. BASICCIRCUIT CONFIGURATION The circuit diagram of a commonly used voltage controlled static current source (VCSCS) is offered in Fig. (1) [lo]. Its operation is easily understood by assuming that the NPN and the PNP devices

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have very large collector current-to-base current transfer ratios, FEN and ~ F E P ,respectively, and identical forward biasing base-emitter terminal voltages; that is VBEN VEBP.As a result, the current, I R , conducted by the resistance, R , is the current sum, ( I K IO), and the applied voltage, VK, is

VK = R(IK + I o ) It follows that

+ VEBP - VBEN= R ( I K + I o ) .

(1)

(2) R To the extent that IK is invariant with device parameters and I K and R are independent of temperature, IO is a constant current that is linearly dependent on the voltage, VK. But (2) is only a first-order approximation of the output current, since, as underscored earlier, VEBP for the PNP device is not identical to VBEN for the NPN transistor. Nor do these two terminal voltages track one another well over wide variations in operating temperature. Additionally, the tacit assumption of infinitely large static current transfer ratio is questionable for the PNP unit. A more thorough analysis of the circuit in Fig. 1 reveals that the current, I R , is hFEN 1 Io IR = ( G x ) I K (hFEP hFEp ( 3 )
+ +

V K Io = -IK.

v~~~

h )

where FEN is the static current transfer ratio of the NPN transistor, QNI, and h ~ is~ the p corresponding gain parameter of the PNP device, QPl. Since VK = RIR

I1

( 3 ) yields,

with ( ~ F E N / ~ F E N 11,

Io=

(5) An inspection of (5) suggests that the output current, IO, is virtually independent of transistor gain parameters if Q F E P ~ F E N>> 1. This requirement, which does not mandate h ~ >> ~ 1, p implies that QFEN % 1, and accordingly, VK VBEN- VEBP I o Fz - IK. (6) R If the constant current, I K , is rendered in the form, VBEN- VEBP IK = +IKO (7)

+ [ 1+

+ VEBP- VBEN QFEPa(hFEP/hFEP + 1 )


FEN

(4)
and
QFENa

QFEP

-%I324 Fig. 2. The circuit proposed to generate the current, I K , required in the VCSCS of Fig. 1.
If R I = 2Rz and if

(1 1) reduces to

IK M

QFEN ( 7 )

+ VEEl + 2(VEE1 - VEE2) + VBEN - VEBP


REE which has the algebraic form of (7). The resultant generalized circuit schematic diagram of the proposed thermally compensated VCSCS is given in Fig. 3. In this schematic diagram, let R1 = 2R2, and select the resistance, REE. such that

where IKO is independent of transistor base-emitter voltages, the current defined by (6) collapses to

I o % vK -IKO. R For Q F E P ~ F E N>> 1, the current, IO, in (5) is therefore independent of thermally sensitive device parameters if the current, I K , is implemented in accordance with (7).
1 1 1 . CURRENT SINK

Then, the substitution of (1 1) into (5) yields the desired thermally stabilized current,

A circuit capable of sinking the current, I K , stipulated by (7) is suggested in Fig. 2. Note that this nontraditional biasing circuit uses two NPN and two PNP transistors connected as base-emitter diodes. An analysis of the topology at hand produces

where VOFF = &I -k 3VEEl - 2VEE2.


(14)

I K = QFEN

(-)

Rz

Rz

+RI

Note that the effective offset voltage, VOFF,cannot q u a l zero, since, assuming VBEN% VEBP,an analysis of the VCSCS in Fig. 3 reveals

%!FEz:
VK

IK IK +Io'

(15)

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: FUNDAMENTAL THE1ORY AND APPLICATIONS, VOL. 41, NO. 5, MAY 1994

407

q4k
'BEN

Qm

&I$ 2

--I

-YEE=
(=*)

-5vDc

$EE

Fig. 4. A thermally stabilized VCSCS designed to deliver an output current, IO. as large as 10 ma for a control voltage setting, VI<, of 2.5 volts.

IV. SIMULATED PERFORMANCE


Fig. 3. Generalized schematic diagram of the thermally compensated VCSCS.

Like the output current, IO, the reference current, II<,must exceed zero, thereby demanding VOFF > 0. Assuming N F E P ~ F E N >> 1, (13) implies an output current that is independent of transistor parameters and thus, the sensitivity of these parameters on temperature. Moreover, (13) suggests a linear relationship between the output current, IO, and the control voltage, L k . The slope, (l/R), of this relationship defines the effective transconductance of the VCSCS. The degree to which the output current, IO, is temperature invariant is, of course, limited by the temperature coefficient of the resistance, R. In particular, the temperature dependence of the output current, as well as that of the effective transconductance of the VCSCS, is an inverse function of the temperature coefficient of R. For proper circuit operation, R must therefore be realized in thin film technology. To this end, cermet (a compound of chromium and silicon oxide) thin film resistances, which feature temperature coefficients in the range of f 5 0 ppm/"C-to-f150 ppm/"C [ll],are recommended. If R is realized in cermet, so must the circuit resistance, REE, be realized in cermet to ensure the satisfaction of (12) over a wide range of operating temperatures. Because of the design requirement, RI = 2R2, the same fabrication restriction applies to the resistances, RI and Rz.

Fig. 4 is an example of a thermally compensated VCSCS designed to supply an output current, IO, in the range of 0 5 IO 5 10 mA for control voltages, L k , in the range 0 < VI< < 2.5 volts. The subcircuit consisting of the transistors, QN1 and QPl, the 215 ohm resistance (R), and the control voltage, VI<, is the actual voltage controlled current source. A dummy 100 ohm load resistance terminates the output port of the VCSCS. A wide load resistance range is possible and, if desired, the load resistance can retum the VCSCS output port to the negative voltage bus line. The only requirement imposed on the load termination is that the resultant voltage established at the collector of transistor QP1 be smaller than the voltage at the QP1 emitter when the indicated output current, IO, is its maximum permissible value. The subcircuit containing the transistors, QN2, QN3, QN4, QP2, and QP3, implements the requisite current sinking commensurate with the thermal compensation of the QN1-QPl subcircuit. With reference to the generalized schematic diagram of Fig. 3, resistance RI is 3,030 ohms, while resistance RS is 1,515 ohms. The simple regulator formed of the two PNP transistors, QP4 and QP5, and its four peripheral resistances (2,49012, 8100, 1,710n2, and 1,1800) derives a temperature independent biasing voltage, ( -VEEI), as delineated in Fig. 3, from the negative supply line voltage, (-VEE). It should be noted that the voltage, (-VEE) in Fig. 4 corresponds to the voltage, ( - 1 5 ~ 2 ) in the diagram of Fig. 3 . Care was exercised to implement, as best as possible, the following design constraints:

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I:

FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 41, NO. 5, MAY 1994

TA1 LE I PSPICE PARAMETERS FOR THE MINIMAL GEOMETRY NF AND PNP TRANSISTORS

PARAMETER
SATURATION CURRENT (/s) IDEAL 6-E JUNCT. EMISSION COEF. (NF) IDEAL B-C JUNCT. EMISSION COEF. (NR)

NPN

PNP

4
B-C CAPACITANCE PARTITIONING f l ~ c ) COLLECTOR GRADING COEFFICIENT (MJc) B-E JUNCTION CAPACITANCE (CJE) B-E JUNCTION POTENTIAL (VJE) SUBSTRATE JUNCT. CAPACITANCE (CJS) SUBSTRATE JUNCT. POTENTIAL (VJS) SUBSTRATE GRADING COEFFICIENT (MJs) NON-IDEAL B-E SAT. CURRENT (/SE) NON--IDEAL &E JUNCT. EMIS. COEF. (NE) NON--IDEAL B-C SAT. CURRENT (1s~) NON--IDEAL B-C JUNCT. EMIS. COEF. (Nc) FORWARD TRANSIT TIME ( 7 ~ ) REVERSE TRANSIT TIME (TR)

fA 0.2654 0.053 I _1.017 I 1.0 __ 1.0 7.016 14.6 20.8 mamps REVERSE KNEE CURRENT (/& 0.1304 0.720 mamps FORWARD EARLY VOLTAGE ( V ~ F ) volts 7 7.74 40.5 REVERSE EARLY VOLTAGE (VAR) volts 4.71 7.873 _FORWARD BETA (PF) 69.43 73.1 REVERSE BETA (PR) 0.41 0.79 BAND GAP POTENTIAL (&) 1.77 1.11 volts __ TEMP. COEF. OF SAT. CURRENT f l , ) 3.0 3.5 j 7.27 7.363 MAXIMUM BASE RESISTANCE (/?& 148 ohms 154.8 MINIMUM BASE RESISTANCE (/?BM) ohms 38 40 ohms EMllTER RESISTANCE (/?E) ohms 6-C JUNCTION CAPACITANCE (CJC) fF B-C JUNCTION POTENTIAL (VJC) mvolts

UNITS

_ _ 1 1 _ 1

__ __

fF mvolts
- -

fF mvolts

__ t i l

To maximize thermal tracking, the densities of currents conducted by the NPN transistors were made approximately the same through judicious choice of their respective base-emitter junction areas. The same design tack was invoked for all PNP devices. The areas indicated in Fig. 4 were computed by examining transistor operating points for VI< = 1.25 volts, which is midway between the control voltage extremes of 0 volts and 2.5 volts. The power supply voltages, 61, VCC, and \$E, were selected to be 5 volts, in concert with the design rules goveming the transistors used in the circuit. The PSPICE parameters for the minimal geometry versions of the utilized NPN and PNP transistors are itemized in Table I('). It should be noted that the NPN and PNP transistor temperature parameters, XTIand XTB,are not identical. The voltage, VEEZin Fig. 3, which is equal to I/& in the schematic diagram of Fig. 4, must be smaller (more negative) than (-VEE~),The latter voltage, which turned out to be 1.783 volts in this design, was implemented by the regulator formed of transistors QP4 and QP5 and their aforementioned resistances. With 141 = Vcc = 5 volts and I k ~ 2 = CEE= 5 volts, V E E ~ = 1.783 volts gives, by (14), an offset voltage of VOFF = 349 millivolts.

4) Since the collector-to-base voltage of transistor QN1 is the emitter-base voltage, & B P I , of QPl, less the base-emitter voltage, V B E N ~ of , transistor QN1, it is prudent to design the circuit'for V E B P ~ > VBENIto ensure that QN1 operates in its forward active domain. This design restriction is implemented by carefully choosing the base-emitter junction areas of, and collector currents conducted by, transistors QN1 and QPl. Fig. 5 is the simulated output current versus control voltage characteristic at 27C and at 125C. For \k greater than about 400 millivolts, the slope of the 27C characteristic, which is the effective forward transconductance of the VCSCS, is 4.50 W v o l t . This result agrees well with the analytically predicted transconductance of 1/R = 1/215 fl = 4.65 mA/volt. The indicated curve also predicts an offset voltage of the order of 200 mV, as compared to an earlier offset calculation of 349 millivolts. The discrepancy between simulated and computed offset voltages can be attributed to imperfect matching between the forward biasing base-emitter voltages of the NPN and PNP transistors. The degree to which the transconductance characteristic is influenced by the temperature dependence of transistor parameters is shown in Fig. 6. This curve reflects the best possible performance of

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409

0.0
Fig. 5 .

0.2

0.4

0.6

0.8

1.0 1.2

1.4 1.6

1.8 2.0

2.2

2.4

2.6

Control Voltage (volts)


Simulated transconductance characteristic at 27C and 125C of the VCSCS in Fig. 4.

and the 125 "C

the VCSCS in that it derives from the tacit presumption that all circuit resistances are thermally matched and have negligible temperature coefficients. It plots the percentage change of the simulated output

current per 10C increments in operating temperature, between operating temperatures of 27C and 125". Note that the temperature sensitivity is negative, and its magnitude diminishes with increasing

410

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FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 41, NO. 5 , MAY 1994

5 4
3

1
0
0.0
Fig. 7.

0.2

0.4

0.6 0.8

1.0 1.2

1.4 1.6

1.8 2.0

2.2

2.4

2.6

Control Voltage (volts)


Simulated transconductancecharacteristic of the uncompensated VCSCS at 27OC and 125OC.

control voltage settings. For 500 mV < VI<< 2.5 V, this temperature sensitivity lies between -O.57%/1O0C and -0.16%/10C. The effectiveness of the proposed compensation scheme is best demonstrated by reconsidering the circuit of Fig. 4, but with the compensating transistors, QN3, QN4, QP2, and QP3, supplanted by appropriate constant voltages. To this end, the series interconnection of the diode-connected transistors, QN3, QN4, and QP3, can be replaced by an ideal battery whose voltage is 2.161 volts. This voltage is the simulated potential difference established between the collector of QN3 and the collector of QP3 at room temperature when 1 1 , = 1.25 volts. Similarly, transistor QP2 can be replaced by a 724 millivolt voltage source. The simulated forward transconductance behavior of the resultant uncompensated VCSCS appears in Fig. 7. Over the control voltage interval, 500 mV < \k < 2.5 V, the temperature sensitivity of the output current, 10, varies from -7.5%/10C-to- 1.25%/1OoC, which is a considerably larger temperature induced change than that evidenced in the compensated circuit. In the linear range of operation, the output port of the VCSCS can be represented as a Norton equivalent circuit whose short circuit static current is the current conducted by a load termination, R L ,which is set to zero ohms. At VI<= 1.5 volts, this short circuit load current varies from 5.839 mA at 0C-to-5.684 mA at 125C. For the same control voltage setting, the corresponding currents conducted by a 100 ohm load resistance is in the range of 5.834 mA-to-5.678 mA. It follows that the effective output resistance seen by the external load resistance is in the range of 116.7 Kf2 at 0C-to-94.6 Kf2 at 125C.

forward transfer characteristics of the VCSCS is achieved. The vehicle for realizing excellent temperature stability is a complementary current sink whose thermal characteristics are made to track those of the transistors embedded in the actual transconductor cell. Further improvements in the observable temperature sensitivity, as well as in the input-to-output linearity, are possible if a monolithic process capable of supporting larger power bus voltages is exploited. Such a capability allows the resistance, REE in Fig. 3, to be chosen larger than the value used in the design, thereby complementing the inequality of (IO). In turn, an improved satisfaction of (10) decreases the sensitivity of circuit performance with respect to the current gain parameter, 1 1 ~ ~ in. both the NPN and the PNP devices.

ACKNOWLEDGMENT The author gratefully acknowledges the technical assistance of Won Chon, Paul Emerson, and Kurt Rasmussen of the Radar Systems Group, GM-Hughes Aircraft Company, El Segundo, CA.

REFERENCES
[ I ] B. Gilbert, A new wideband amplifier technique, IEEE J. Solid Srure Circ., vol. SC-3, pp. 353-365, Dec. 1968. [2] B. Gilbert, A four quadrant analog divider/multiplier with 0.01% distortion, ISSCC Dig. Tech. Papers, vol. SC-3, pp. 284-289, 1983. [3] W. R. Davis and J. E. Solomon, A high-performance monolithic IF amplifier incorporating electronic gain control, IEEE J. Solid Srure Circ., vol. SC-3, pp. 408416, Dec. 1968. [4] W. M. Sansen and R. G. Meyer, Distortion in bipolar transistor variable-gain amplifiers, IEEE J. Solid Srute Circ., vol. SC-8, pp. 275-282, Aug. 1973. [5] E. A. Vittoz, MOS transistors operating in the lateral bipolar mode and their applications in CMOS technology, IEEE J. Solid State Circ., vol. SC-18, pp. 273-279, June 1983.

V. CONCLUSION A voltage controlled static current source (VCSCS) has been designed in a complementary (NPN-PNP) bipolar process. Despite mismatches in the thermal properties of the NPN and PNP transistors utilized in the design, excellent temperature stability in the static

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41 I

M. G. R. Degrauwe, CMOS voltage references using lateral bipolar transistors, IEEE J. Solid State Circ., vol. SC-20, pp. 1151-1 157, Dec. 1985. A. B. Grebene, Bipolar and MOSAnalog Integrated Circuit Design. New York: Wiley-Interscience, 1984, pp. 556-575. B. M. Gordon, Linear electronic analog/digital conversion architectures, IEEE Trans. Circ. and Sysr., vol. CAS-25, pp. 391-418, July 1978. J. 0. Voorman, Analog integrated filters or continuous-time filters for LSI and VLSI, Rev. Phys. Appl., no. 22, pp. 3-14, Jan. 1987. A. B. Grebene, Bipolar and MOSAnalog Integrated Circuit Design. New York: Wiley-Interscience, 1984, pp. 187-1 89. - Bipolar and MOS Analog Inregrated Circuit Design. New York: Wiley-Interscience, 1984, pp. 154155.

Assuming the use of matched devices and that the basewidth modulation is ignored, the differential output current is

AIOIJT= c ~ F ~ ( tanh AI)

(&)

Some Circuit Design Techniques Using Two Cross-Coupled, Emitter-Coupled Pairs


Katsuji Kimura

Abstract-A circuit structure having two cross-coupled, emitter-coupled pairs is proposed as a fundamental analog function element for multiplying two electrical input quantities; the input voltage difference and the tail current difference. The simplest form is well-known as the Gilbert multiplier cell. In this circuit, the tail current difference is the differential output current of an emitter-coupled pair, nearly proportional to the differential input voltage. Therefore, if the tail current difference is the differential output current of a squaring circuit, nearly proportional to the square of the differential input voltage, a squaring multiplier is obtained and can be used for radio communication applications as a frequency mixer with a local oscillator frequency doubler. If the tail current difference is the differential output current of a multiplier then a tripler, capable of multiplying three electrical input quantities, is obtained. The folded technique, for low voltage operation, and the multi-tanh technique, for input voltage range expansion, are employed.

where parameter CVF,, is the dc common-base current gain factor for an npn transistor, and VT(= k T / q ) is the thermal voltage. In addition, k is Boltzmanns constant, T is absolute temperature in degrees Kelvin, and q is the charge of an electron. A I is the differential output current, defined as the result of subtracting the two tail currents. Fig. l(b) shows the transfer characteristic of the cross-coupled, emitter-coupled pairs. Here, tanh(x) is expanded as tanh(z) = x - x3/3... + .E( 1x1 << 1).Therefore, subtraction of the individual tail currents of the emitter-coupled pairs, and multiplication of the current difference and the differential input voltage of the two multiplication of the current difference and the differential input voltage of the two emitter-coupled pairs is accomplished. When I V 1 I = Vr, the nonlinearity of the cross-coupled, emitter-coupled pairs is -7.6 per cent. Therefore, the approximately linear input voltage range is restricted to within [VII < VT for bipolar technology. The input voltage range limits cross-coupled, emitter-coupled pairs to be applied in multiplication circuits with small-amplitude input signals. Taking the derivative of ( I ) , the transconductance of the crosscoupled, emitter-coupled pairs is

I. INTRODUCTION Multiplication circuitry is an essential analog function element acting as a modulator, demodulator, frequency mixer, etc. The Gilbert multiplier cell [ 11 has been especially popular for multiplication circuitry over the past few decades. The outstanding features of the Gilbert multiplier cell are its behavior in operation arising from its simple circuit structures and a limiting characteristic to two inputs. Furthermore, the most often used Gilbert multiplier cell in circuitry involves two cross-coupled, emitter-coupled pairs. This subcircuit accomplishes subtraction of the individual tail currents of the two emitter-coupled pairs, and multiplication of the tail current difference and the differential input voltage of the two emitter-coupled pairs [2]. Therefore, a circuit structure with the cross-coupled, emitter-coupled pairs possesses nice universality. Fig. l(a) shows the general circuit configuration including the cross-coupled, emitter-coupled pairs. Manuscript received July 30, 1992; revised November 24, 1993. This paper was recommended by Associate Editor John Choma Jr. K. Kimura is with the Fundamental Technologies Development Deparment, Mobile Communications Division, NEC Corporation, 4035, Ikebe-Cho, Midori-Ku, Yokohama, Japan 226. IEEE Log Number 9401 188.

Fig. l(c) shows a graph of this transconductance characteristic. Fig. 2 shows well-known linear circuits with a differential input stage and a differential output stage. The simplest circuit proposed by Gilbert [ 11 is shown in Fig. 2(a), the multiplication characteristic of a multiplier is illustrated by drawing two input waveforms and the output waveform in Fig. 2(b). A series connection of two cross-coupled, emitter-coupled pairs and a source-coupled pair is also usable as multiplication circuitry, as shown in Fig. 2(c). Improvements in linearity in the lower emitter-coupled pair has provided an advantage for emitter degeneration and transconductance reduction [3],as shown in Fig. 2(d). This is not achieved by the cross-coupled, sourcecoupled pairs. However, the cross-coupled, source-coupled pairs are applied successfully to a simple operational transconductance amplifier (OTA) [4], as shown in Fig. 2(e). A nonlinear circuit with a differential output stage, such as squaring circuit or a multiplier, can be used for the circuit instead of linear circuits. Then, a squaring multiplier and atripler can be built. These are very useful for radio communication applications such as frequency mixer with a local oscillator frequency doubler, and a frequency mixer with AGC. In this paper, multiplication circuitry consisting of two cross-coupled, emitter-coupled pairs driven by the differential output current of either a linear circuit or a nonlinear circuit will be discussed. Furthermore, a low voltage technique and an input voltage range extension technique are also clarified.
11. FOLDED MULTIPLIERS FOR LOW VOLTAGE OPERATION

Low voltage versions of the bipolar and Bi-MOS Gilbert multiplier cells are shown in Figs. 3(a) and 3(b), using a folded emittercoupled pair and folded, cross-coupled, emitter-coupled pairs [ 5 ] . Although the folded circuits require complementary bipolar and MOS

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