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9/23/13

Analysis Combinational Circuit

Dr. Le Dung
Hanoi University of Science and Technology

From a given combina2onal circuit to analysis


Its func2on (Truth table, Expression forms) Timing diagram (Test vectors, Delay, Hazard/Glitch)

Dr. Le Dung

Hanoi University of Science and Technology

9/23/13

An example (1)
Analysis this combina2onal circuit
2 to 4 Decoder 4 to 1 MUX D0 D1 D2 D3 S S 1 0 Y

b a

m0 A0 A1 m1 m2 m3

f(a,b,c,d) ?

c d

Dr. Le Dung

Hanoi University of Science and Technology

An example (2)
Modular understanding
2 to 4 Decoder m0 A0 A1 m1 m2 m3 m0 m1 m2 m3 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 S1 0 0 1 1 S0 0 1 0 1 4 to 1 MUX D0 D1 D2 D3 S S 1 0 Y D0 D1 D2 D3 Y

A1 0 0 1 1
Dr. Le Dung

A0 0 1 0 1

Hanoi University of Science and Technology

9/23/13

An example (3)
Truth table Expression forms
c
0 0 0 0 0 0 0 0 1 1 1 1

d
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

a
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

b
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

f
1
0 0 0 0

f=Y=D0

1
0 0 0 0

f=Y=D1

f = (0, 5, 10, 15) = (0, 5, 10, 15) cdab abcd

1
0 0 0 0

f=Y=D2

f = abcd + abcd + abcd + abcd

1 1 1 1

f=Y=D3

Dr. Le Dung

Hanoi University of Science and Technology

An example (4)
Expression forms
c 0 0 1 1 d 0 1 0 1 F = Y = D0 = m0 = ab D1= m1 = ab D2= m2 = ab D3= m3 = ab

f = m0.cd + m1.cd + m2.cd + m3.cd = abcd + abcd + abcd + abcd = (a c)(b d) = (a + c) + (b + d)

Dr. Le Dung

Hanoi University of Science and Technology

9/23/13

An example (5)
Timing diagram with no delay
a b c d

f = (a c)(b d)

Test vectors : abcd = 000010001010111011110111010101000000

Dr. Le Dung

Hanoi University of Science and Technology

An example (6)
Timing diagram with delay
a b c d m0 = D0 m1 = D1 f Test vectors : abcd = 0000 0100011001000101
Dr. Le Dung Hanoi University of Science and Technology

9/23/13

Sta2c Hazard /Glitch


Hazard condi2on: A single variable change causes a
momentary output change when no output change should occur.

Cause: dierent delay in two paths (see Example)


Glitch: The momentary output change = unwanted transient pulse + Sta2c 1-hazard = glitch 101 (in SOP ) + Sta2c 0-hazard = glitch 010 (on POS)

Solu2on: Adding redundant terms (product terms or sum terms)

Dr. Le Dung

Hanoi University of Science and Technology

An example of sta2c 1-hazard


a
INV

A B

AND 2

Y X1 A B
OR 2

Y = f

c b
a = b = 1 c X1 X2 f
Dr. Le Dung

A B

AND 2

Y X2

Sta2c 1-hazard = glitch


Hanoi University of Science and Technology

9/23/13

Removing sta2c 1-hazard


a c b
A B
AND 2

Y X1 A B C
OR 3

A B A B

AND 2 A

Y X2

AND 2

Y X3

Sta2c hazard free

Redundant term = consensus term

Dr. Le Dung

Hanoi University of Science and Technology

Dynamic hazard
A dynamic hazard is the possibility of an output changing more than once as a result of a single input change Cause: dierent delay in mul2ple paths

Dynamic Hazard on 0 1

Dynamic Hazard on 1 0

Any circuit that is sta2c hazard free is also dynamic hazard free Any circuit dynamic hazard free
Dr. Le Dung Hanoi University of Science and Technology

9/23/13

An example of dynamic hazard (1)

Dr. Le Dung

Hanoi University of Science and Technology

An example of dynamic hazard (2)

Dr. Le Dung

Hanoi University of Science and Technology

9/23/13

An example of dynamic hazard (3)

Dr. Le Dung

Hanoi University of Science and Technology

Func2on hazard
Func2on hazards are non-solvable hazards which occurs when more than one input variable changes at the same 2me.

Func2on hazards can not be logically eliminated with actual specica2on of the circuit. The only real way to avoid such problems is to restrict the changing of input variables so that only one input should change at any given 2me.

Dr. Le Dung

Hanoi University of Science and Technology

9/23/13

Hazard-free design
Hazards are hard to detect by hand: importance of simula2on The danger for hazards increases when rise 2mes and fall 2mes are not equal Are hazards a problem?
For synchronous circuits, they are not Unless they control the clock of a memory element For asynchronous circuits, they always are a problem

Dr. Le Dung

Hanoi University of Science and Technology

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