uck Convc,-jrtcr Digit,d C-onLLol 3-lediod . for Cumm. Shana g of hiterleavM SyiicL-oam.

B Buck Converter

Digital Control Merlircis for CLLIWIU Sharing of Interleaved SynelironoLLs

U NDEL'ND Tore hl. UNIILLANI) Tore M.

Digital Control Methods for Current Sharing of Interleaved Synchronous Buck Converter
PAL Andreassen, Tore M. Undeland Norwegian University of Science and Technology O. S. Bragstadsplass 2E Trondheim, Norway Tel.: +47- 73594210 Fax: +47 - 73594279 E-Mail: pal.andreassenIe1craftntnu.no URL: http://www.elkraft.ntnu.no/eno/

Keywords
(Converter controt>, (dDSP, (<ZVS converters>

Abstract
The quasi square wave operation of the synchronous buck with interleaved parallel outputs has been successfully used in low voltage high current DC-supply for microprocessors. This topology results in fast trsient response and high power density. In this paper, two digital control strategies for current sharing control are tested by simulation in Simulink, and tested in the laboratory. The digital current control methods are tested using a 150 MHz Texas Instrument TMS320F28 12 DSP and studied with regard to the current reference step response. The results from the simulations and the experiments show that it is possible to increase control performance by using a predictive controller but that this would require extra cost and design effort to implement a low noise and high bandwidth measurement hardware on the output voltage.

Introducfton
The quasi square wave (QSW) operation of the synchronous buck converter is proven to result in fast transient response, high power density and zero voltage switching (ZVS) [1]. This topology is a good candidate for high current low voltage DC-supply for microprocessors. The synchronous buck in QSW operation is operated in a so called synchronous continuous conduction mode [3]. By allowing reverse current through bidircctional switches, the power may flow in both directions. Because of this, the ZVSQSW converter could be used in topologies where bidirectional power flow is needed [2].
The disadvantages of the quasi square wave operation are high transistor peak current and high input/output current ripple, to achieve zero voltage switching.

Vin

+~ ~ ~ ~ ~V

Fig. 1: Interleaved ZVS Quasi Square Wave Buck Converter

lilt 2005 - Dic,-,deii Dresden E1?E

ISBN : 90-75815-08-5,

P.1 I'd1

Conva-ter Digit,d C-ontLol rvlc,-tlio& for Current Shariikg of litmrlcaved Syneltronotis SyncL-oiiom BtLek Back Converter

Digital Control Methods for Current Sitaring of Jiirerlnsved

U NDJ-L'ND Tore hl. UNDLLAND Tore M.

The current ripple is more than 2 times the average output current. High turn-off current of the main switch tends to increase the turn off losses, especially when minority-carrier devices such as IGBTs are used [2].

Because ofthe high current ripple, interleaved parallel outputs are necessary in order to keep the ripple current in both the input capacitor and the output capacitor low. With the interleaved parallel outputs a controller is needed in order to ensure load current sharing and phase shift ofthe current ripple.

The most common solution in order to implement current sharing is analog peak current mode control [4]. The error signal of the output-voltage controller is used as a common peak current reference signal for all parallel outputs. The common reference signal is compared with the instantaneous inductor current in a separate controller for each output. The PWM output is set low if the inductor current is larger than the reference signal. The result is a separate duty cycle for each module in order to level out the peak current in all of the outputs. The sharing of the average current will therefore be dependent on the variation of inductance in each output.
A direct implementation of the analog peak current mode control scheme in digital hardware would require a very fast AID converter because you would need a large number of samples per switching period. The need for large signal processing capabilities would require expensive hardware. Therefore, methods more applicable to digital control hardware have been developed [5, 6].

Digital control and sampling strategies

The TMS320F2812 DSP used in these experiments has two event-managers. With the event-manager up-down timer can be set up to a triangular wave form and compared to an input value to generate symmetric pulse width modulation (PWM). The event-manager can then generate up to four interrupts. It can generate an interrupt on timer underflow, on timer period match and on compare match both in upand down-counting direction. Fig.2a shows the available interrupts. A compare match triggers the switching ofthe transistors. Sampling of interleaved currents Based on the theory of symmetric PWM, in steady state the peak current will be on compare match in upcounting direction, the valley current will be on compare match in the down-counting direction, and the average value of the inductor current will be on timer underflow and on period match. The interrupts can trigger a sampling of the current. In which interrupt to sample the current may be selected based on if the peak current, the valley current or the average current is to be controlled.
an

o s

Ji

Timer7 ~~~~~~~~~~~Timerl
^ A ' PWMj1 PWM2

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IPWM

Compare 1&2

Int

Int
(a)

Int

Int

Sample[n]
Vin,o,
LI, IL2

Sample[n+1]
vin,vo,
(b)
LI, L2

Fig. 2: (a) Single triangle sampling and interrupts (b) Interleaved sampling and pulse width modulation

IiPL 2005 -- 91Di Dresden DEl 20X;

ISBN :90-75,801-%-f

P.22
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This method of sampling the current and generating a pulse width modulated signal is often used in new digital control of motor drives. With the ZVS-QSW converter this sampling method can be very useful in average current control in order to filter out the ripple current which will be more than 200% peak to peak of the average current. Analog filtering ofthis ripple would result in long delay times in the feedback and low bandwidth for the control, but with the timer underflow sampling this ripple current is filtered out digitally. The factors that will reduce the bandwidth of this digital control will now be the delays in the feedback loop, the effect of zero order hold (ZOH) sampling, and the computational speed of the DSP.

The average current may be sampled at both the period match and timer underflow. This can be utilized so that all measurements, V,, V0, IL, and IL2 are sampled at the same time. The average current in the LI inductor is sampled at timer underflow of timerl . And the average current in the L2 inductor is sampled at period match of timer2 which is the same as timer underflow of timerl. Fig. 2b shows the principle of
sampling and the pulse width modulation of the interleaved signals. Control design A digital average current sharing controller is implemented using symmetric PWM and timer underfiow sampling. The structure of the control system is shown in Fig. 3a. The bandwidth of the current mode controller is reduced due to delays in the feedback loop and due to the effect of the zero order hold. Linear control The control to inductor current transfer fumction for one ofthe parallel outputs is derived by averaging over one switching period and by linearization. Eq. 1 shows the derived transfer function. R. is the load resistance, L is the output filter inductance, and C is the output capacitor.
11 dS =G(s)

L (s2

R0C

(1)

R0C LC
The system transfer function is then discretized by adding a zero order hold element and sampler at the sampling frequency of 50 kHz [9]. A discrete PI controller is then added to the system. It is the frequency response of the discretized system that is studied. The gain and time constant of the discrete controller is adjusted for sufficient open loop phase margin. The design criteria used is an open loop phase margin of at least 50 with input voltages, Vm,, up to 2 times the nominal input voltage. Predictive control With digital control, predictive methods may be used in order to compensate for the effect of zero order hold sampling and delays in the feedback loop. In [6] a general predictive control law is proposed. This method can be adapted to the average current sharing control of the ZVS-QSW converter. With symmetric PWM and timer underflow mterrupt samplng, the current in the inductor at the time, nT,, is given by the following equation.

iEl?] = iL[77-I]+

-*d, d, T'-

d*'* T

(2)

where iLfn] is the inductor current at the nth interrupt, VI, is the input voltage, VO is the output voltage, d,, is the duty cycle in the nth period, L is the inductance, and T2 is the sampling period. The duty cycle can also be described as d,,-(l-d, . Eq. (2) can be rewritten to

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2005 D"W.d
-

ISBN

90J758tI-O-5

PB.3

Digitd C-ontiol Nicthod -N for Cturcm Sliariw of iaDz:rlcavM SyncL-oaom Buch. Om vcr.cr

Digital Control Mcthocts for CLLrrcnr Sharing of lnrrrlctwod Synchronous Buck Convcrrrr

U NDJ-L'ND Tc-r hlq UNDLLANI) Torr IA.

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(a)

Fig. 3: (a) Digital average current sharing control (b) Sampling and PWM with predictive control

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r c, T Es- Lo rT

(3)

The predicted current at the next interupt will then be

V[n +1] = iL[n -1] + Fn

ld, + d,,I) T, -2. V T,

-

(4)

The control objective would then be to control the predicted inductor current to the current reference
value,

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+

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cycle,d1,
VI'

can now

be calculated based

on

Eq. (4)

(gkf* i L[n -1])+2

(5)

Eq. (5) is the predictive control law for the average current sharing of the interleaved QSW converter. The controlled current waveform and the symmetric switching and sampling scheme is illustrated in Fig. 3b.

Simulations of the converter control system

The simulations are done in Simulink. The modeling of the converter is with the dynamic node technique [9]. Elements in the converter are modeled separately and connected together by capacitive nodes in the system. The control system is modeled with the standard elements of the Simulink library. The values of the circuit elements illustrated in Fig.3a are the same through all simulations and laboratory tests. The values used are, LI-L2-l3pH, C-40yH, R0-2.I and ,,z-IOV. Simulations of the interleaved converter with linear control The simulation set up of the linear control system and the simulation result of a current reference step is shown in Fig.4. The discrete transfer fimction ofthe current controller is based on the previously described design criteria and takes into consideration the delay due to the zero order hold.

LIt 2005 Dstzsdru 0 -- D A DEl 20 it1

ISBN :90-75815-0W-5

P.4 P>.4

Convcr.cr Digit,d C-ontLol Mc,-.io& for CAurc,-iit SlLiring of litterleavW S)IWIhIOItOLLS SyncL-oaotu; Buch. Buck Converter

Digital Control Morliods for Curront Sharing of Interleaved

U NDJ-L'ND Tore hl. UNDLLANI) Tore M.

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Fig. 4: Simulation set up and simulation result of a current reference step.

Simulations of the interleaved converter with predictive control The simulation set up of the predictive control system is shown in Fig.5. The simulation result of a current reference step is shown in Fig.6.

With the output voltage measurement, the predictive curTent controllers are coupled together. This can result in oscillations. Therefore, the gain in the current feedback loop should be reduced in order to reduce the oscillations. The gain will not be according to the predictive control law, but close to. The performance of the controller is not signficantly reduced by reducing the gain. Also a filter on the output voltage measurement will reduce oscillations between the two current controllers.

Fig. 5: Simulation set up of the predictive controller.

The simulations were first done assuig no noise and no filter with reduced bandwidth on the voltage measurement. The result of the no noise simulation is shown in Fig.6a. In any practical circuit this will not be possible. A filter on the measurement will be needed and still then there will be some noise on the sanpling input. Therefore a simulation with more realistic filter ad noise properties is performed. The

results ofthe predictive control with filter and noise is shown in Fig.6b.

IiPL 2005 - Di Dreselen DEl 20X; 1-zdeit

ISBN

ISBN :90-75,80 165,

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thm ise very ltdc nose rceflion predictie conrollr tberctcay will have the fate step responw. in dfi voltage fixback loop of he ot; vwlta gJtti le-ads to ripple on thie outu lhe ripple can be
h pero ne An oute reducd by fltaing th voltape meauremcnts m But hi wllagi ro lineBar voltage conrl loop wol rult in better noise rej:tion adthe negatve ftdm&c loop will rxac the voltage ripple. A conrl board wih a Texa IF281s 282 DSP is usod totest fe digitSl 0ontrol Unh*ues. Two
ous buk convres acouplod togetlbve.The input voltage Vi,, thieoutput volte ,, and ELe mrt;TL, in each ofthe two inucs is smpled. Te curarent is controed uigte two Uikr digital omtrol ucbniquc mpeene in thie 281 2 DSP.

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Fig. 6:- Simlation of a curet nfrne itte

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Ihe sme circuit values as the values used in the siuaiwarre used in fthe la ly- wt up. The of a curret rofcne step tDthe linear control is &hiowl in Fig.7. The msuewn of a isshwn tmen refm=e ei:p to the predictve contrl B WI Fig.8.

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Conclusion

This paper has discussed and tested two digital control techniques for average current aring of te intrleaved synchronous buck converter. The rsults both by simulaton and eperiments show that any improvement in clontroa predictive oDntrol medhod is only possible when by plem ing a low noise high bandwidth mesurement e of the the out voltage. ihe perf control is possble but not without the adtional oost ofbetter hardwae.
a
on

References [1 ]. X. ZhoLl, P.-L. WNong P. Xu, FtC. Lee, KQ. Iluang, Investigation of Candi'date VRtI Topologies for Fuuer MiEompnxcessors IEE Transactions on Power Elecnrnies, Volu: 1t No: 6, Nov. 2000 Lcc [2]. G.Hu11a., &-Sxvitclhing Thchriiqiu.cs ini P WM- cotwv ttrs, fIdulstrial Elc ics, Control and [istrumvnicntnoni, fltciccings of he[CON '93, 1p 6)7-643 ieC W-.T.\ g, "High-Efficiency Opertion of Hig-FrertiencyXT7'.DC Conversio for Next-GTeneralion SC [3]5. Voliume: I p30-35 Nficroprce$sor"', Prccee1irgs of IECOWN V, [4]. X. ZIOLl, P. Xu. F.C, Lee, AQ. IIuang, "A Novel CiuTmTt-Slharig Control Tehiiique for Low-Voltage I1gb,

i'

Nov. 2.0(N. [5]. S. Bibian, JiP "Digitq Colntrol wth lrnpLnvcd P[rformanc for Boost Power Factor Corretion Circuits". I . APE-C 9001t.Sxi.eenii Anim EEE Volumire: I 4-8 Applied Power Electrmoics Coference and Dqxosition, 201
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CQurramt Voltage Regulator M-dul

Applihations, E[-EE

Trmansactions oni Powr

Elntonies, Volutme:

1 5,

No:

6,

[6]. J Clien, AK Ptrcdic, RAWV Erikson D. LMik;sinovic, Predictive Digital Cunrent Prngrammne (bnn3A, [BEEE Trnisactions on Power Eloetmiies, Voluine 18_ No 1., Nov. 2003. ApIp catoion Iand Design> 2n$;)d E--dition, I [7]. N. M{ohaa, 7F.M. ULTdehtd, W.Robbin. "Power jElctroicsCs vcrcrsp Join Wilcy Sons, 1995 [8]. RW-. Erick-son "Fundlanenlals ofPIower Eleclroni' 5 ih Printinii Kluwer Academic PiblishLers 199') [9].Flinlers, F.; Oghlanna, XV.r; "Silniulation of a eomplex Iraclion PWMN1 reciifier using ;SLEMLLNK and ih1e dynamic node teclmiql&e,' Indstrial Eleaciics, Cotntm andl Imsunmentrion. 1997 [ECON 97. 23rd International
ConfceLnace oni Voue
2

Miarch

2001

9-14 Nov. 1997 Pag

9

c: 73 8 -

743

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