Course Code Course Title Assignment Number Maximum Marks Last Date of Submission

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CS-64 Introduction to Computer Organisation BCA (4)-64/Assignment/ 2012 100 (Weightage 25%) 30th April, 2012/ 30th October, 2012

There are three questions in this assignment. Answer all the questions. You may use illustrations and diagrams to enhance your explanations. You may use illustrations and diagrams to enhance the explanations. Please go through the guidelines regarding assignments given in the Programme Guide for the format of presentation. Answer to each part of the question should be confined to about 300 words.

1) (a) Convert the following numbers as asked: (i) Decimal 999 to Hexadecimal (ii) Octal 555 to Hexadecimal (iii) Hexadecimal AAAA to Decimal (iv) Hexadecimal AAAA to Octal

(4 Marks)

Ans: You can do It. (b) Assume that a computer represents negative integers in signed 2s complement notation having the size of 8 bits. You may also assume that all the registers used for integer arithmetic are of 8 bits. Perform the following operations using this computer (the numbers indicated in the operations are decimal numbers). Indicate the overflow condition, if any. (i) Add -38 and -90 (ii) Subtract 90 from 38 (iii) Add 63 and 65 (iv) Subtract -90 from -65 (4 Marks)

Ans: You can do It. (c) A four bit data 0001 is to be sent across a communication channel. What should be the parity bits for SEC code, if this data is to be sent correctly across to a destination? Also indicate where these SEC code bits will be placed in the data + code bit combination that is to be sent. Assume that the data bits that were received were 1 S 0 S 0 S 1 (SEC bits remained unchanged in between wherever they were, that is the value of S may the related SEC bit or Null ). Correct this code using SEC bits generated at the receiver and the SEC bits received from the sources. Show all the steps of this process. (6 Marks)

Ans:

Dont copy as it is. You can solve yourself using this example.
Transmission sent using even parity:

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A wants to transmit: A computes parity bit value: A adds parity bit and sends: B receives: B computes parity:

1001 1^0^0^1 = 0 10010 10010 1^0^0^1^0 = 0

B reports correct transmission after observing expected even result. Transmission sent using odd parity: A wants to transmit: A computes parity bit value: A adds parity bit and sends: B receives: B computes overall parity: 1001 ~(1^0^0^1) = 1 10011 10011 1^0^0^1^1 = 1

B reports correct transmission after observing expected odd result. This mechanism enables the detection of single bit errors, because if one bit gets flipped due to line noise, there will be an incorrect number of ones in the received data. In the two examples above, B's calculated parity value matches the parity bit in its received value, indicating there are no single bit errors. Consider the following example with a transmission error in the second bit: Transmission sent using even parity: A wants to transmit: A computes parity bit value: A adds parity bit and sends: *** TRANSMISSION ERROR *** B receives: B computes overall parity: 11010 1^1^0^1^0 = 1 1001 1^0^0^1 = 0 10010

B reports incorrect transmission after observing unexpected odd result. B calculates an odd overall parity indicating the bit error. Here's the same example but now the parity bit itself gets corrupted: A wants to transmit: A sends: *** TRANSMISSION ERROR *** B receives: 10011 1001 10010

A computes even parity value: 1^0^0^1 = 0

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B computes overall parity:

1^0^0^1^1 = 1

B reports incorrect transmission after observing unexpected odd result. Once again, B computes an odd overall parity, indicating the bit error. Consider the same example as before with an even number of corrupted bits: A wants to transmit: A sends: *** TRANSMISSION ERROR *** B receives: B computes overall parity: 11011 1^1^0^1^1 = 0 1001 10010

A computes even parity value: 1^0^0^1 = 0

B reports correct transmission though actually incorrect.

(a)

A logical function calculator compares two numbers for the function A >= B. The comparator output 1 of the comparison is TRUE else FALSE. In case if both A and B are equal, the comparator outputs a second bit as 1 (0 otherwise). The partial truth table for the comparator is given in Figure 1:

Number A Bit 1 0 0 ... 0 0 ... 1 1

Bit 0 0 0 ... 1 1 ... 0 1

Number B Bit 1 0 0 ... 0 0 ... 1 1

Bit 0 0 1 ... 0 1 ... 1 1

Output Same 1 0 1 1 0 1

Zero 1 0 0 1 0 1

Figure 1: The partial truth table for A>= B for the two output Complete the truth table and design and draw the combinational circuit using ANDOR-NOT gates for the description given. (6 Marks)

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(b)

Why do you need a flip-flop? Explain the characteristics table of J K flip flop. How is it different than that of S R flip flop? Explain the synchronous counter in the context of change of states of the flip flop. (4 Marks)

Ans:
Flip-flops are synchronous bistable devices. The term synchronous means the output changes state only when the clock input is triggered. That is, changes in the output occur in synchronization with the clock. Flip-flop is a kind of multivibrator. There are three types of multivibrators: Monostable multivibrator (also called one-shot) has only one stable state. It produces a single pulse in response to a triggering input.

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Bistable multivibrator exhibits two stable states. It is able to retain the two SET and RESET states indefinitely. It is commonly used as a basic building block for counters, registers and memories. Astable multivibrator has no stable state at all. It is used primarily as an oscillator to generate periodic pulse waveforms for timing purposes. Edge-triggered J-K flip-flop The J-K flip-flop works very similar to S-R flip-flop. The only difference is that this flip-flop has NO invalid state. The outputs toggle (change to the opposite state) when both J and K inputs are HIGH. The truth table is shown below.

(c)

What is associative memory? Explain with the help of a diagram. What is a Cache memory? What are its different organizations? Explain the Associative cache memory organization with the help of a diagram showing mapping from main memory to the cache memory. You must show proper addresses for both the memories in the diagram. However, for simplicity, you may take size of the main memory as 32 byte and cache as 4 byte. (4 Marks)

Ans:

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Associate cache is content addressable memory. The cache memory does not have its address. Instead this memory is being accessed using its contents. Each line of cache memory will accommodate the address and the contents of the address from the main memory. Always the block of data is being transferred to cache memory instead of transferring the contents of single memory location from main memory. Memory is an essential component of a computer system. It is used to store data and instructions. There are various types of memories. There is a hierarchy of memories:CPU register Cache memory Main memory Secondary memory

CPU Register It is a smallest and fastest memory that resides in CPU so it is called internal processor memory. It holds the data during execution in CPU. There are large numbers of register in CPU, which increase the efficiency of processing. Cache Memory It is also High-speed memory. It placed between CPU register and Main memory logically. As we know, there is difference between the speed of CPU and Main memory. Generally, CPU Speed is faster than main memory. So, it is used to make the balance speed between them. It catches the data from the main Memory and send to the CPU and vice-versa. It improves the data transfer rate between main memory and CPU. Main Memory Main memory is a small and relatively fast storage device that store data and instructions those are currently used by computer. Means, it receives the data from the user directly through the input device. Thereafter, it goes to the CPU for the execution and finally data stores into Secondary Storage Device. It is a volatile memory so looses their contents on power failure. Secondary Storage It is mass storage device also called auxiliary memory. It stores the data permanently as user desire. For example - Hard disk is a device used for mass storage of data. All data and program are stored in Hard Disk.

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(d)

You have been asked to design the configuration of a database server (please do not give the names of manufacturer), specifically the RAID configuration for your server. Which of type of RAID machine will you select? Give justification in support of your answer. Also explain the process of interrupt handling when more than one interrupts can occur simultaneously. (4Marks)

Ans: RAID Level 5 is more suitable for this becauseRAID 5 is the most common secure RAID level. It is similar to RAID-3 except that data are transferred to disks by independent read and write operations (not in parallel). The data chunks that are written are also larger. Instead of a dedicated parity disk, parity information is spread across all the drives. You need at least 3 disks for a RAID 5 array. A RAID 5 array can withstand a single disk failure without losing data or access to data. Although RAID 5 can be achieved in software, a hardware controller is recommended. Often extra cache memory is used on these controllers to improve the write performance.

In 5th level parity bits are not separated for the data bits. It has very high data transfer rate. So it is useful where high input/output required.

Advantages Read data transactions are very fast while write data transaction are somewhat slower (due to the parity that has to be calculated).

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Disadvantages Disk failures have an effect on throughput, although this is still acceptable. Like RAID 3, this is complex technology. Ideal use RAID 5 is a good all-round system that combines efficient storage with excellent security and decent performance. It is ideal for file and application servers. (e) Explain the functions and purposes of Direct Memory Access (DMA) and Input/output processor in Computer. Find out how in Pentium processor I/O devices are connected to the system bus. (4 Marks)

Ans: DMA:-Direct memory access (DMA). Module is required when large amount of data is to be transferred. DMA transfers the requested block bytes by byte directly to the memory with out CPU interaction after completion the transfer (request) DMA send a signal to CPU. Thus we can say DMA module perform the task requested by CPU. This type of data transfer is called direct memory access (DMA),

The DMA controller needs the usual circuits of an interface to communicate With CPU and I/O device. In addition, it needs an address register, a word count register, and a set of address line. The address register and address line are used for direct communication with the memory. The word count register specifies the number of words that must be transferred. The data transfer may be done directly between the device an memory under control of DMA.

The DMA controller has three register : an address register, a word count register, and control register. The address register contains an address to specify the desired location in memory. The

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address bits go through bus buffers into the address bus. The address register is incremented after each word that is transferred to memory. The word count register holds the number of words to be transferred. The register is decremented by one after each word transfer and internally tested for zero. The control register specifies the mode of transfer. All register in DMA appear to CPU as I/O interface register. Thus the CPU can read from or write into DMA register under program control via the data bus. transfer data be memory a per unit transferred

2) (a) Is it possible to have an Instruction set with no operands at all? Justify your answer. Assume that a machine is to be designed for performing simple arithmetic operations (including unary and binary), what should be the optimum number of operand in an instruction set for such machine? Give justification in support of your answer. How does the number of operand addresses in an Instruction Set affect the size of a program on a computer? (4 Marks)

Ans: Ans. As we know, an instruction set is a collection of all the instruction that can be executed in CPU. All instructions are represented in a sequence of bits. An instruction is divided into no of fields and layout of instruction set is called format. This Means A program in computer consists of sequence of instructions. Executing these instructions runs the program in computer. Moreover each instruction is further divided into sequences of phases The concept of execution of an instruction through different phases is called instruction cycle. The instruction is divided into sub phases as specified ahead. Thus we cannot think instruction set without operands. 1. First of all an instruction is fetched (accessed) from memory. 2. Then decode that instruction., 3. Decisions is made for memory or register of I/O reference instruction, in case of memory indirect address, read the effective address from the memory. 4. Finally execute the instruction.

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This life cycle shows how Number of operator affects the size of memory. A machine is to be designed such that it stores arbitrary length arrays in the memory. This machine also supports subroutine calls. Suggest four best addressing modes for the machine. Give reasons for your selection. (4 Marks) Ans: four best addressing modes for the machine are:1. Auto increment or Auto decrement mode : This is similar to register indirect mode except the register is incremented or decremented after (or before) its value is used to access memory. When the address stored in register refer to a table of data in memory, it is necessary to increment or decrement the register after every access to the table. This can be achieved by using the increment to decrement instruction. However, because it is such a common requirement some computers incorporate a special mode that automatically increments or decrements the contents of register after data access. (b)

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2. Relative address mode: In this mode, the content of program counter is added of address part of the instruction in order to obtain the effective address. The address part of instruction is usually a signed number (in 2s complement representation) which can be either positive or negative. When this number is added to the content of program counter, the result produces an effective address whose position in memory is relative to the address of the next instruction. 3. Indexed addressing mode: In this mode, the content of an index register is added to the address part of the instruction to obtain the effective address. The index register is special CPU register that contain an index value. The address field of instruction defines the beginning address of a data array in memory. Each operand in array is stored in memory relative to the beginning address. The distance between the beginning address and the address of the operand is the index value stored in the index register. Any operand in the arrays can be accessed with the same instruction provided that the index register contains the correct index value. The index register can be incremented to facilitate access to consecutive operands. 4. Base register addressing mode : In this mode, the content of a base register is added to address part of instruction to obtain the effective address. This is similar to the indexed addressing mode except that the register is now called a base register instead of an index register. (c) Consider the instruction ISNZ Op where Op is a register operand that is the address of an instruction of the executing program. The instruction checks if the value of the previous instruction execution is NOT ZERO (the result may be in the AC register), if so then it branches to the address specified by the Op. Write the sequence of micro-operations that will be required to execute this instruction. You may use various micro-operation cycles and the necessary registers. (6 Marks)

Ans: (d) Assume that an 8-bit Register R has the data 01101110. Perform the following operations on the register R: (i) Selective Set the lower 4 bits to 1100

Ans: Lower 4 bits 1110 Given 4 bits 1100 ___________________ Selective set 1110 ___________________ (i) Extract the lower 4 bits Ans: 00001110 (ii) Clear the register using a logical operation Ans: Clear all bits using XOR 0110 1110 __________________ 1000

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__________________

(iv) Insert a value 1111 in the lower 4 bits of the register. Ans: 01100000 00001111 ___________ 01101111 ___________

(4 marks)

Represent the following floating point numbers using IEEE 754 floating point single precision format. i. 32.0125 Binary of 32.0125 is 0 0 1 0 0 0 0 0.000 Normalized from is 1.00000000 X 25

(e)

Sign bit = 1 Significand field = 0000...000 Exponent field = 5 + 127 = 132 = 1000 0100 Complete 32-bit number is:
1 10000100 ii. -0.125 Do as same. (f) Explain the working of the control unit of a computer with the help of a Block diagram. Explain the importance of micro-instruction in computer. Also explain the differences between the horizontal and vertical microinstructions. (8 marks) 00000.000 (4 marks)

Ans: Ans. Control unit controls the input and output execution. Control unit operations Master clock signal: -Clock signal to be set 0 or 1 for the micro operation that means it indicates the clock signal and count the time how many ns taken by micro operation. Instruction register:- Instruction register of CU determines the addressing mode of bits (instruction) that means operational code always need address to perform the micro operation. Flags: - It is used to determine the status CPU. Control signals from control bus: - CU receives the control signal from the control bus that means outside of CPU. Control signal within CPU: - That means such type of control signal is used for micro operations and transfer data from one register to another register. Output control operation

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Control signal in CPU: - Such type of signal is used to transfer of the data from one register to another register means output register. Control signal to control bus: - Such type of control signal transfer data form CPU registers to main memory input/output device.

Functions 1. Exchange the data between CPU and memory or input/output module. 2. Exchange the data between registers. 3. Instruct ALU to perform specific operations. 4. It controls all regular operations happening in CPU. Micro operation is a basic operation of system that is performed on the data stored in register in digital computer. The function of a computer is to execute programs. We have seen that the operation of a computer, in executing -a-program, consists of a sequence of instruction cycles, with one machine instruction per cycle. There are four types of micro operation: Register transfer micro operation. Arithmetic micro operation. Logic micro operation. Shift micro operation. Horizontal microcode is typically contained in a fairly wide control store; it is not uncommon for each word to be 56 bits or more. On each tick of a sequencer clock a microcode word is read, decoded, and used to control the functional elements which make up the CPU. In a typical implementation a horizontal micro program word comprises fairly tightly defined groups of bits. For example, one simple arrangement might be: In vertical microcode, each microinstruction is encodedthat is, the bit fields may pass through intermediate combinatory logic which in turn generates the actual control signals for internal CPU elements (ALU, registers, etc.). In contrast, with horizontal microcode the bit fields themselves directly produce the control signals. Consequently vertical microcode requires smaller instruction lengths and less storage, but requires more time to decode, resulting in a slower CPU clock. 3)

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(a)

What are the advantages of having segments in 8086 micro-processor? Explain the use of stack segment register and process of calculation of physical address of the top of the stack in 8086 microprocessor. (4 marks)

Ans: Advantages: 1. Complex problems can be segmented into smaller and more manageable form. 2. Team development is possible because of logical segmentation. A team of programmes will build the system, and work has to be subdivied along clear boundaries. 3. Upper layer can share the services of a lower layer. Thus layering allows us to reuse functionalities. 4. Each layer is specialized for specific functioning. 5. Late source code changes should not ripple through the system because of layered architecture. 6. Similar responsibilities should be grouped to help understability and maintainability. 7. A message that moves downwards between layers is called request. A client issues a request to layer. I suppose layer I cannot fulfill it, then it delegates to layer J1. 8. Messages that moves upward between layers are called notifications. A notification could start at layer I. Layer I then formulates and sends a message (notification) to layer j +1. 9. Layers are logical placed to keep information caches. Requests that normally travel down through several layers can be cached to improve performance. Stack pointers are used to implement a processor stack in memory. In many processors, address registers can be used as generic data stack pointers and queue pointers. A specific stack pointer or address register may be hardwired for certain instructions. The most common use is to store return addresses, processor state information, and temporary variables for subroutines. It allows the memory capacity to be 1MB even though the address associated with individual instructions is 16 bits wide. It allows the instruction, data, or stack portion of a program to be more than 64KB long by using more than one code, data, or stack segment

(b) Ans:

Explain the REPE, CMPS, AAA, and XLAT instructions of 8086 processor with the help of one example each. (4marks)

REPE It repeats the instruction until CX =0 or ZE not equal to 1 Example:CAMPS It compares two strings. MOV CX, 5

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MOV SI, OFFSET STR1 MOV DI, OFFSET STR2 REPE COMPS AAA Example:ASCII adjusts after addition. MOVE AL, 5 ADD AL, BL AAA XLAT Example:The 80x86 instruction set includes an instruction that allows us to perform table lookup. The instruction is XLAT, and it takes no operands. MOV MOV XLAT BX,OFFSET HA_TABLE ;Offset of table AL,H_DIGIT ;Position of table entry ;Now AL contains ASCII code

(c)

Explain any one direct, one register indirect, one based indirect and one indexed indirect addressing modes of 8086 microprocessor with the help of an example of each. (4 marks)

Ans: Direct register-direct operands can hold the address of register. MOV X,AL Register Indirect:- effective address is the contents of a register. MOVE AL, [BX] indexed indirect addressing modes:- it is similar to indirect addressing mode . it holds the index of data such as array. MOV AL, ARR[SI]

(d) Ans:

Explain the process of Input/output using Interrupt 21h in 8086 microprocessor with the help of examples. (4 marks)

Each microprocessor provides instructions for I/O with the devices that are attached to it, e.g. the keyboard and screen.

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The 8086 provides the instructions in for input and out for output. These instructions are quite complicated to use, so we usually use the operating system to do I/O for us instead. In 8086 assembly language, we do not call operating system subprograms by name, instead, we use a software interrupt mechanism. An interrupt signals the processor to suspend its current activity (i.e. running your program) and to pass control to an interrupt service program The 8086 int instruction generates a software interrupt. It uses a single operand which is a number indicating which MS-DOS subprogram is to be invoked. For I/O and some other operations, the number used is 21h. Thus, the instruction int 21h transfers control to the operating system, to a subprogram that handles I/O operations. Example MOV DL, A MOV AH, 2H INT 21H ; DL = A ; CHARACTER OUTPUT SUBPROGRAM ; CALL MS-DOS OUTPUT CHARACTER

(e)

Write a program in 8086 assembly language that finds the total of an array of maximum 10 integer elements. You may assume that the array is stored in the memory and the last value in the array is -2000. The calculated result is stored in the location named sum. (8 Marks)
SEGMENT NUM1 DW 4,6,7,8,5,3,2,3,1,-2000 SUM DW 0 ENDS

Ans:
ARRAYS

ARRAYS CODE

SEGMENT ASSUME CS: CODE, DS: DATA START: MOV AX, DATA MOV DS, AX MOV SI 0 MOV CX, 9 AGAIN: MOV AL, NUM1 [SI] ADC BX, AL INC SI DEC CX JNZ AGAIN MOV SUM, BX FINISH: MOV AX, 4C00h INT 21h CODE ENDS END START

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(f)

Write a program in 8086 assembly language that passes two input parameters to a subroutine through a stack. The subroutine return a value 1 if the value of first parameter is greater than the second, otherwise returns 0. Make suitable assumptions, if any. (10 marks)
SEGMENT A DB 4 B DB 3 X DB 0

DATA

DATA ENDS STACK_SEG SEGMENT DW STACK_SEG ENDS CODE

STACK 2 DUP(0)

SEGMENT ASSUME CS: CODE, DS: DATA START: MOV AX, DATA MOV DS, AX MOV AL, A PUSH AX MOV AL, B PUSH AX CALL COMPARE POP AX MOV X, BX NOP CODE ENDS END START

COMPARE PROC NEAR PUSH ES ;NEED TO PRESERVE THESE PUSH SI ; REGISTERS PUSH AX LES SI, [BX+4];GET PTR TO 2ND VAR MOV AX, ES:[SI] ;GET ITS VALUE LES SI, [BX] ;GET PTR TO 1ST VAR CMP AX, ES:[SI] ;2ND->1ST, 1ST->AX JNE ZERO JA ONE POP AX POP SI POP ES ZERO: MOV BX,0

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ONE: MOV BX,1 RET COMPARE ENDP

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