1.

Introduction
For the past four decades, the semiconductor industry has distinguished itself by the rapid pace of improvements in its products. The propelling force behind this magnificent journey has been an ambition to adhere to Moores Law [1] . Which originally stated that the number of devices on a chip would double every year (The time frame was later modified to every two years, and subsequently averaged to every eighteen months). Building low power VLSI systems has been another significant performance goal because of the fast growing technology in mobile communication and computation, which mainly need some source of portable power supply. The advance in battery technology is not going as fast as the advances in electronic devices. There is a limited amount of power available for the mobile system. So designers are faced with more constraints; high speed, high throughput, less silicon area, and at the same time, consumes as minimal power as possible. The power-delay product metric relates the amount of energy spent during the realization of a determined task, and stands as more fair performance metric when comparing optimizations of a module designed and tested using different technologies, operating frequencies, and scenarios. Addition is one of the fundamental arithmetic operation, that is extensively many VLSI systems such as microprocessors and application specific DSP architectures. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation, ... etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal. Building low power VLSI systems has been another significant performance goal because of the fast growing technology in mobile communication and computation, which mainly need some source of portable power supply. The advance in battery technology is not going as fast as the advances in electronic devices. There is a limited amount of power available for the mobile system. So designers are faced with more constraints, high speed, high throughput, less silicon area, and at the same time, consumes as minimal power as possible. Mainly there are three major components of power consumption in CMOS circuits [2] Dynamic Power due to charging and discharging of the circuit capacitances during transistor switching. Short Circuit Power due to short circuit current flowing from power supply to ground when both p-network and n-network are ON, Static Power due to leakage current. The first component is the dominant one, it accounts for 85-90% of the total power consumption in a system.

The other two components are not negligible especially the second one since it accounts for about 10-15% of the total power consumption in some circuits. The total Power is given by the following equation

P i Vdd .Vswing .Cload . f . pi Vdd . Iisc Vdd .I leak

i

where Vdd is the power supply voltage, Vswing is the voltage swing of the output which is ideally equal to Vdd. is the output load capacitance at node i, f is the system clock frequency, pi is the switching activity at node i, Iisc is the short circuit current at node i, and 1leak is the leakage current. The summation is over all the nodes of the circuit. Reducing any of these components will end up with lower power consumption, although we are always interested in increasing f.

1.1Motivation
Low power consumption without compromising the speed is the key factor for any ASIC design.in all arithmetic circuits full-adder is a building block. If a full-adder can be designed such that its switching power and leakage power is low, good driving capability, with good speed with optimum number of transistors then we can design any energy efficient ASIC circuits.

2. Literature Survey
Many approaches have been proposed in literature in order to optimize the full-adder circuits with respective to power and some approaches only concentrated on full voltage swing at the output and some concentrated only on driving capabilities. In order to achieve these optimizations various logic styles have been proposed namely Standard CMOS[2] DCVS[4],CPL[5],SR-CPL[6],DPL[7] and Hybrid styles[8]. Each of above approaches have its own merits and demerits with respective to circuit size, power, leakages and so on. Some of research work have proposed alternative logic structures to minimize the number of transistors to implement the full-adders and all of these methods make use of individual transistors which are larger in size and there intermediate voltage swings are partial. Such as 14-T, NEW-14T[9],HPSC[10] fulladder circuits. So all these methods were compromised on leakage power and speed so these will not good for portable devices. In some of the old approaches they designed full-adder circuits such that first carry signal is generated and it will be used to generate the sum signal and they achieve power and speed main limitation of these approaches is not suitable for tree structured arithmetic logic structures.

3. Design Methodology
Proposed full-adder is examining by the full-adders truth table, it can be seen that sum signal is equal to the A xor B when C=0,and it is equal to A xnor B when C=1.Thus multiplexer can be used to obtain the value taking the C input as the selection signal and the carry will be Carry ( A B)C ( A B) A

C 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

Sum 0 1 1 0 1 0 0 1

Carry 0 0 0 1 0 1 1 1

Fig 1. Full-Adder truth table

A XOR/XNOR B

MUX C

Sum

MUX

Carry

Fig 2. Alternative logic scheme for designing full-adder cells. To generate the sum XOR and XNOR signals internally generated this block is implemented using a concept of parallelism and DPL logic style is used which leads high driving capability and complete voltage swings at internal nodes and this XOR and XNOR signal drive the carry multiplexer to generate the carry. And the maximum percentage of the circuit is designed powerless and ground less approach which leads to reduce the power consumption from the power lines.

B A A A B A B A B B B A A B A B C C A B A
A B A B A B

c
A B

A B

SUM

c
A B

C
CARRY

A
A B

B Fig 3. Proposed New Hybrid-CMOS Full-Adder logic structure

To generate the sum XOR and XNOR signals internally generated this block is implemented using a concept of parallelism and DPL logic style is used which leads high driving capability and complete voltage swings at internal nodes and this XOR and XNOR signal drive the carry multiplexer to generate the carry. And the maximum percentage of the circuit is designed powerless and ground less approach which leads to reduce the power consumption from the power lines. The capacitive load for the C input has been reduced, as it is connected only to some transistor gates and no longer to some drain or source terminals, where the diffusion capacitance is becoming very large for sub-micrometer technologies. Thus, the overall delay for larger modules where the C signal falls on the critical path can be reduced. All the multiplexers are designed with transmission gate logic style to drive the larger capacitive loads. The propagation delay for the Sum and carry outputs can be tuned up individually by adjusting the multiplexers gates. This is very good for where the skew between sum and carry. And for having well balanced propagation delays at the outputs to reduce the chance of glitches in cascaded applications.
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4. Simulation Environment
All the circuits are designed in cadence VIRTUOSO environment using GPDK 45nm technology. To simulate a real circuit environment input buffer is chosen such that there is a signal distortion as expected in an actual circuit. For PDP comparisons supply voltage is 1.1V at 200 MHz operating frequency was employed and operating temperature for circuit kept at 27oC.The default value of the length is 45nm is constant and width is varied up to 6um for proper transistor sizing. The used simulation test bench is shown in fig 4. For Accurate results all the input possible conditions are considered and for load capacitance we use high size of inverters (6um/4um) is used because on chip loads are high.

In A

3 2 3 2 3

3 A 2 3 B 2 3 C 2 Carry Sum Full-Adder

6 4 6 4

In B

In C 2

Fig 4. Test bed for simulating the full-adders under comparison.

5. Simulation results
In this project five full-adder circuits are compared namely HPSC, Hybrid, SR-CPL based full-adder[11],DPL based full-adder[11] and proposed full-adder the schematics were designed using GPDK 45nm technology. In order to have a fair comparison all the full adder circuits are operated at 200MHz. Simulation results show that only two full adder circuits suffering from glitch problems these are the HPSC and HYBRID to generate immediate signals the logic styles that have incomplete voltage swings at the internal nodes this leads to power consumption and delay. Considering the power consumption of the whole test bench the proposed full adder circuit saves 70% of the power compared to the HYBRID full adder and the speed has been improved to 14% and the energy is saved up to 75%.The best power delay product is achieved by which delay and power are decreased. The impotence of the simulation environment and the inclusions of the power components for the surrounding circuitry are evident as some realizations reported previously as low power cells have been shown to perform worse than other ones when considering the power consumption of the whole test bench. For a good designer we can eliminate the inverters at the inputs if the input i s fed from the registers.

Fig 5: input stimulus for a full-adder cell the first three are the inputs A, B and C and the remaining two are outputs which are sum and carry. Frequency of the inputs is 200MHz with a supply voltage of 1.1V.

66 64 62 Delay(pS) 60 58 56 54 52 50 Hybrid Hybrid HPSC HPSC Proposed-1 Proposed-2 New-Proposed New-Proposed Proposed-1 Proposed-2

Fig 6. Delay comparisons

7 6

Power(uW)

5 4 3 2 1 0 Hybrid HPSC Proposed-1 Proposed-2 New-Proposed

Full-Adder Type Fig 7. Power comparison

450 400 350 300 PDP E-18 250 200 150 100 50 0 Hybrid HPSC Proposed-1 Proposed-2 New-Proposed

Fig 8.Energy comparisons

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6. Conclusion
New Hybrid-CMOS full adder is proposed with an alternative logic structure .proposed full-adder is compared with five existing low power fulladders. Six transistors are reduced than the previous low power full[11] adder .Based on the observation the proposed full-adder has better driving capability, Due to its inherit Hybrid Nature provides full voltage swings (internal & output) Simulation Results Showing 75% Energy improvement, 70% Power savings, 14% Speed Improvements and 75% energy improvements. So it is recommended to use of new Hybrid-CMOS design style for the design of energyefficient circuits.

References
[1] G. E. Moore, cramming more components onto integrated circuits, Electronics Magazine,vol.38,pp.114-117,apr 1965. [2] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, A System Perspective. Reading, MA: Addison-Wesley, 1988. [3] C. Chang, J. Gu, and M. Zhang, A reviewof 0.18-mfull adder performances for tree structured arithmetic circuits, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 686695, Jun. 2005. [4] K. M. Chu and D. Pulfrey, A comparison of CMOScircuit techniques: Differential cascode voltage switch logic versus conventional logic, IEEE J. Solid-State Circuits, vol. SC-22, no. 4, pp. 528532, Aug. 1987. [5] K. Yano, K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, A 3.8 ns CMOS 16 x 16-b multiplier using complementary passtransistor logic, IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 388395, Apr. 1990. [6] R. Zimmerman and W. Fichtner, Low-power logic styles: CMOS versus passtransistor logic, IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 10791090, Jul. 1997. [7] M. Suzuki, M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, and Y. Nakagome, A 1.5 ns 32-b CMOS ALU in double pass-transistor logic, IEEE J. Solid-State Circuits, vol. 28, no. 11, pp. 11451150, Nov. 1993. [8] M. Zhang, J. Gu, and C. H. Chang, A novel hybrid pass logic with static CMOS output drive full-adder cell, in Proc. IEEE Int. Symp. Circuits Syst., May 2003, pp. 317320. [9] D. Radhakrishnan, Low-voltage low-power CMOS full adder, IEEE Proc. Circuits Devices Syst., vol. 148, no. 1, pp. 1924, Feb. 2001. [10] S. Goel, A. Kumar, and M. Bayoumi, Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 12, pp. 13091320, Dec. 2006. [11]Mariano ,M.L.Aranda,CMOS Full-adders for Energy efficient Arithmetic Applications,IEEE transactions on VLSI,2011.

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