N MOS Fabrication Process

By
Mahendra V
Dept. ECE
KL University

N-MOS Fabrication Process

Si-substrate

Fig. (1) Pure Si single crystal

------------------------------------------------------------------------------------------------Fig. (2) P-type impurity is lightly

doped

Faculty: Mahendra V, Dept. ECE

N-MOS Fabrication Process

(Oxidation)

------------------------------------------------

Thick SiO2
(1 m)

-------------------------------------------------Fig. (3) SiO2 Deposited over si surface

------------------------------------------------

Photoresist
Thick SiO2
(1 m)

-------------------------------------------------Fig. (4) Photoresist is deposited

over SiO2 layer
Faculty: Mahendra V, Dept. ECE

N-MOS Fabrication Process

Photolithography

UV Light

Mask-1

Photoresist

-------------------------------

Thick SiO2
(1 m)

----------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ---------------------------------Fig. (5) Photoresist layer is

exposed to UV Light through a
mask
Faculty: Mahendra V, Dept. ECE

Mask-1 is used to expose the SiO2

where S, D and G is to be formed.

N-MOS Fabrication Process

Etching

Polymerised
Photoresist

----------------------------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----------------------------------

Thick SiO2
(1 m)

Fig. (6) Developer removes unpolymerised photoresist. It

will cause no effect on Si surface

Faculty: Mahendra V, Dept. ECE

N-MOS Fabrication Process

Etching

-------------------------------

Thick SiO2
(1 m)

----------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----------------------------------

Fig. (7) Etching [HF acid is used] will remove SiO2 layer
which is in direct contact with etching solution

Faculty: Mahendra V, Dept. ECE

N-MOS Fabrication Process

Etching

-------------------------------

Thick SiO2
(1 m)

----------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----------------------------------

Fig. (7) unpolymerised photoresist is also etched away

[using H2SO4]

Faculty: Mahendra V, Dept. ECE

N-MOS Fabrication Process

Oxidation

Thin SiO2
(0.1 m)

-------------------------------

Thick SiO2
(1 m)

----------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----------------------------------

Fig. (8) A thin layer of SiO2 grown over the entire chip surface

Faculty: Mahendra V, Dept. ECE

N-MOS Fabrication Process

Oxidation

Polysilicon layer
(1 2 m)

----------------------------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----------------------------------

Thick SiO2
(1 m)

Thin SiO2
(0.1 m)

Fig. (9) A thin layer of polysilicon is grown over the entire chip
surface to form GATE

Faculty: Mahendra V, Dept. ECE

N-MOS Fabrication Process

Oxidation

Photoresist

Polysilicon
layer

----------------------------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----------------------------------

Thin SiO2
(0.1 m)
Thick SiO2
(1 m)

Fig. (10) A layer of photoresist is grown over polysilicon layer

Faculty: Mahendra V, Dept. ECE

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N-MOS Fabrication Process

Photolithography
UV Light

Mask-2

----------------------------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ---------------------------------Mask-2 is used to deposit

Polysilicon to form gate.
Fig. (11) Photoresist is exposed to UV Light

Faculty: Mahendra V, Dept. ECE

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N-MOS Fabrication Process

Etching

Polysilicon

Thin SiO2
(0.1 m)

-------------------------------

Thick SiO2
(1 m)

----------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----------------------------------

Fig. (12) Etching will remove that portion of Thin SiO2 which is
not exposed to UV light

Faculty: Mahendra V, Dept. ECE

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N-MOS Fabrication Process

Etching

Polysilicon used as GATE

(1 2 m)

Thin SiO2
(0.1 m)

-------------------------------

Thick SiO2
(1 m)

----------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----------------------------------

Fig. (13) Polymerised photoresist is also stripped away

Faculty: Mahendra V, Dept. ECE

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N-MOS Fabrication Process

Diffusion or Ion Implantation
GATE
SOURCE

DRAIN

Mask-3 is used to n+ diffusion

Thin SiO2
(0.1 m)

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -

Thick SiO2
(1 m)

- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -- - - - - - - - - - - - - n+
- - - - - - - -n+
---------------------------------------------

Fig. (14) n+ Doping to form SOURCE and DRAIN

Faculty: Mahendra V, Dept. ECE

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N-MOS Fabrication Process

Step - Oxidation

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -- - - - - - - - - - - - - n+
- - - - - - - -n+
---------------------------------------------

Thick SiO2
(1 m)

Thick SiO2
(1 m)

Fig. (15) A thick layer of SiO2 (1 m) is again grown.

Faculty: Mahendra V, Dept. ECE

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N-MOS Fabrication Process

Step - Photolithography

UV Light

Mask-3

Mask-4 is used to make contact cuts for S, D and G.

Photoresist

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -- - - - - - - - - - - - - n+
- - - - - - - -n+
---------------------------------------------

Thick SiO2
(1 m)

Thick SiO2
(1 m)

Fig. (16) Photoresist is grown over thick SiO2. Selected areas of the poly GATE and SOURCE and
DRAIN are exposed where contact cuts are to be made

Faculty: Mahendra V, Dept. ECE

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N-MOS Fabrication Process

Step - Etching

Mask-3

Photoresist

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -- - - - - - - - - - - - - n+
- - - - - - - -n+
---------------------------------------------

Thick SiO2
(1 m)

Thick SiO2
(1 m)

Fig. (17) The region of photoresist which is not exposed by UV light will become soft. This
unpolymerised photoresist and SiO2 below it are etched away.

Faculty: Mahendra V, Dept. ECE

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N-MOS Fabrication Process

Step - Etching

Mask-3

Photoresist

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -- - - - - - - - - - - - - n+
- - - - - - - -n+
---------------------------------------------

Thick SiO2
(1 m)

Thick SiO2
(1 m)

Fig. (18) The contact cuts are formed for S, D and G (hardened photoresist is stripped away).

Faculty: Mahendra V, Dept. ECE

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N-MOS Fabrication Process

Step - Metallization

Metal (1m)

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -- - - - - - - - - - - - - n+
- - - - - - - -n+
---------------------------------------------

Thick SiO2
(1 m)

Thick SiO2
(1 m)

Fig. (19) Metal (aluminium) is deposited over the surface of whole chip (1 m thickness).

Faculty: Mahendra V, Dept. ECE

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N-MOS Fabrication Process

Step - Oxidation
Photoresist

Metal (1m)

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -- - - - - - - - - - - - - n+
- - - - - - - -n+
---------------------------------------------

Thick SiO2
(1 m)

Thick SiO2
(1 m)

Fig. (20) Photoresist is deposited over the metal.

Faculty: Mahendra V, Dept. ECE

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N-MOS Fabrication Process

Step - Photolithography
UV Light

Mask-4

Photoresist
Metal (1m)

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -- - - - - - - - - - - - - n+
- - - - - - - -n+
---------------------------------------------

Thick SiO2
(1 m)

Thick SiO2
(1 m)

Mask-4 is used to deposit metal in contact cuts of S, D and G.

Fig. (21) UV Light is passed through Mask-4 (with a aim of removing all metal other than metal in
contact-cuts).

Faculty: Mahendra V, Dept. ECE

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N-MOS Fabrication Process

Step - Etching

Mask-4

Photoresist
Metal (1m)

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -- - - - - - - - - - - - - n+
- - - - - - - -n+
---------------------------------------------

Thick SiO2
(1 m)

Thick SiO2
(1 m)

Fig. (22) Photoresist and metal which is not exposed to UV light are etched away.

Faculty: Mahendra V, Dept. ECE

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N-MOS Fabrication Process

Step - Metallization
SOURCE

DRAIN

GATE

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -- - - - - - - - - - - - - n+
- - - - - - - -n+
---------------------------------------------

Fig. (23) Final n-MOS Transistor

Faculty: Mahendra V, Dept. ECE

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Basic Steps to be followed

1.
2.
3.
4.
5.
6.
7.
8.
9.

Formation of n-well regions

Define nMOS and pMOS active areas
Field & gate oxidation
Form & pattern polysilicon
P+ diffusion
N+ difusion
Contact cuts
Deposition & Pattern metalization
Over glass with cuts for bounding pads

Faculty: Mahendra V, Dept. ECE

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Points to Remember
Mask-1 is used to expose the SiO2 where S, D and G is to be formed.
Mask-2 is used to deposit Polysilicon to form gate.
Mask-3 is used to n+ diffusion
Mask-4 is used to make contact cuts for S, D and G.
Mask-5 is used to deposit metal in contact cuts of S, D and G.

Faculty: Mahendra V, Dept. ECE

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