C3PU GROUP

WHO ARE WE?

Ivan Sovi, leader

PROCESSOR DESIGN FOR RECONFIGURABLE PLATFORMS

Simon Cossart Luka Kova Filip Keri

CPU SCHEMATIC VIEW

SINGLE REGISTER
We want to have the ability to remember small amount of data really fast Category of sequential, synchronous circuitry We remember data D each time when the clock signal changes from 0 to 1, and put it in Q That way we are able to remember data really fast for one period of the clock (longer if the data D didnt change)

INPUT signals: D 16 bits of data we want to remember Clk controlling clock

OUTPUT signal: Q remembered data

SINGLE REGISTER
D data

IMPLEMENTATION

clock
Q data One period

Rising edge

TRI-REGISTER
We want to control a register with an electric signal When the enable signal is egal to 1 you are able to store and display data.

INPUT signals: D 16 bits of data we want to remember Clk controlling clock En Enable signal OUTPUT signal: Q remembered data

TRI-REGISTER
IMPLEMENTATION

TRI-REGISTER IMAGES

REGISTER ARRAY
Register array consists of many registers We use 8 registers Register array is same as RAM (Random Acess Memory)

INPUT signals: data 16 bits of data we want to remember Clk controlling clock Sel select en - enable
OUTPUT signal: Q remembered data

ALU(ARITHMETIC-LOGIC UNIT)

INPUT SIGNALS : A, B, Sel -A : 16 bits data input -B : also 16 bits data input -Sel : 4 bits control input OUTPUT signal: C C 16 bits of process data We want it to perform basic operation like AND, OR, + , - and NOT

ALU(ARITHMETIC-LOGIC UNIT)
IMAGES

Implemented circuit

SHIFTER
We want to perform operation on 16 bits of data Category of combinational circuitry The operation performed on data D depends on the data sel (select) We can have 2^3 different operation with 3-bit sel

INPUT signals: D 16 bits of data sel operation selection OUTPUT signal: Q data after the operation

SHIFTER
D data sel Q data

IMPLEMENTATION

COMPARATOR
Compare a and b in different ways

INPUT signals: a first operand data bus b second operand data bus sel selection of operations to be performed OUTPUT signal: y a op b

FINITE STATE MACHINES

Mathematical model of computation Abstract machine that can be in only one of the finite number of states The transition between the states is achieved by the triggering events we stay
in the state until the trigger event

0
Even number of 0s Odd number of 0s

Even or odd number of 0s? Sequence -> 01010

0 1 0 1 0

TRAFFIC LIGHT

FINITE STATE MACHINE

QUESTIONS?