Absolute Maximum Ratings (Note)

If MilitaryAerospace specified devices are required please contact the National Semiconductor Sales OfficeDistributors for availability and specifications Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range DM54LS b55C to a125C DM74LS 0C to a70C Storage Temperature Range b65C to a150C

DM54LS73ADM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

June 1989 Note The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the Electrical Characteristics table are not guaranteed at the absolute maximum ratings The Recommended Operating Conditions table will define the conditions for actual device operation

and K inputs is allowed to change while the clock is high or low without affecting the outputs as long as setup and hold This device contains two independent negative-edge-trigSymbolgered J-K Parameter DM54LS73A DM74LS73A times are Units not violated A low logic level on the clear input flip-flops with complementary outputs The J and Min Nom regardless Max will reset the outputs of the levels of the other K data is processed by the flip-flops on the falling Min edge ofNom Max clock Voltage pulse The clock triggering at a voltage VCC the Supply 45 occurs 5 55 475 5 525 inputs V level and is not directly related to the transition time of the VIH negative High Level Input Voltage 2 The data on the2J V going edge of the clock pulse VIL IOH IOL fCLK fCLK tW

Recommended Operating Conditions General Description

Connection Diagram High Level Output Current

Low Level Input Voltage

07
b04

08
b04

V mA mA MHz MHz ns

Low Level Output Current 4 Dual-In-Line Package Clock Frequency (Note 2) 0 30 Clock Frequency (Note 3) 0 25 20

8 0 0 25 30 25

Pulse Width Clock High 20 (Note 2) Preset Low 25 Clear Low 25

25 25 30 ns 30 20v ns

tW

Pulse Width Clock High 25 (Note 3) Preset Low 30 Clear Low 30

tSU tSU tH tH TA

Setup Time (Notes 1 and 2)

20v
TLF63721

Setup Time (Notes 1 and 3) 25v 25v ns Order Number DM54LS73AJ DM54LS73AW DM74LS73AM or DM74LS73AN Hold Time (Notes 1 and 0v 0v ns See NS 2) Package Number J14A M14A N14A or W14B Hold Time (Notes 1 and 3) 5v Free Air Operating Temperature b55 5v 125 0 70 C ns

Note 1 The symbol ( ) indicates the falling edge of the clock pulse is used for reference Note 2 CL e 15 pF RL e 2 kX TA e 25C and VCC e 5V Note 3 CL e 50 pF RL e 2 kX TA e 25C and VCC e 5V

v Table Function

Inputs J X L H L H X

Outputs Q L
00 Q H

CLR L H H H H H
H e High Logic Level L e Low Logic Level X e Either Low or High Logic Level

CLK X

K X L L H H X

Q H Q L

v v v v
H

H Toggle Q0 Q

e Negative going edge of pulse Q0 e The output logic level before the indicated input conditions were established Toggle e Each output changes to the complement of its previous level on each falling edge of the clock pulse

C1995 National Semiconductor Corporation

TLF6372

RRD-B30M105Printed in U S A

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol VI VOH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Conditions VCC e Min II e b18 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIL e Max VIH e Min DM54 DM74 DM54 DM74 25 27 Min Typ Max
b15

Units V V

(Note 1)

34 34 025 035 04 05 025 03 Clock mA

VOL

V 04

IOL e 4 mA VCC e Min II Input Current Max VCC e Max Input Voltage VI e 7V JK Clear

DM74 01

04 mA 80 mA
b08

IIH

High Level Input Current

VCC e Max VI e 27V

JK Clear

20 60 Clock

IIL

Low Level Input Current

VCC e Max VI e 04V

JK Clear

b04 b08

Clock IOS ICC Short Circuit VCC e Max Output Current (Note 2) Supply Current DM54
b20 DM74 b100 b20

mA
b100

VCC e Max (Note 3)

mA

Switching Characteristics at VCC e 5V and TA e 25C (See Section 1 for Test Waveforms and Output Load)
Symbol Parameter To (Output) From (Input) CL e 15 pF RL e 2 kX CL e 50 pF Units Min fMAX tPHL tPLH tPLH tPHL Maximum Clock Frequency Propagation Delay Time Clear High to Low Level Output Propagation Delay Time Clear Low to High Level Output 30 20 to Q 20 to Q 20 20 24 28 ns ns 24 ns 25 MHz 28 ns Max Min Max

Propagation Delay Time Clock to Low to High Level Output Q or Q Propagation Delay Time Clock to High to Low Level Output Q or Q

Note 1 All typicals are at VCC e 5V TA e 25C Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second For devices with feedback from the outputs where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where V O e 225V and 2125V for DM54 and DM74 series respectively with the minimum and maximum limits reduced by one half from their stated values This is very useful when using automatic test equipment Note 3 With all outputs open ICC is measured with the Q and Q outputs high in turn At the time of measurement the clock is grounded

Physical Dimensions inches (millimeters)

14-Lead Ceramic Dual-In-Line Package (J) Order Number DM54LS73AJ NS Package Number J14A

Physical Dimensions inches (millimeters) (Continued)

14-Lead Small Outline Molded Package (M) Order Number DM74LS73AM NS Package Number M14A

14-Lead Molded Dual-In-Line Package (N) Order Number DM74LS73AN NS Package Number N14A

Physical Dimensions inches (millimeters) (Continued)

14-Lead Ceramic Flat Package (W) Order Number DM54LS73AW NS Package Number W14B

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