Modeling and Design of A Neutral Point Voltage Regulator For A Three Level Diode Clamped Inverter Using Multiple Carrier Modulation

Modeling and Design of a Neutral Point Voltage Regulator for a Three Level
Diode Clamped Inverter Using Multiple Carrier Modulation

Ashish Bendre Giri Venkataramanan Vijay Srinivasan Don Rosene
University of Wisconsin-Madison
1415 Engineering Drive
Madison WI 53706
608 262 4479
bendre@cae.wisc.edu
SoftSwitching Technologies
8155 Forsythia Street
Middleton WI 53562
608 662 7392
drosene@softswitch.com

Keywords: Multilevel converters, Converter control, Modeling, Harmonics, Modulation strategy
Abstract
This paper presents the design and implementation of a novel neutral point voltage regulator for a
three level diode clamped multi level inverter, which uses a multiple carrier sine triangle modulator in
conjunction with a closed loop controller for neutral point regulation. Redundant state choices are
controlled via a continuous voltage offset that controls the dc current injection into the midpoint of the dc
bus. Small signal dynamic models are developed for closed loop regulators with this voltage offset as the
control variable. Besides maintaining dc bus voltage balance, a significant reduction is seen in the voltage
distortion at the neutral point when the regulator is used and this leads to a definitive reduction in the
required dc bus capacitance. Analytical, computer simulation and experimental results verifying the
approach are presented in the paper.
I. Introduction
Three level or neutral point clamped converters are seeing widespread application in large
industrial drive systems [1,2]. Several carrier-based and space vector based strategies have been proposed
for the modulation of these converters [3,4]. However, these strategies by themselves only concern
themselves with output voltage waveform synthesis and require a post-facto algorithm to manage the dc
bus power balance among the three dc level. In general, they result in significant third harmonic injection
into the neutral point of the converter, which causes an increase in the required dc link capacitance of the
converter. While a number of open loop control strategies have been proposed for the reduction of the
harmonic content [5,6], a closed loop control strategy, which reduces the harmonic content as well as
regulating the neutral point from parasitic asymmetries like device voltage drops is presented in this
paper. The closed loop regulator is based on controlling the neutral point current injection as a function of
a control input that corrects the existing imbalance. Small signal transfer function models are developed
and used to design the regulator. A detailed simulation of a three level inverter shows the benefits of
using the closed loop regulator for multiple carrier modulation methods and these results are verified
using a hardware prototype. Extensive modeling has been carried out for the switching frequency effects
of various modulators previously [7,8]. This paper focuses on design of closed loop compensators for
multiple carrier modulators, and loop stability is analyzed for low frequency effects. The partitioning of
three level inverter controller functions into output voltage synthesis and dc bus balance is described in
Section II. Section III presents the relationships between the neutral point current injection and the
Modeling and Design of a Neutral Point Voltage Regulator for a Three Level Diode Clamped Inverter Using Multiple Carrier Modulation BENDRE Ashish
EPE 2003 - Toulouse ISBN : 90-75815-07-7 P.1
voltage offset provided to the three references. In Section IV, the small signal model for the controller is
derived. Simulation results verifying the performance of the regulator and hardware results from a
prototype three level converter are included in Section V, followed by conclusions.
II. Closed Loop Neutral Point Regulator
The proposed control approach for regulating the neutral point voltage of a three level neutral
point clamped inverter is based on the concept of 'sharing function' introduced in [6]. A simplified
schematic of the three level neutral point clamped inverter is illustrated in Figure 1(a). A representation of
the carrier waveforms and the modulating signal for a given phase is illustrated in Figure 1(b). The
sharing function can be implemented as simply a voltage offset (V
off
) that adds to each of the three
sinusoidal phase references. The average value of the offset is nominally zero, representing equal power
drawn from the two dc buses. However, by perturbing the offset voltage, the relative distribution of power
drawn from the dc buses may be varied. This is the basis of the proposed control approach.
V
0
V
-1
V
1
I
-1
I
1
I
0
V
a
I
a
V
b
I
b
V
c
I
c

(a) (b)
Figure 1: (a) Simplified schematic of a three level converter (b) Representative illustration of three phase references,
triangular carriers and injected offset voltage for three phase three level converter
Power Source
Diode Clamped
Switching Matrix
DC Stack
[H(t)]
[Vs]
[Is]
Plant
[Vp]
[Ip]
Vpa
Vpb
Vpc
[Vo]
[Vs]
[Vo]
[m] [sf]
Stack balance
regulator
Output Voltage
Regulator
[H(t)]
Throw
Switching
function
generator
|V
ref
|

Figure 2: Multi level diode clamped inverter system controller block diagram
Figure 2 shows a controller block diagram for a stacked multi level inverter system where the
major components of the system can be identified. The switching matrix H(t), defines the input-output
relationships between the various voltage levels of the dc stack to the three phase currents. The load is
modeled as resistive element in series with a filter inductor that yields sinusoidal output currents. The
output voltages V
o
(t), and the stack voltages V
s
(t) are the feedback signals to the controller. The controller
functions are partitioned into stack voltage balancing functions and output regulation. The output voltage
regulator accepts output voltage reference magnitude V
ref
and phase angle and produces the three-phase
pole voltage commands m(t). Although the development here features an output voltage regulator, the
neutral point regulation algorithm may be implemented with motor drives with various open or closed
loop regulation strategies. The dc stack balance regulator generates an offset voltage that is added to the
reference waveforms of the pulse width modulator. Together, these are used to compute the individual
elements of the switching matrix H(t), which directly relate to the switch gating signals of the converter,
as described in detail in [6]. The reciprocal properties of the switching matrix H(t) of the multi level
converter connect the pole voltages and pole currents to the stack voltages and stack currents, which may
be mathematically expressed as
p
T
s
s p
I H ) ( I
V H ) ( V
(t) t
(t) t
=
=
(1)
The design of the regulator follows two sequential steps. First, the input-output relationship
between the V
off
and the dc stack current injection as a function of operating conditions such as
modulation level, output current and power factor is determined. This non-linear function may be
linearized at the steady state operating condition and used for developing a controller for the stack
voltages.
III. Modeling dc stack current injection for three level converters
If effects at the switching frequency are ignored, averaging the injection over the repetition
interval i.e. the fundamental period of the reference waveforms, time domain integration [6] can be
utilized to replace the switching functions elements h
ij
of the matrix H in equation (1) by their averaged
counterparts m
ij
.
T
ij
T
1
) ( m dt (t) h
ij
(2)
By integrating these averaged stack currents over a fundamental period, the individual cycle average for
the top, middle and bottom stack currents can be obtained.
( )dt t I t m t I t m t I t m I
c ic b ib a ia
AVG
i

+ +
=
2
0
) ( ) ( ) ( ) ( ) ( ) (
2
1
(3)
The integral equation (3) contains three symmetric terms. If a process for evaluating one term is
demonstrated, it can then be expanded to include the contributions of the other two terms in the
expression. For multiple carrier modulation, it can be shown that [6]
( )
( ) ( )
( )
( ) ( ) j
ref
i n / i n
j
ref
j
ref
i n / i n
j
ref
ij
(t)] [V W
(t)] [V i n
(t)] [V W
i n (t)] [V
(t) m
1 2 1 2
3 2 1 2
2
1 2
2
3 2
+

+
+

=
(4)
where,
1 2 1 2 if 1
1 2
1 2
< < + =

+
i n (t) V i n (t) W
ref
a
a
i n
i n

otherwise 0
1 2
1 2
=

+
(t) W
a
i n
i n
(5)

The reference sinusoids are expressed as follows

( ) [t] m n (t) V
ref
a
cos 1 =
(6)
with m being the modulation index. Equation (5) establishes gating or window functions that assign either
an algebraic combination of the reference to the individual entries m
ij
or sets it to zero. Thus, (4) is of the
form
2 2 1 1 ia
] [ ] [ ] [ ] [ ) ( m Window Sinusoid Window Sinusoid t + =
(7)
When the product of this throw function with the phase current is integrated, the window functions
provide the limits of the integral. The contribution to the stack injection at level i from phase a can be
expressed with simplification for a three level converter:

( )
( )
( ) ( )
( )
|
|
.
|
\
|

=

= =

dt t I (t)] [V
i n (t)] [V
dt (t)] [V W
i n (t)] [V
dt t I t m I
t
t
a a
ref a
ref
a
ref
i n / i n
a
ref
a ia
AVG
i
a
2
1
'
'
3
2
0
3 2 1 2
3
2
0
) (
2
3 2
3
2
1
2
3 2
3
2
1
) ( ) (
3
2
1

(8)
t
1
, t
2
are limits on the integral established by the interval when the corresponding window function is
non zero. Similar equations can be written for the contribution to the three levels of the stack current from
the other two phases in (3) and an expression for the total average can be written and evaluated.
The neutral point regulator adds an offset term to all three references, which influences the
window functions and hence the limits on the integrals in (8). If the references are balanced sinusoids,
these limits will correspond to fixed angles, however when the offset is added to the references, these
limits will be a function of both the reference sinusoid as well as the offset term. If the output currents are
assumed to be sinusoidal with one per unit amplitude, the average current injection into the midpoint of
the stack can be computed as a function of the modulation index m, the power factor , and the offset
voltage as follows:
( ) ( ) | |
cos sin 2 cos

3
0
m V m I
off
AVG
+ =
(9)
where, ]
m
V
[
off
1
cos
2

= .
IV. Regulator Design
The multi level inverter controller model developed in Section II can be applied to a three level converter
as shown in Figure 3.
Kp
V
off
V
mid
*
V
mid
f
Multiple
carrier
modulator
+
-
Neutral Point
Compensator
m
From
outer
loops
V
t
V
b
+
+
-
-
I
Ct
I
Cb
V
DC
+
-
I
1
I
0
I
-1 T
h
r
e
e

L
e
v
e
l

C
o
n
v
e
r
t
e
r
I
a
I
b
I
c

Figure 3: Block diagram of neutral point regulator using control offset voltage.
From the equivalent circuit in Figure 3, the dynamics of the voltage imbalance V
m
(=V
t
-V
b
) may
be expressed as
( )
AVG
AVG
m
I
C dt
dV
0
1
= (10)
where
( )
off
AVG
V m f I , ,
0
= (11)
as described in (9). The small signal behavior of this system with respect to the control input being the
sharing function may be characterized as follows.
off
off
off
AVG
m
V
V
V m f
dt
V d
C
~
) , , (
~
=

(12)
where,
( )
(
(
(
(
(
(
2
2
2
2 2
0
1
3
cos 6
m
V
m
V m
V
I
off
off
off
AVG
(13)
From (12) and (13), it is clear from the small signal dynamics of the neutral point voltage are represented
by an integrator whose gain depends on the partial derivatives expressed by (13) and the offset voltage.
Thus, the system will have zero steady state error dynamics, using only a proportional controller with gain
K
p
as shown in Figure 4. It is seen that the forward gain is dependent upon the magnitude and phase of the
reference vector, and the sign is dependent on the power factor. Thus, a priori knowledge of the power
delivery mode (motoring or regenerating) is required to design a stable compensator. The closed loop
transfer function between the command voltage and actual imbalance may be expressed as
off
V
f
p
m
f
m
K
s
s
V
V
+
=
1
1
) (
*
(14)
The closed loop system transfer function is that of a low pass filter with a bandwidth controlled by the
gain K
p
. Clearly, the bandwidth of the neutral point regulator can be improved by increasing the
proportional gain of the compensator. If the current phase angle is known, the compensator gain can be
dynamically scheduled to compensate for the variations in the system forward gain, thus ensuring a
uniform bandwidth for various operating points.

Kp
Voff
V
m
*
V
m
f
1
--
s
f(m,,Voff)
------------
C (Voff)
-
+ ~

Figure 4: Operating point model of the neutral point compensator.
V. Simulation and hardware results
A MATLAB Simulink
[9] model of a three level converter using multiple carrier modulation was
developed and operated in inverter mode. The operating parameters are shown in Table 1. Extensive
simulations were conducted to verify the performance of the regulator and the inverter system at a wide
variety of operating conditions. Selected waveforms from the computer simulation are illustrated in
Figure 5. Figure 5 (a) shows the upper and lower bus voltages and the zero neutral point injection
respectively, without a neutral point regulator. Figure 5 (b) shows the corresponding dc bus stack
waveforms with the proposed closed loop neutral point voltage regulator. The superior performance of the
system using the closed loop neutral point regulator is readily evident from the figure.

Table 1: Parameters for prototype three level inverter system
Parameter Value
Load Inductance
Load Resistance
DC Link Voltage
Output current
DC bus capacitance
Switching frequency
Modulation level
12mH
25
400 V
5 A
90 F
5 kHz
0.75

(a) Upper link voltage and NP current without regulation (b) Upper link voltage and NP current with regulation
Figure 5: Simulation waveforms of three level inverter showing effects of closed loop neutral point regulation.
A hardware prototype was built to verify the analysis and simulation results obtained using the
closed loop neutral point regulator. The prototype used nine dual IGBT devices and unlytic capacitors
interconnected with laminated bus planes to create a three phase three level inverter power platform.
The control algorithm has been implemented on a general-purpose real time control prototyping
platform. This platform is based on a TI TMS320C31 Digital Signal Processor and a Xilinx Spartan series
Field Programmable Gate Array for software and logic-based algorithm implementation. DSP code can
execute off 128K-words of zero-wait state decoding on-board SRAM. Data acquisition and monitoring is
facilitated by multiple high-speed A/D and D/A converters, which interface to the DSP via device
communication and interrupt logic implemented on the FPGA. Additional peripherals include a Field
Programmable Analog Array (FPAA) and its supporting circuits to facilitate re-configurable analog signal
conditioning implementation, PWM guarantee circuits that can insure complementary and dead-time
compliant switching control signals, and a 16-bit hexadecimal display useful for monitoring parameters
like DSP state-machine and fault status. The real-time PC-host interface to the DSP for code download
and debug is based on the TI TMS320C31 DSK evaluation platform. A simplified block diagram of this
controller is shown in Figure 6. The DSP was used to synthesize the reference waveforms and to
implement the neutral point voltage regulator. PWM control generation, dead-time restriction and
protection functions are implemented on the FPGA. High power signal scaling and conditioning have
been implemented on a separate sensor-board that interfaces to the control prototyping platform.
Interface
SRAM
Analog feedback from
Sensor Board
Select
Switches
FPAA subsystem
(Not used for this
application)
DSP
FPGA
subsystem
D/A converters
A/D converters
PWM guarantee
circuits, connectors,
fault inputs
Display
Real Time
PC
Interface
PC parallel
port
Gate Drive &
Sensor Board
Analog Monitoring

Figure 6: Block diagram of Control Prototyping Platform
The hardware prototype is shown in Figure 7 and key operating waveforms i.e. Pole A-Pole C voltage and
load line-line voltage are shown in Figure 8.

Figure 7: Hardware prototype Figure 8: A-C Pole-Pole voltage (Ch 4) and load line-
line voltage (Ch 3)
Figure 9 (a) and (b) show the measured upper dc bus waveform (ac coupled) along with the offset
command with and without the closed loop neutral point voltage regulator. Another indication of the
improvement obtained due to the regulator can be seen in Figure 10 where the phase current and the
filtered neutral point currents with and without the closed loop method are shown. Finally, Figure 11
shows the measured normalized spectrum of the neutral point injection, underlining the attenuation of the
third harmonic. The loop gain of the neutral point regulator shown in Figure 4 was measured with the
loop operating using a Venable closed loop analyzer [10]. The predicted results from the small signal
model show excellent match with the actual measurements as seen in Figure 12.

Figure 9 (a) Upper dc bus waveform (ac coupled) no
regulation
Figure 9 (b) Upper dc bus waveform (ac coupled) with
regulation

Figure 10 (a) Phase current (Ch 2) and the filtered
neutral point currents (Ch A) no regulation
Figure 10 (b) Phase current (Ch 2) and the filtered
neutral point currents (Ch A) no regulation

Figure 11 (a) Measured spectrum of neutral point current
without regulation
Figure 11 (b) Measured spectrum of neutral point
current with regulation

Figure 12 (a) Predicted NP regulator loop gain Figure 12 (b) Measured NP regulator loop gain
VI. Conclusions
This paper has presented a neutral point voltage regulator for a three level diode clamped multi level
converter, which uses a multiple carrier modulator in conjunction with a voltage offset based NP balance
controller. This combined control approach does not compromise the output voltage synthesis function
while maintaining tight regulation of the neutral point voltage even with a small dc link capacitance. A
voltage offset added to all three phase references is used as a control handle to vary the ratio of
distribution of duty cycles of redundant. Closed form expressions are presented for the neutral point
current injection as a function of the modulation index, the power factor and the offset voltage. By
analyzing small signal models for the neutral point voltage developed using these closed form
expressions, a closed loop neutral point compensator has been designed that provides excellent
performance and stability. A detailed computer simulation of a three level inverter with very modest dc
bus capacitance is implemented in MATLAB-Simulink and the neutral point voltage waveforms have
been presented. Measured waveforms from a three level hardware prototype show very close correlation
to analytic and simulation results. Very close match is seen between predicted and measured loop gains
for the neutral point compensator. A significant improvement is seen in the voltage distortion at the
neutral point when the regulator is used and this leads to a definitive reduction in the required dc bus
capacitance. The proposed strategy has been extended to space vector PWM strategies producing
effective neutral point regulators and these results will be presented in a future publication. The novel
concept of controlling the neutral point injection via a continuous voltage offset, and then developing
small signal models for closed loop regulators with this sharing function as the control variable, can also
be applied to regulate other system quantities. Detailed analytical development and experimental results
verifying the performance have been presented in the paper.
Support for this project from the Wisconsin Electric Machines and Power Electronics Consortium
(WEMPEC), DRS Power and Control Technologies and the Office of Naval Research through grant
N00014-01-1-0623 is gratefully acknowledged. This work also used shared facilities provided by the
ERC Program of the National Science Foundation under Award Number EEC-9731677 to the Center for
Power Electronics Systems (CPES) at the University of Wisconsin-Madison.
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Modeling and Design of A Neutral Point Voltage Regulator For A Three Level Diode Clamped Inverter Using Multiple Carrier Modulation

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