PESIT Project Proposal Title: COMPARISON OF EXISTING AND PROPOSED 1-BIT FULL ADDER CIRCUTES, USING CADENCE VIRTUOSO

ENVIRONMENT Date:12/10/13

Project Title
COMPARISON OF EXISTING AND PROPOSED 1-BIT FULL ADDER CIRCUTS, USING CADENCE VIRTUOSO ENVIRONMENT

TABLE OF CONTENTS
1 GENERAL INFORMATION............................................................................................................................ 3 2 REQUIREMENTS AND SOLUTIONS............................................................................................................ 3 3 PROJECT MANAGEMENT ASPECTS.......................................................................................................... 6 4 RISK EVALUATION....................................................................................................................................... 7 5 FUTURE ENHANCEMENTS.......................................................................................................................... 7 6 REFERENCES............................................................................................................................................... 7

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1.1

GENERAL INFORMATION
Objective

In this project, I will collect all the Existing Full Adder circuits (with 28 Transistors to a minimum of 6 Transistor Count) from various International Journal papers, and design them and compare the same in terms of various parameters like Power, Delay, Transistor count (Area), etc., in Cadence Virtuoso Environment and then conclude the project with a very good details, that helps the designer to choose the best design that suites for the particular parameter.
1.2 Introduction

ADDITION is one of the fundamental arithmetic operations. It is used extensively in many VLSI systems such as application-specific DSP architectures and microprocessors. In addition to its main task, which is adding binary numbers, it is the nucleus of many other useful operations such as subtraction, Multiplication, division, addresses calculation, etc. In most of these systems the adder is part of the critical path that determines the overall performance of the system. That is why enhancing the performance of the 1-bit full-adder cell (the building block of the binary adder) is a significant goal. The choice of logic style to design digital circuits strongly influences the circuit performance. The delay time depends on the size of transistors, the number of transistors per stack, the parasitic capacitance including intrinsic capacitance and capacitance due to intracell and intercell routing, and the logic depth (i.e., number of logic gates in the critical path). The dynamic power consumption depends on the switching activity and the number and size of transistors. Among other things, the die area depends on the number and size of transistors and routing complexity.
1.3 ProjectResult

The circuits are designed in a Cadence Virtuoso Environment using 45nm Technology GPDK Tool Kit, with a voltage supply of 1.2V, and Threshold Voltage (Vth) of 0.9v and compared with each other and Tabulate the result. The Comparison is done in terms of Number of Transistors, Delay (Sum and Carry), as well as Power Consumption. 2 REQUIREMENTS AND SOLUTIONS

2.1

MainRequirements/Features

Cadence Virtuoso Environment using 45nm Technology GPDK Tool Kit, with a voltage supply of 1.2V, and Threshold Voltage (Vth) of 0.9v.
2.2 Descriptionof the Project

existing full adder circuits The Full Adder circuit is an important component in applications such as Digital Signal Processing (DSP) architecture, microprocessor, and microcontroller and data processing units. In recent years, several variants of different logic styles have been proposed to implement Full Adder cells. Many papers have been published regarding the optimization of low-power full adders, trying different options for the logic style. So in this chapter the brief discussion of the various full adder

circuits, starting with the most conventional 28 transistor full adder and then gradually studied full adders consisting of as less as 6 transistors has been discussed.

Details of each of the Existing Full Adder Circuits

Now the various Existing Full adder design circuits are been explained with detailed details of the paper from which it has been collected, and its other information. A 28 TRANSISTOR CMOS CONVENTIONAL FULL ADDER

Figure a: 28T CONVENTIONAL FULL ADDER the conventional CMOS adder cell using 28 transistors based on standard CMOS topology which is as shown in above figure had been discussed. And there it was described that, due to high number of transistors, its power consumption was high, and also the large PMOS transistor in pull up network resulted in high input capacitances, which caused high delay and dynamic power. And this adder was based on regular CMOS structure (pull-up and pull-down network). So the full adder with 28 transistors was presented in that paper and we have chosen and have taken the same and has been compared it with other circuits and it is as shown in Figure 4a.

A 26 TRANSISTOR FULL ADDER

Figure b: 26T FULL ADDER In the paper 2, they have proposed two new full adder designs by combining common digital gates and majority functions. They have compared the performance of the better one with six other full adders. So the full adder with 26 transistors was presented in that paper and we have chosen and have taken the same and has been compared it with other circuits and it is as shown in Figure 4b.

A 6 TRANSISTOR FULL ADDER

Figure c: 6T FULL ADDER In the paper 3, the design of an adder circuit based on majority function is proposed. The adder comprises of only six MOS transistors. To make the design to be used invariably in the system with least nano device dimensions, some modifications have been done in the existing adder design. So the full adder with 6 transistors was presented in that paper and we have chosen and have taken the same and has been compared it with other circuits and it is as shown in Figure 4c. 2.3 IMPLEMENTATION METHOD: THE VARIOUS DESIGN STEPS Firstly a schematic view of the circuit is created using the Cadence Composer Schematic Editor. Alternatively, a text netlist input can be employed. Then; the circuit is simulated using the Cadence Affirma analog simulation environment. Different simulators can be employed, some sold with the Cadence software (e.g., Spectre) some from other vendors (e.g., HSPICE) if they are installed and licensed. Once circuit specifications are fulfilled in simulation, the circuit layout is create on the Virtuoso Layout Editor. The resulting layout must verify some geometric rules dependent on the technology (design rules). For enforcing it, a Design Rule Check (DRC) is performed. Then, the layout should be compared to the circuit schematic to ensure that the intended functionality is implemented. This can be done with a Layout Versus Schematic (LVS) check. All these verification tools are included in the Diva software in Cadence (more power ful Cadence tools can also be available, like Dracula, or Assura in deep submicron technologies). Finally, a netlist including all layouts parasitic should be extracted, and a final simulation of this netlist should be made. This is called a Post Layout simulation, and is performed with the same Cadence simulation tools. Once verified the layout functionality, the final layoutis converted to a certain standard file format depending on the foundry (GDSII, CIF, etc.) using the Cadence conversion tools. The Summary of the design steps is again explained with a high speed current mode dynamic latched comparator as follows.

Step 1: Invoking Cadence Tool Step 2: Create Library Step 3: Create Schematic Step 3.1: Placing the Instances Step: 3.2 Adding the I/O Pins Step: 3.3 Adding Wires Step 4: Create Test Circute Step 4.1: Create Symbol Step 5:simulation

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3.1

PROJECT MANAGEMENT ASPECTS

Hardware,SoftwareRequirements

Cadence Virtuoso custom design platform L

3.2 TargetDates

Stages S1

Target Date 12/10/13

Deliverables Project proposal and start of the project

Comment Synopsis approval, project plan and Start project Review requirements , design Release and hand-over of project deliverables

S2 S3

3.3

StudentsDetails

Students Santhosh Kumar S A

Guide Internal: External:

RISK EVALUATION
Availability of cadence tool

FUTURE ENHANCEMENTS 1 We can improve the performance of each of these designed 1-bit full adder blocks by varying their W/L ratios or by adding some of the passive elements like Resistors, Capacitors, etc. Using the designed 1-bit full adder blocks, we can design the 2-bit, 4-bit, 8-bit, 16-bit, 32-bit, 64-bit Adder/Subtractor circuits and so on. We can even design and compare these designs in all possible Nanometer technologies like 180nm, 90nm, 65nm, 32nm, 22nm, and so on. We can replace the full adder blocks of any previous application projects, with our designed full adder circuit blocks, that can do the same function as that is done by the old full adder circuits, to improve the performance factors like Area, Delay, or Power consumption, etc.

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REFERENCES 1. Comparative Analysis of Different Types of Full Adder Circuits.: M.B. Damle, Dr. S.S Limaye and M.G. Sonwani. 2. Study of Existing Full Adders and To Design a LPFA (Low Power Full Adder).: Pardeep Kumar, Susmita Mishra and Amrita Singh.