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Code No: C6106, C0608, C7702, C6802, C5702 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD M.Tech I Semester Examinations October/November-2011 CPLD & FPGA ARCHITECTURES AND APPLICATIONS (COMMON TO COMMUNICATION SYSTEMS, DIGITAL SYSTEMS & COMPUTER ELECTRONICS, EMBEDDED SYSTEMS & VLSI DESIGN, VLSI & EMBEDDED SYSTEMS, VLSI SYSTEM DESIGN) Time: 3hours Max.Marks:60 Answer any five questions All questions carry equal marks ---

R09

1.a) b) 2. 3.a) b) 4. 5. 6. 7. 8.

Explain the Max 5000/7000 series architecture. Explain Pac with an example. Explain lattice plats architecture 3000 series. Explain the design aspects of AXC4000 FPGA. Explain the design flow for FPGA.

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Explain one-hot state machine with an example.

Explain the extended petrinets for parallel controller.

Explain the front end design tools for fpgas and asics. Explain the multiplexer design.

Write short notes on the following. i. Speed performance of actel ii. Speed performance in system programmability iii. Asic design flow.

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