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Current status and scope of gallium nitride-based vertical transistors for high-power electronics application

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IOP PUBLISHING Semicond. Sci. Technol. 28 (2013) 074014 (8pp)

SEMICONDUCTOR SCIENCE AND TECHNOLOGY

doi:10.1088/0268-1242/28/7/074014

INVITED REVIEW

Current status and scope of gallium nitride-based vertical transistors for high-power electronics application
Srabanti Chowdhury 1 , Brian L Swenson 2 , Man Hoi Wong 3 and Umesh K Mishra 4
1 Department of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ 85287, USA 2 Transphorm Inc., 115 Castilian Drive, Goleta, CA 93117, USA 3 National Institute of Information and Communications Technology, 4-2-1 Nukui-kitamachi, Koganei, Tokyo 184-8795, Japan 4 Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA

E-mail: srabanti.ucsb@gmail.com

Received 2 January 2013, in nal form 24 March 2013 Published 21 June 2013 Online at stacks.iop.org/SST/28/074014 Abstract Gallium nitride (GaN) is becoming the material of choice for power electronics to enable the roadmap of increasing power density by simultaneously enabling high-power conversion efciency and reduced form factor. This is because the low switching losses of GaN enable high-frequency operation which reduces bulky passive components with negligible change in efciency. Commercialization of GaN-on-Si materials for power electronics has led to the entry of GaN devices into the medium-power market since the performance-over-cost of even rst-generation products looks very attractive compared to todays mature Si-based solutions. On the other hand, the high-power market still remains unaddressed by lateral GaN devices. The current and voltage demand for high-power conversion application makes the chip area in a lateral topology so large that it becomes difcult to manufacture. Vertical GaN devices would play a big role alongside silicon carbide (SiC) to address the high-power conversion needs. In this paper vertical GaN devices are discussed with emphasis on current aperture vertical electron transistors (CAVETs) which have shown promising performance. The fabrication-related challenges and the future possibilities enabled by the availability of good-quality, cost-competitive bulk GaN material are also evaluated for CAVETs. (Some gures may appear in colour only in the online journal)

1. Introduction and background

Power conversion is ubiquitous in our everyday lives. It plays a role from charging our cellphone to powering our home. Power conversion could mean stepping up or stepping down from one
This work was done at Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA. 0268-1242/13/074014+08$33.00

voltage level to another (boost or buck) or a conversion from dc to an ac voltage (inverter) or from 1-phase to 3-phase (phase converter), or just isolating from the supply line (power factor correction). A switch can be regarded as the heart of any power conversion unit. An ideal switch is one which offers an innite resistance to current in its OFF-state and zero resistance when in its ON-state. In solid state power electronics application a switch is realized by a transistor in its class D operation. With
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Semicond. Sci. Technol. 28 (2013) 074014

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Figure 1. Entire range of power applications that can be addressed with GaN (based on Yole Development report [1]).

Figure 3. Total device loss versus frequency of operation using bulk material properties of Si, GaN and SiC (plot generated based on switching FOM [2]).

Figure 2. On-resistance versus Breakdown Voltage for wide bandgap materials (Courtesy Palacios group, MIT).

advancement in solid state technologies the whole range of power electronics application can be addressed by solid state devices. The whole range of power for targeted application is shown in gure 1 [1]. Si transistors have been providing the solutions for the entire range of voltages needed for power conversion ranging from 100 s of Watts to Megawatts with various devices like MOSFETs, IGBTs, SJTs, BJTs and thyristors. However the advent of wide bandgap (WBG) materials, and their rapid technological progress, promises enhanced performance beyond the Si roadmap. The higher critical electric eld (Ec) due to the large bandgap of these materials makes them ideal for high-power electronics applications. A plot of the breakdown voltage (Vbd) and on-resistance (Ron), the two important parameters for evaluating any material system, is shown in gure 2. Increasing operating voltages need higher Vbd and higher efciencies need lower Ron which is simultaneously best served by WBG materials. Of the listed material systems SiC and GaN are more mature (after Si and GaAs) and commercially available for device fabrication. Figure 2 is plotted based on the bulk material properties where the entire structure is homoepitaxially grown. The two main losses in a switch are conduction and switching losses. Conduction loss (I2Ron) decreases with lower Ron. Switching
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loss ((IVop (tr + tf) f ), where I and Vop are the operating current and voltage respectively, tr and tf are rise and fall times) increases with the switching frequency, f . The device loss (conduction plus switching) is minimized by optimizing the device area [2] at each frequency and the minimum device loss with frequency is thus obtained as shown in gure 3 for Si, SiC and GaN. Clearly the advantage of the WBG material is noted at higher frequencies over Si, which is due to higher Ec and mobility () achievable in these materials. Lower device loss at higher frequencies makes WBG materials more attractive since they enable circuits operations at higher frequencies, thereby reducing the size of the passive components and making the system more compact and cost effective. WBG materials also enable high-temperature operation (>200 C), reducing or eliminating cooling requirements which saves a substantial amount of cost of the system. Today, SiC and GaN, having comparable advantages due to their material properties, are being pursued in both universities and industries as a replacement technology for Si. The next-generation PE device will ultimately be determined by the technology that has the best performance/cost advantage. So far, the cost, quality and availability of GaN material (both heteroepitaxial on Si and bulk GaN) have shown tremendous progress and if the trend is sustained the technology would succeed in replacing Si, by virtue of better performance at comparable cost. Lateral devices on SiC and Si substrates have broken the trade-off between Ron and Vbd and several studies done on this carry the mark of their success [36]. Vertical topology prevalent in Si and SiC power devices [7] has not been researched extensively unlike the lateral counterpart. In this paper the current status and scope of vertical GaN devices that depend on the success of bulk GaN substrates have been discussed.

Semicond. Sci. Technol. 28 (2013) 074014

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(a)

(b)

Figure 4. (a) A lateral AlGaN/GaN power HEMT (b) A vertical transistor using AlGaN/GaN layer structure on bulk GaN drift layer and substrate.

2. Applications space of lateral and vertical III-nitride transistors

GaN can be grown homoepitaxially or heteroepitaxially on foreign substrates (like Si, SiC and sapphire). The heteroepitaxial growth is more suited for low- and mediumpower (up to 10 kW) application where devices with lateral topologies are favored. In a typical lateral device, a thin layer of AlGaN is grown on top of the GaN channel to take advantage of the high mobility (2000 cm2 V1 s1) twodimensional electron gas (2DEG) formed at the AlGaN/GaN interface which is used as the current carrying layer. The source, drain and gate are fabricated on the same plane on top (see gure 4(a)). Electrons modulated by the gate ow from the source to the drain, where the distance between the gate and drain sustains the blocking voltage in the offstate of the device. Extensive eld plate structures with proper passivation are designed to manage the electric eld between the gate and the drain region well below the Ec of the materials that holds the voltage. The eld plate structures also help preventing electron trapping by the surface traps by managing high eld points, thereby preventing current collapse in these devices. However, for higher power (>10 kW) application where higher breakdown voltages (>1.2 kV) are required, the lateral topology becomes increasingly unattractive both in cost and manufacturability, due to very large chip areas required by the breakdown voltages at the required current level (typically over 20 A). Vertical topologies are eventually more economic and viable for such a range of PE application. The power level at which vertical devices become preferred over lateral devices is currently under investigation. A typical vertical device presented as CAVET (see gure 4(b)) has the source and gate on the top and the drain at the bottom. The current controlled by the gate ows through the bulk of the material into the drain. The horizontal high-mobility electron channel achieved by the AlGaN/GaN layer is used in conjunction with a thick GaN drift region in order to achieve low Ron and high breakdown voltage. Current blocking layers (CBL) achieved by either p-type doping of the GaN layer or
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by implantation (rendering the layer insulating) were designed such that the gate-modulated current owed vertically through a well-dened opening called aperture. Since vertical devices sustain the blocking voltage in the vertical direction into the bulk material of the device it makes the chip area smaller for a specic current of operation compared to the lateral design. The high-electric-eld region being buried in the bulk alleviates current collapse due to surface traps, eliminating or reducing extensive passivation and eld plating as required by the lateral designs.

3. Role of bulk GaN substrate

A vertical device structure is typically fabricated on a homoepitaxially grown material where thick device layers could be grown with low extended defects on thick bulk GaN substrates (200 m or more). Since the blocking voltage in the off-state of the device is sustained by the drift layer, to attain higher blocking voltages the drift region is grown thicker so that almost all of the applied voltage between the source and drain is absorbed in that region. Scaling up of voltages requires scaling up of the thickness of the drift region and thus vertical topology proves more economical in the device area for high-voltage applications. The manufacturability and commercialization would greatly depend on the availability of good-quality material with low extended defect density and low impurity concentration at a low cost. The advancement in solid state lighting (LEDs and laser diodes) has enabled great improvement in the bulk GaN technology facilitating growth of wafers over 6 in diameter with dislocation densities as low as 104 cm2. The trend so far looks very promising with the cost of bulk GaN substrate dropping by a signicant amount. According to Lux research 2 inch ammonothermal substrates cost will fall by more than 60% to $730/substrate in 2020, while 4 inch HVPE substrates cost will fall by 40% to $1340/substrate in 2020 which looks very encouraging. Such progress in bulk GaN technology makes the GaN vertical device an extremely important area

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(a )

(b )

(c )

Figure 5. (a) Schematic layout of a CAVET with all the critical parts of the device labeled (b) A CAVET with resistive aperture design showing unsaturated device IdVds characteristics. (c) The same CAVET with higher doped aperture does not choke the current, thereby leading to saturation. Simulation done in Silvaco Atlas.

of research when the need for energy-efcient PE devices for high-power application is becoming more and more obvious.

4. Overview of work reported on vertical transistors in III-nitride

Even though not as much research has been done on vertical devices compared to lateral devices, there were a few very encouraging results reported over the last 5 years [812]. Some of the research highlights are mentioned in this section. 4.1. CAVETs redesigned for power electronics application The CAVET was the rst vertical transistor reported in 2000 by Ben Yaacov et al [8]. The rst CAVETs were designed for RF power application for dispersion-free performance, exploiting the advantage of high-eld region being buried under the gate into the bulk of the material. Later, in 2009, the device was designed and reported as a high-voltage switch for power electronics application and demonstrated very promising depletion and enhancement mode performance [9]. The breakdown voltage was improved to 200 V as reported in 2012, with a 3 m drift region and Ron less than 2.2 m cm2 [10]. 4.2. Vertical insulated gate AlGaN/GaN HFET Kanechika et al reported vertical insulated gate HFETs [11] on bulk GaN substrates in 2007 with Ron = 2.6 m cm2. The device structure was similar to a CAVET with the CBL achieved through Mg doping of the GaN layer around the aperture. 4.3. Vertical GaN-Based trench gate metal oxide semiconductor FET In 2007 Otake et al [12] also reported vertical MOSFETs on bulk GaN with a threshold voltage of 3.7 V and Ron of 9.3 m cm2.
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Of these devices the CAVETs have made the most signicant progress for high-voltage power electronics application with demonstration of low Ron, low current collapse and high breakdown. With the availability of bulk substrates the technology looks viable for commercialization but needs focused research. The following section will discuss CAVETs in further detail and the future scopes will be discussed.

5. Operation principle, fabrication and results from CAVET

5.1. Operation principle The device (see gure 5(a)) comprises two source regions on the either side of the gate on the top and drain at the bottom. An AlGaN/GaN structure is utilized to form the high-mobility 2DEG which ows from sources on top to the drain and after being modulated by the gate. Electrons owing through the channel are directed through a conductive aperture layer into an n- GaN drift region designed to hold the blocking voltage and down to the n+ GaN drain region. CBLs are placed appropriately to prevent the current from owing from any other region in the device other than the aperture. It is essential to have the aperture region more conductive than the channel region to avoid any downstream choke of the current in the onstate of the transistor. In order to ensure this, the doping of the aperture region (Nap) is chosen such that the conductance of the aperture region (Lap.qNap.W g/tCBL) is higher than the channel resistance (where q is the electron charge, Lap is the length of the aperture, tCBL is the thickness of the CBL region and W g is the gate width of the device). A simulation, done in Silvaco ATLAS, shows the effect of the aperture conductivity on the device current with drain voltage. With a resistive aperture the drain current does not saturate at low drain bias as shown in gure 5(b) and the voltage drop is considerably held by the aperture region. Increasing the aperture conductivity leads to saturation of current as shown in gure 5(c), with most of

Semicond. Sci. Technol. 28 (2013) 074014

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0.15

IDS (kA/cm )

IDS (kA/cm2)

0.10

Mg (140 keV) Mg (120 keV) Mg (100 keV) Mg (80 keV) Al (90 keV)

1E-5 1E-6 1E-7 1E-8 1E-9

Mg (140 keV) Mg (120 keV) Mg (100 keV) Mg (80 keV) Al (90 keV)

0.05

10
(a )

20
(b )

30

40

50

0.1

10

V (V) DS

V (V) DS
(c )

Figure 6. (a) Two-terminal structure to test the blocking capability of the CBL (b) IV characteristics obtained from simple two-terminal measurements as shown in (a) showing that the Mg implanted CBL bolocking is superior to Al implanted blocking layer. The optimum energy was found to be 80 keV (c) log I-log V plotted for the same device.

the source to drain voltage dropping in the channel region. Unlike lateral HEMTs the high-electric-eld region under the off-state operation is buried under the gate in a CAVET and therefore the surface state-related dispersion is alleviated in these devices. 5.2. Fabrication challenges of a CAVET The design space in a CAVET involves designing a good CBL, an aperture conductive enough to not choke the current but not so conductive to limit the breakdown voltage of the device and a low doped drift region to hold the blocking voltage. The CBL is designed to provide a barrier to the electron owing from the source to the drain through any other path except the aperture. A p-type GaN layer therefore would be a very effective current block providing a barrier of over 3 eV. In the simulations done in Silvaco ATLAS a p-type GaN layer was used as the CBL. However activating Mg in a buried GaN layer has always been found challenging in the past [8] and the estimated energy barrier has never been achieved. Another way of achieving the CBL is by the ion-implantation technique which has proved to be advantageous over a partially activated Mg-doped CBL. Fabrication of a CAVET involves a two-step growth for both ion-implanted CBL and doped CBL, where the channel and the cap above the aperture are regrown after the CBL is formed in the desired regions. A doped CBL layer requires, in addition, etching away the CBL from the top of the aperture region before regrowing the channel. The etch leads to exposure of non-c polar facets in the side walls which has proved to be very conductive due to high levels of oxygen incorporation during regrowth, leading to parasitic leakage paths. The ion-implantation technique was found more benecial since the regrowth of the channel done after the selective implantation of the CBL around the aperture is done on a planar surface and does not require any etching of the surface layers. The scope of using different implant species with various doses and energies to render the GaN layer is quite large, and several of those are yet to be tried. Two promising results are discussed in detail here. In this work done at UCSB, the insulating property was obtained by implantation of two different implant species Al (dose: 1015 cm2, energy: 90 keV, at RT) and Mg (dose: 1015 cm2, energy: 80 keV, at
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RT). The results were compared using two-terminal structures where the implanted CBL under investigation with the desired implantation species was sandwiched between two n+ GaN layers which formed the anode and cathode contacts (see gure 6(a)). Under the bias, the electrons from the cathode (grounded) owed into the anode held at a positive potential, through the CBL. This resembles the off-state scenario of a CAVET where the drain is subjected to a positive voltage (like the anode) and the source is grounded (similar to the cathode). The difference is that the two-terminal structures do not have the thick drift region present in a CAVET. These short-loop experiments proved to be an excellent method of evaluating the blocking capability of the standalone CBL. Although due to differences in device structure and device dimensions, the breakdown voltages obtained from these two-terminal device results were not used to quantitatively derive the blocking voltage of the CBL in a CAVET, they were used to characterize and compare the blocking capabilities of different CBL designs. For example CBLs obtained using different implant energies for the same dose of Mg are shown in gures 6(b) and (c) and compared to Al implanted CBL. This study led to the important conclusion that as the implant energy was increased, the current blocking capability degraded, therefore showing the window of implant conditions that can be used to design the CBL. 80 keV was chosen for Mg (dose 1015 cm2) as the implant energy for the CBL while fabricating a CAVET. Anything less than 80 keV did not give the required implant prole as veried by simulation. 5.3. Comparison of Al and Mg implanted CBL in a fully functional CAVET The process ow of a CAVET is illustrated in gure 7. Two CAVETs with similar base structure grown by Toyota Motor Corp., Japan, which consisted of a 0.3 m thick GaN (Si: 5 1016 cm3?), 3 m thick n-GaN (Si: 2 1016 cm3) on n + GaN substrate were implanted selectively around the aperture with 1015 cm2 [Mg] or [Al] at 80 keV or 90 keV to form the CBL. The optimized implant energies were chosen to achieve a similar insulating property. Regrowth of the GaN channel and the Al0.3Ga0.7N cap was achieved using MOCVD

Semicond. Sci. Technol. 28 (2013) 074014

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Figure 7. Schematic representation of the process ow of a CAVET on bulk GaN substrate.

growth for both the Al and Mg implanted samples. Implanted source contacts were used to contact the source ohmic region and the drain was laid out at the back of the conductive GaN substrates. Device-to-device and bond pad isolations were obtained by dry etching (RIE) of mesa regions and covering the trenches with an MOCVD-deposited SiN layer. The Ni/Au/Ni gate was laid on top of a 25 nm thick MOCVD deposited SiN layer used as the gate dielectric to reduce the gate leakage in the device. CAVETs with the Al-implanted CBL showed wellbehaved dc transistor characteristics (shown in gure 8(a)). The maximum breakdown voltages, Vbd, obtained from these devices measured up to 280 V for a 3 m thick drift region (see gure 8(b)). Ron measured from the Al-implanted CBL CAVET was less than 1.5 m cm2. The Idon/Idoff of this device was 105. However when the CAVETs with Mgimplanted CBL, fabricated using similar process techniques as Al-implanted CAVETs were tested, uncontrolled threshold voltage shifts were observed and most of the devices did not turn on even at a large positive gate bias. All Mgimplanted CBL CAVETs showed similar behavior which was later identied with diffusion of Mg into the regrown channel region causing depletion of the 2DEG in the channel. This was veried by SIMS (see gure 8(c)) which showed a diffusion tail of the implanted Mg extending into the channel. To avoid diffusion of Mg into the regrown channel, which was favored by the higher temperature (1165 C) of regrowth in a MOCVD chamber, MBE regrowth technique was pursued for the regrowth of the GaN channel and AlGaN cap. The regrowth was done in a plasma-assisted MBE chamber where the regrowth temperature was maintained at 700 C. Details of the regrowth technique in both MOCVD and MBE systems has been discussed by the author elsewhere [10].
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The results obtained from CAVETs with Mg-implanted CBL using MBE regrowth showed promising Ron(2.2 m cm2) and VBD(200 V) as shown in gure 8(d). The Idon/Idoff of this device was 5 104. From Vbd and Ron values, Al-implanted and Mg-implanted CBL showed similar performance; however the dispersion results obtained in each case showed a signicant difference. The device with Al-implanted CBL was measured to be more dispersive compared to Mg-implanted CBL in pulsed IV measurement where the gate was pulsed with an 80 s pulse width signal. The comparison of the two devices is clearly seen in gures 8(a) and (d). One of the hypotheses to explain the results is based on diffusion of defects from the CBL to the channel, a phenomenon that is assisted by temperature. The implantation causes damage in the lattice, creating traps and point defects in the CBL. The defects could migrate closer to the GaN channel when regrown by MOCVD due to higher growth temperature. These defects could cause trapping of electrons under bias, leading to current collapse in the on-state of operation. The MBE regrown CAVETs did not show any current collapse under similar bias conditions suggesting that a lower regrowth temperature is favored to keep the defects localized within the CBL. However, that the current collapse phenomenon is a result of different nature of traps introduced by Al implanted and Mg implantation cannot be ruled out. From these initial results, Mg-implanted CBL with a lower temperature MBE regrowth looked superior to Al-implanted CBL in a fully functional CAVET and deserves to be explored more. One important point to be noted is that in all the CAVETs the CBL was shorted to the source to assist easy charging and discharging of the CBL. This is necessary for switching performance. The dependence of Ron on the Lap for the same doping density and the same aperture to gate overlap (Lgo) optimized for minimal parasitic leakage is illustrated in gure 9 (see gure 5(a) for the

Semicond. Sci. Technol. 28 (2013) 074014

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(a )

(b )

(c )

(d )

Figure 8. (a) dc and Pulsed IdVds characteristic for MOCVD regrown CAVET with Al-implanted CBL showing dispersion under 80 s pulses applied to gate. (b) Breakdown characteristics obtained from MOCVD regrown CAVET with Al implanted CBL and MBE regrown CAVET with Mg implanted CBL (c) SIMS prole showing diffusion of implanted Mg into the MOCVD regrown channel layer and is compared with the implanted Al which drops off sharply at the regrown interface. There is an Al marker in the plot that traces the Al level in the epitaxial layer. (d) dc and Pulsed IdVds characteristics for MBE regrown CAVET with Mg implanted CBL showing no dispersion under 80 s pulses applied to gate.
40

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5 0 0 2 4 6 8 10 12 14 16

Lap (m)
Figure 9. Ron decreases with increasing Lap (Nap and Lgo are kept constant at 5 1016 cm3 and 3 m, respectively). This was obtained from the MBE regrown CAVET with Mg-implanted CBL.

device schematic). Ron decreases with increase of Lap since the conductance in the aperture increases proportional to Lap. A saturation in Ron is observed when the dominant part of the resistance is offered by the channel and drift region.

6. Conclusion and future scopes

Although the earlier works done on vertical devices have shown great promise, much more focused research is yet to
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come. The rst challenge in achieving these devices is the availability of good-quality bulk GaN, needed for the highvoltage performance, followed by the cost of material. The rst problem is getting solved using different novel growth methods (like Ammonothermal, Na-ux method, improved HPVE techniques) resulting in materials with defect densities less than 104 cm2. The cost of material would go down as more and more industries embrace the technology for highpower device application. Among the fabrication challenges, the need for a good CBL ranks high in the list. A good blocking characteristic that remains effective up to very high voltages is essential for any vertical device. This makes the design and fabrication of the CBL, which is subjected to high electric elds, very critical. Challenges like activation of buried pdoping and unintentional doping of the etched side walls under regrowth conditions of the top channel layer have caused the barriers to be lower than the expected value and introduced unwanted leakage, respectively. Implantation techniques have resulted in good CBL but still challenges like activation (which requires very high temperature anneal) have prevented them to be an easy replacement of doped layers and primarily effective as isolation layers based on crystal damage. Critical dimensions of the aperture region and the optimum doping are other major design criteria that need to be effectively designed for sustaining the electric elds in off-state of the device. Regrowth of the channel and the cap remains critical

Ron (m cm 2)

Semicond. Sci. Technol. 28 (2013) 074014

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but has been found relatively easily achievable so far in all the CAVETs. With all the challenges mentioned, CAVETs have demonstrated electric elds over 100 V m1 suggesting that a 10 m thick drift region, if designed properly, should be capable of blocking over 1 kV. This is at least three times better than any industry-quality lateral device reported so far. This result alone suggests the importance of the vertical devices for achieving high-voltage, high-current and highpower performance and pushing the roadmap to limits not yet conceived.

Acknowledgments
The authors would like to acknowledge Dr T Uesugi, Dr T Kachi and Dr M Sugimoto from Toyota Motor Corp., Japan, for providing GaN substrates and funding this work.

References
[1] 2012 Presentation by Yole Development at CSEurope [2] Huang A Q 2004 New unipolar switching power device gure of merits IEEE Electron Device Lett. 25 298301 [3] Dora Y, Chakraborty A, McCarthy L, Keller S, Denbaars S P and Mishra U K 2006 High breakdown voltage achieved on AlGaN/GaN HEMTs with integrated slant eld plates IEEE Electron Device Lett. 27 7135

[4] Selvaraj S L, Suzue T and Egawa T 2009 Breakdown enhancement of AlGaN/GaN HEMTs on 4-in silicon by improving the GaN quality on thick buffer layers IEEE Electron Device Lett. 30 5879 [5] Lu B and Palacios T 2010 High breakdown (>1500 V) AlGaN/GaN HEMTs by substrate-transfer technology IEEE Electron Device Lett. 31 9513 [6] Chu R, Corrion A, Chen M, Ray L, Wong D, Zehnder D, Hughes B and Boutros K 2011 1200-V normally Off GaN-on-Si eld-effect transistors with low dynamic onresistance IEEE Electron Device Lett. 32 6324 [7] Baliga B J 1982 Semiconductors for high voltage, vertical channel FETs J. Appl. Phys. 53 175964 [8] Ben-Yaacov I, Seck Y-K, Mishra U K and Denbaars S P 2004 AlGaN/GaN current aperture vertical electron transistors with regrown channels J. Appl. Phys. 95 20738 [9] Chowdhury S, Swenson B L and Mishra U K 2008 Enhancement and depletion mode AlGaN/GaN CAVET with Mg-Ion-implanted GaN as current blocking layer IEEE Electron Device Lett. 29 5435 [10] Chowdhury S, Wong M H, Swenson B L and Mishra U K 2012 CAVET on bulk GaN substrates achieved with MBE-regrown AlGaN/GaN layers to suppress dispersion IEEE Electron Device Lett. 33 413 [11] Kanechika M, Sugimoto M, Soeima N, Ueda H, Ishiguro O, Kodama M, Hayashi E, Itoh K, Uesugi T and Kachi T 2007 A verticalinsulated gate AlGaN/GaN hetrojunction eld effect transisitor Japan. J. Appl. Phys. 46 L5035 [12] Otake H, Chikamatsu K, Yamaguchi A, Fujishima T and Ohta H 2008 Vertical GaN-Based trench gate metal oxide semiconductor eld-effect transistors on GaN bulk substrates Appl. Phys. Express 1 011105