Beruflich Dokumente
Kultur Dokumente
er Pipeline A/D Converters Comparison with Alternative Approaches Possible Future Trends and Barriers
Storage media
Audio I/O
Low-Integration Interface
High-Integration Interface
Wireless LAN Data Channel (1-50MS/s, 6-10b) Magnetic Storage Read Channel(50-200MS/s,6-8b) ADSL data channel (3-10MS/sec, 12-16b) Digital Multi-standard TV Baseband ADC(20MS/sec, 8-10b) Digital Video Camera ADC(20MS/sec, 8-12b) CATV Decoder Modem ADC(10-20MS/s,8-10b)A HDTV, various apps, (50-75MS/s, 10b) Digital-IF for Multi-standard Broadcast TV rcvr(100200Mb/sec, 8-12b)
t=1
t=2(0.4n+1)
Serial
t=2(n)
10
100
1000
10000
Key point: For Video Rates, only candidates are ash, multistep, and pipeline
AACD-1994, PRG SLIDE 6
High Speed- 10MS/sec->500MS/sec Complex- requires 2N Comparators, High Power Used mainly for very high-speed signal acquisition
AACD-1994, PRG SLIDE 8
No gain in path- requires precision comparators Requires at least three full clocks Usually requires R-string Exponential hardware growth with resolution
AACD-1994, PRG SLIDE 9
k bits
k bits
...
Stage i
...
Stage Ns
vo vin
k-bit k-bit
S/H
vo
00
01
10
11
vin
Disadvantage:
ADC
DAC
Advantages:
Requires fast
interstage processing
Design Considerations for HighSpeed, Low-Power CMOS A/D Converters Introduction: Technology and Architecture Considerations Design of Low-Power Pipeline A/D Converters Comparison with Alternative Approaches Possible Future Trends and Barriers
Design of Low-Power Pipeline ADCs Some Basic Pipeline Concepts Low-Power Interstage Gain Blocks Dynamic Comparator Implementation Bootstrapped Clock Driver Design Capacitor Size Optimization Experimental Results
v+ in vin
Comps k bits
0 0 0 1 1 1 1
CS +100
CI
v+ o vo
-+
vDAC
0 0 0 1 0 0 0 0
vDAC
CS
CI
Decode Logic
Bias
Clocks
Ref: C. Conroy, VLSI92
VIN
VOUT
Code
ADC usually R-string ash or Cap-based ash.
AACD-1994, PRG SLIDE 14
Folded Cascode Cs
Cf Cl
Cgs
Cl+Cp =CLt
This is a single-time-constant circuit! C gs C = Ft 1 2f t C 1 + C Lt Ft
1 g m
(C
+ C
gs
1 + 1 + C
Ft
+ C
Lt C
Fixed Vgs-Vt
s = 1 + C 2f 1 t gs C
1 + 1 + C
C gs
Ft
+ C
Lt C
Ft
1 2f t
C 1 + C
Lt Ft
m in
m in
1 2f t
1 + (A
m in
1 g m
(C
+ C
gs
1 + 1 + C
C gs
Ft
+ C
Lt C
Ft
Minimize: Result:
= g s (o p t )
C C F
+ CL
2 2f T
(1 +
C C
L F
) = 2
m in
opt
8V
dd
1 ( 1 + A ) 2 C + q S 2
C C F
L2 + CL 2
C L
Observations:
Optimum Cgs is equal to Cequiv Power is very sensitive to charge gain- use low gain/ stage in pipelines Power drops rapidly with technology line width Analysis says pwr goes as square of speed, channel
length, but actually it is more like linear because of Slew Rate, Velocity Saturation.
Leff, Microns 0.8 0.8 0.8 0.8 Desired Time Const. 400ps 400ps 400ps 400ps kT/C noise for 1/6 lsb, Vswing=1V 8bits, 600uVRMS 10bits, 150uVRMS 12bits, 37uVRMS 14bits, 9uVRMS Cs 10fF 160fF 2.5pF 40pF 5fF 80fF 1.25pF 20pF Cf 5fF 80fF 1.25pF 20pF Cl Power, Vdd=3V 72uW 1.1mW 18mW 200mW
Poor voltage gain-settling time trade-off Poor voltage swing-settling time trade-off Barely usable at 3V, not usable at 1.5V
Alternative Approaches:
Add broadband input stage to telescopic Two-stage Miller compensated w/one stage cascoded Multi-stage Nested Miller amplier
Bias1 C3 Vout+
Bias1 C4 Vout-
Bias3
ts = 17ns(0.1%) Cs = 0.39pF Cf = 0.39pF Cl = 1.8pF Pd = 4.1mW Vdd=3.3V Av>60dB Swing = +/1Volt P-P
Vin
Latch
dout
Clk
Key Goal:
Key Question:
n1bit ADC
n1bit DAC
n2bit ADC
n2bit DAC
Vin
+ S/H
Key Point: Can remove ADC Errors by Increasing ADC range in next stg
Vin
Correction Logic
Final Result: DAC Linearity and amplier gain errors ultimately limit linearity
vout
+1 Key Point: Tolerates comparator offset on the order of 1/4 full scale!
00
01
10
0 -1
vin
1 2
1 4
1 4
1 2
+1
-1
q q
Vdd VoutVout+
VrefM1
VinVin+ M2 M3 M4
Vref+
R1
R2
If w1 = M x w2, Vdecision = Vref / M Well dened built-in Vdecision based on ratio Simple design for low input cap. No DC power!
AACD-1994, PRG SLIDE 28
Cs
DAC
STAGE i
C C
B+1 bits
Vout
Vin
GND Vdd
GND -Vthp
Vdd -Vthn
Vdd=5V
Vdd=3.3V
Gap!
Vdd=1.5V
*Integrated A/D&D/A Converter, OCATE, July 1991 Low Power ADC by Vlado Valencic
+ standard design approach - need process mod + Needed for digital anyway - Big cost in power due to limited swing to rail - possible cross-talk to sensitive nodes - difcult to predict CL + no cross-talk (can isolate sensitive nodes) + easy to predict CL
Vhi = ~5V
3.3 0
Vhi
C2
+ C L + C parasitic
C2
2Vdd
Without Scaling
STAGE 4
Vin
STAGE 1
STAGE 2
STAGE 3
10bit
9bit 8bit
With Scaling
STAGE 3 STAGE 4
Vin
STAGE 1
STAGE 2
Optimization result:
Power
Unscaled
Noise Limited
Scaled!
1 2 N-1 N Stage
Approx. 40 - 50% reduction in static power consumption! Minimum performance degradation Requires auto-calibration to correct cap mismatches for front stages
AACD-1994, PRG SLIDE 34
Experimental Prototype 1.2m 2-poly, 1-metal CMOS Technology 3.2x3.3mm active area
Experimentally Observed Power vs. Sampling Rate Master bias current adjusted for each sample rate
Power(mW) 30 20 15 10
5 3 1 2 5
AACD-1994, PRG SLIDE 36
Fs (MS/s) 10 20
Measurement Results
ADC Performance: 3.3V @ 25C
Technology Resolution Conversion Rate Active Area Differential Input Range Input Capacitance Power Dissipation DNL/INL SNDR 1.2-m CMOS 10 b 20 MS/s 3.2 x 3.3 mm2 +/- 1 V 1 pF (single-ended) 35 mW* at 20MS/s (2.8 mW* at 1MS/s) 0.5 / 0.6 LSB 59.1 dB (Fin=100 kHz) 55.0 dB (Fin= 10 MHz)
10
[93] Matsushita,ISSCC93
0.1
10bit ADC
[Year]
This Work
3m
2m 1.5m
1m
1/L(m) 0.8m
1. Sekino,Sony,ISSCC82 2. Tsukada,Hitach i, ISSCC85 3. Dingwall, RCA,ISSCC85 4. Peetz, HP,ISSCC86 5.Lewis,UCB,I SSCC86 6. V.D.Grift,Phil, ISSCC87 7. Yoshi,Sony,ISSCC87 8. Akazaw,NTT,ISSCC87 9. Tsutomoto,NTT,ISSCC 88 10. V.D.Plaasche,Ph,ISSC C88
2step
30M
4Gbip
5V
0.7
35K
7.5
2.74
FL
25M
2uCMOS
5V
0.3
33K
16
13.6
2step
5M
2uCMOS
5V
0.15
6K
3.3
5.6
FL
250M
7Gbip
12
48K
36
0.77
Pipe
5M
3uCMOS
10
0.18
10K
7.2
23.0
Fold
50M
7.5Gbip
0.3
10K
6.6
5.63
FL
350M
10Gbip
1.5
22K
35
5.97
FL
400M
18Gbip
2.7
65K
22
2.08
FL
2G
26Gbip
18K
76
9.73
Fold
100M
12Gbip
0.8
17K
8.3
2.65
Pipe
1M
12
1.5CMOS
0.4
7.8K
0.4
4.0
2step
20M
10 b 12 b 8b
4.5Gbip
0.9
40K
4.4
5.06
2step
1M
3uCMOS
10
0.7
150K
1.4
8.0
2st
40M
1uCMOS
0.6
20K
8.0
3.41
2st
1.5M
10 b 8b
2uCMOS
0.15
15K
1.0
6.82
2st
40M?
1.4CMOS
0.1
8.1K
22.2
56.8?
Pipe
20M
10 b 10 b 10 b
BICMOS
1.0
85K
10.0
10.2
2step
15M
1uCMOS
0.250
4K
3.0
12.28
2step
75M
7Gbip
23K
10.7
5.476
Pipe
2.5M
3uCMOS
5V
0.1
40K
3.6
144(12b ) 13.6
Pipe
20M
1uCMOS
5V
0.3
12K
4.0
FL
500M
10Gbip
5V
3.1
35K
50
4.1
FL
1G
6b
13Gbip
5V
2.8
40K
75
6.8
fold
600M
8b
5V
0.9
7K
50(est)
14.2
Pipe
50M
10 b
3Gbip
5V
0.75
18K
16
21.8
Pipe
20M
12 b 12 b
7Gbip
10V
3.5
26K
3.5
2step
5M
1uCMOS
5V
0.2
16K
0.8
16.2
Pipe
1M
15 b
4G,2.4uBiCM OS
10
1.8
100K
025
4.4
Pipe
100M
0.8uBiCMOS
5V
0.95
32K
5-10?
10.7
Pipe
100M
12Gbip
0.8
30K
10.2
85M
8b
1.2uCMOS
0.8
35K
18
5.7
30M
10 b
0.8uCMOS
3.3
0.030+
20K
3.5
90
FM1 is ratio of sampling rate to equivalent technology ft multiplied by 103 FM2 is a power gure of merit normalized to technology ft. It is given by
FM2 = 2 B
(S R )
Pf
100
35
This work 22
31
FM2 30.0
11 2
26
5 23
33 32
27
FM2 =
(S R )
Pf
19 18
33
29
10.0
9
25
14 12
28
34
3.0
15 8 1 10
24
7 6 3
16 20 13 21
1.0
11
12
13
Comparison of Power Figure of Merit, Recently Published Flash, 2-step, and Pipeline ADCs
AACD-1994, PRG SLIDE 45
Design Considerations for HighSpeed, Low-Power CMOS A/D Converters Introduction: Technology and Architecture Considerations Design of Low-Power Pipeline A/D Converters Comparison with Alternative Approaches Possible Future Trends and Barriers
In-band kT/C: 2 v n
f pb f 2 s
kT C s
Cs can be 2x smaller Sample rate is 2x higher Power remains constant for constant in-band noise
One-bit increase in SNR costs 4X in cap value, power
AACD-1994, PRG SLIDE 48
Author
Type
Out SR 200K
Techn
PSV
FM3
1. Dedic, ISSCC94 2. Alexander, ISSCC94 3. Ritoneime, ISSCC94 4. Ray, pc 5. Mats., ISSCC94 6. Tcho
6th ord. 4th ord. 4th ord. 4th ord. 2nd ord. pipe
1.2uC MOS 1uBiC MOS 1.2uB iCMO S 1uCM OS 0.5uC MOS 1.2uC MOS
=
5V
7.8e-16
200mW/ MS/sec
12M
192K
5V
350e-16
2.5M
44K
5V
5.5e-16
18M 6M 20M
13b 9b 10b
5V 1V 3V
FM 3
P f 2 s 2B
1000 100
4 1
10 1
5 6
10
12
14
16
Design Considerations for HighSpeed, Low-Power CMOS A/D Converters Introduction: Technology and Architecture Considerations Design of Low-Power Pipeline A/D Converters Comparison with Alternative Approaches Possible Future Trends and Barriers
More effective on-board sub-regulation? Better CAD tools for simulation? Process/package enhancements?
How do we push sample rates to 200-300 Mhz in CMOS?
Super-integrated subsystem, 2004 0.15 micron technology 1.5-2.5V Vdd, >108 xistors/chip Analog content<5%