PIC18F6520/8520/6620/8620/6720/8720

10.0 I/O PORTS

10.1
Depending on the device selected, there are either seven or nine I/O ports available on PIC18FXX20 devices. Some of their pins are multiplexed with one or more alternate functions from the other peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: TRIS register (data direction register) PORT register (reads the levels on the pins of the device) LAT register (output latch) The Data Latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are driving. A simplified version of a generic I/O port and its operation is shown in Figure 10-1.

PORTA, TRISA and LATA Registers

PORTA is a 7-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. The Data Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA register, read and write the latched output value for PORTA. The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/ T0CKI pin is a Schmitt Trigger input and an open-drain output. All other RA port pins have TTL input levels and full CMOS output drivers. The RA6 pin is only enabled as a general I/O pin in ECIO and RCIO Oscillator modes. The other PORTA pins are multiplexed with analog inputs and the analog VREF+ and VREF- inputs. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register 1). Note: On a Power-on Reset, RA5 and RA3:RA0 are configured as analog inputs and read as 0. RA6 and RA4 are configured as digital inputs.

FIGURE 10-1:

SIMPLIFIED BLOCK DIAGRAM OF PORT/LAT/ TRIS OPERATION

RD LAT TRIS D WR LAT + WR Port Q

CK Data Latch

Data Bus RD Port I/O pin

The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.

EXAMPLE 10-1:
CLRF ; ; ; LATA ; ; ; 0x0F ; ADCON1 ; 0xCF ; ; ; TRISA ; ; PORTA

INITIALIZING PORTA
Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs

CLRF

MOVLW MOVWF MOVLW

MOVWF

2004 Microchip Technology Inc.

DS39609B-page 103

PIC18F6520/8520/6620/8620/6720/8720
FIGURE 10-2: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS FIGURE 10-3: BLOCK DIAGRAM OF RA4/T0CKI PIN

RD LATA
Data

RD LATA Data Bus WR LATA or PORTA

Bus WR LATA or PORTA

Q VDD

Q Q N

CK

CK

I/O pin(1)

Data Latch D WR TRISA Q N I/O pin(1) WR TRISA CK Q TRIS Latch VSS Analog Input Mode RD TRISA RD TRISA Q D TTL Input Buffer

Data Latch D Q Q

VSS Schmitt Trigger Input Buffer

CK

TRIS Latch

D EN EN

EN RD PORTA To A/D Converter and LVD Modules Note 1: I/O pins have protection diodes to VDD and VSS. Note 1: RD PORTA TMR0 Clock Input

I/O pins have protection diodes to VDD and VSS.

FIGURE 10-4:

BLOCK DIAGRAM OF RA6 PIN (WHEN ENABLED AS I/O)

ECRA6 or RCRA6 Enable Data Bus RD LATA D WR LATA or PORTA Q

VDD P

CK

Data Latch D WR TRISA Q N I/O pin(1)

CK

VSS

TRIS Latch

RD TRISA ECRA6 or RCRA6 Enable

TTL Input Buffer

D EN

RD PORTA Note 1: I/O pins have protection diodes to VDD and VSS.

DS39609B-page 104

2004 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720
TABLE 10-1:
Name RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/LVDIN OSC2/CLKO/RA6

PORTA FUNCTIONS
Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 Buffer TTL TTL TTL TTL ST TTL TTL Input/output or analog input. Input/output or analog input. Input/output or analog input or VREF-. Input/output or analog input or VREF+. Input/output or external clock input for Timer0. Output is open-drain type. Input/output or slave select input for synchronous serial port or analog input, or Low-Voltage Detect input. OSC2 or clock output, or I/O pin. Function

Legend: TTL = TTL input, ST = Schmitt Trigger input

TABLE 10-2:
Name PORTA LATA TRISA ADCON1

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Bit 6 RA6 Bit 5 RA5 Bit 4 RA4 Bit 3 RA3 Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on POR, BOR Value on all other Resets

Bit 7

-x0x 0000 -u0u 0000 -xxx xxxx -uuu uuuu -111 1111 -111 1111

LATA Data Output Register PORTA Data Direction Register VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0

--00 0000 --00 0000

Legend: x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by PORTA.

2004 Microchip Technology Inc.

DS39609B-page 105

PIC18F6520/8520/6620/8620/6720/8720
10.2 PORTB, TRISB and LATB Registers
A mismatch condition will continue to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. RB3 can be configured by the configuration bit CCP2MX, as the alternate peripheral pin for the CCP2 module. This is only available when the device is configured in Microprocessor, Microprocessor with Boot Block, or Extended Microcontroller operating modes. The RB5 pin is used as the LVP programming pin. When the LVP configuration bit is programmed, this pin loses the I/O function and become a programming test function. Note: When LVP is enabled, the weak pull-up on RB5 is disabled.

PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register, read and write the latched output value for PORTB.

EXAMPLE 10-2:
CLRF PORTB ; ; ; ; ; ; ; ; ; ; ; ;

INITIALIZING PORTB
Initialize PORTB by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs

CLRF

LATB

MOVLW

0xCF

FIGURE 10-5:

BLOCK DIAGRAM OF RB7:RB4 PINS

VDD Weak P Pull-up Data Latch D CK TRIS Latch D Q TTL Input Buffer Q I/O pin(1)

MOVWF

TRISB

RBPU(2)

Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Note: On a Power-on Reset, these pins are configured as digital inputs.

Data Bus WR LATB or PORTB

WR TRISB

CK

ST Buffer

Four of the PORTB pins (RB3:RB0) are the external interrupt pins, INT3 through INT0. In order to use these pins as external interrupts, the corresponding TRISB bit must be set to 1. The other four PORTB pins (RB7:RB4) have an interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The mismatch outputs of RB7:RB4 are ORed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON<0>). This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of PORTB (except with the MOVFF instruction). This will end the mismatch condition. Clear flag bit RBIF.

RD TRISB

RD LATB Latch Q RD PORTB EN Set RBIF Q1 D

Q From other RB7:RB4 pins RB7:RB5 in Serial Programming Mode Note 1: 2:

D RD PORTB EN Q3

I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).

b)

DS39609B-page 106

2004 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720
FIGURE 10-6: BLOCK DIAGRAM OF RB2:RB0 PINS
VDD RBPU(2) Data Latch D Q I/O pin(1) CK TRIS Latch D WR TRIS CK Q TTL Input Buffer Weak P Pull-up

Data Bus WR Port

RD TRIS Q RD Port EN INTx Schmitt Trigger Buffer Note 1: 2: RD Port D

I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).

FIGURE 10-7:

BLOCK DIAGRAM OF RB3 PIN

VDD RBPU(2) CCP2MX CCP Output(3) 1 VDD P Enable(3) CCP Output Data Bus WR LATB or WR PORTB Data Latch D CK TRIS Latch D WR TRISB CK Q Q N VSS TTL Input Buffer 0 I/O pin(1) Weak P Pull-up

RD TRISB RD LATB Q RD PORTB EN D

RD PORTB CCP2 or INT3 Schmitt Trigger Buffer Note 1: 2: 3: CCP2MX = 0

I/O pin has diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration register and the device is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode.

2004 Microchip Technology Inc.

DS39609B-page 107

PIC18F6520/8520/6620/8620/6720/8720
TABLE 10-3:
Name RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3/CCP2(3)

PORTB FUNCTIONS
Bit# bit 0 bit 1 bit 2 bit 3 Buffer TTL/ST
(1)

Function Input/output pin or external interrupt input 0. Internal software programmable weak pull-up. Input/output pin or external interrupt input 1. Internal software programmable weak pull-up. Input/output pin or external interrupt input 2. Internal software programmable weak pull-up. Input/output pin or external interrupt input 3. Capture2 input/Compare2 output/PWM output (when CCP2MX configuration bit is enabled, all PIC18F8X20 operating modes except Microcontroller mode). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Low-voltage ICSP enable pin. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data.

TTL/ST(1) TTL/ST(1) TTL/ST(4)

RB4/KBI0 RB5/KBI1/PGM

bit 4 bit 5

TTL TTL/ST(2)

RB6/KBI2/PGC

bit 6

TTL/ST(2)

RB7/KBI3/PGD

bit 7

TTL/ST(2)

Legend: Note 1: 2: 3: 4:

TTL = TTL input, ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. RC1 is the alternate assignment for CCP2 when CCP2MX is not set (all operating modes except Microcontroller mode). This buffer is a Schmitt Trigger input when configured as the CCP2 input.

TABLE 10-4:
Name PORTB LATB TRISB INTCON INTCON2 INTCON3 Legend: Bit 7 RB7

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Bit 6 RB6 Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 INT0IE RBIE TMR0IF TMR0IP INT3IF INT0IF INT3IP INT2IF RBIF RBIP INT1IF 0000 0000 1111 1111 1100 0000 Value on all other Resets uuuu uuuu uuuu uuuu 1111 1111 0000 0000 1111 1111 1100 0000

LATB Data Output Register PORTB Data Direction Register GIE/ GIEH RBPU INT2IP PEIE/ GIEL INT1IP TMR0IE

INTEDG0 INTEDG1 INTEDG2 INTEDG3 INT3IE INT2IE INT1IE

x = unknown, u = unchanged. Shaded cells are not used by PORTB.

DS39609B-page 108

2004 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720
10.3 PORTC, TRISC and LATC Registers
The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register, without concern due to peripheral overrides. RC1 is normally configured by configuration bit, CCP2MX, as the default peripheral pin of the CCP2 module (default/erased state, CCP2MX = 1).

PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register, read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions (Table 10-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. Note: On a Power-on Reset, these pins are configured as digital inputs.

EXAMPLE 10-3:
CLRF PORTC ; ; ; ; ; ; ; ; ; ; ; ;

INITIALIZING PORTC
Initialize PORTC by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs

CLRF

LATC

MOVLW

0xCF

MOVWF

TRISC

FIGURE 10-8:

PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)

PORTC/Peripheral Out Select Peripheral Data Out 0 RD LATC Data Bus WR LATC or WR PORTC
D CK Q Q

VDD P

I/O pin(1) N TRIS Override Logic VSS Pin RC0 RC1 TRIS OVERRIDE Override Yes Yes Peripheral Timer1 Osc for Timer1/Timer3 Timer1 Osc for Timer1/Timer3, CCP2 I/O CCP1 I/O SPI/I2C Master Clock I2C Data Out SPI Data Out USART1 Async Xmit, Sync Clock USART1 Sync Data Out

Data Latch D Q Q

WR TRISC

CK

TRIS Latch RD TRISC Peripheral Output Enable(2)

Schmitt Trigger
Q D EN

RC2 RC3 RC4 RC5 RC6 RC7

Yes Yes Yes Yes Yes Yes

RD PORTC Peripheral Data In Note 1: 2: I/O pins have diode protection to VDD and VSS. Peripheral Output Enable is only active if Peripheral Select is active.

2004 Microchip Technology Inc.

DS39609B-page 109

PIC18F6520/8520/6620/8620/6720/8720
TABLE 10-5:
Name RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1)

PORTC FUNCTIONS
Bit# bit 0 bit 1 Buffer Type ST ST Function Input/output port pin, Timer1 oscillator output or Timer1/Timer3 clock input. Input/output port pin, Timer1 oscillator input or Capture2 input/ Compare2 output/PWM output (when CCP2MX configuration bit is disabled). Input/output port pin or Capture1 input/Compare1 output/ PWM1 output. RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4 can also be the SPI data in (SPI mode) or data I/O (I2C mode). Input/output port pin or synchronous serial port data output. Input/output port pin, addressable USART1 asynchronous transmit or addressable USART1 synchronous clock. Input/output port pin, addressable USART1 asynchronous receive or addressable USART1 synchronous data.

RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1

bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

ST ST ST ST ST ST

Legend: ST = Schmitt Trigger input Note 1: RB3 is the alternate assignment for CCP2 when CCP2MX is set.

TABLE 10-6:
Name PORTC LATC TRISC

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Bit 6 RC6 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 Value on all other Resets uuuu uuuu uuuu uuuu 1111 1111

Bit 7 RC7

LATC Data Output Register PORTC Data Direction Register

Legend: x = unknown, u = unchanged

DS39609B-page 110

2004 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720
10.4 PORTD, TRISD and LATD Registers
PORTD can also be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 10.10 Parallel Slave Port for additional information on the Parallel Slave Port (PSP).

PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register, read and write the latched output value for PORTD. PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: On a Power-on Reset, these pins are configured as digital inputs.

EXAMPLE 10-4:
CLRF PORTD ; ; ; ; ; ; ; ; ; ; ; ;

INITIALIZING PORTD
Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD<3:0> as inputs RD<5:4> as outputs RD<7:6> as inputs

CLRF

LATD

MOVLW

0xCF

MOVWF

TRISD

PORTD is multiplexed with the system bus as the external memory interface; I/O port functions are only available when the system bus is disabled, by setting the EBDIS bit in the MEMCOM register (MEMCON<7>). When operating as the external memory interface, PORTD is the low-order byte of the multiplexed address/data bus (AD7:AD0).

FIGURE 10-9:

PORTD BLOCK DIAGRAM IN I/O PORT MODE

PORTD/CCP1 Select PSPMODE

RD LATD Data Bus WR LATD or PORTD D Q VDD

CK

Data Latch D WR TRISD Q I/O pin(1) CK Q 0 N VSS TTL Buffer RD TRISD Q D 0 RD PORTD 0 EN EN Schmitt Trigger Input Buffer 1 TRIS Latch PSP Write 1

PSP Read

Note 1:

I/O pins have diode protection to VDD and VSS.

2004 Microchip Technology Inc.

DS39609B-page 111

PIC18F6520/8520/6620/8620/6720/8720
FIGURE 10-10: PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE
Q D EN EN RD PORTD

RD LATD Data Bus WR LATD or PORTD Port Data CK Data Latch D WR TRISD CK TRIS Latch RD TRISD Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to VDD and VSS. Q TTL Input Buffer I/O pin(1) 0 1

DS39609B-page 112

2004 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720
TABLE 10-7:
Name RD0/PSP0/AD0 RD1/PSP1/AD1 RD2/PSP2/AD2 RD3/PSP3/AD3 RD4/PSP4/AD4 RD5/PSP5/AD5 RD6/PSP6/AD6 RD7/PSP7/AD7

PORTD FUNCTIONS
Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Buffer Type ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL
(1) (1) (1) (1) (1) (1) (1) (1)

Function Input/output port pin, Parallel Slave Port bit 0 or address/data bus bit 0. Input/output port pin, Parallel Slave Port bit 1 or address/data bus bit 1. Input/output port pin, Parallel Slave Port bit 2 or address/data bus bit 2. Input/output port pin, Parallel Slave Port bit 3 or address/data bus bit 3. Input/output port pin, Parallel Slave Port bit 4 or address/data bus bit 4. Input/output port pin, Parallel Slave Port bit 5 or address/data bus bit 5. Input/output port pin, Parallel Slave Port bit 6 or address/data bus bit 6. Input/output port pin, Parallel Slave Port bit 7 or address/data bus bit 7.

Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave Port mode.

TABLE 10-8:
Name PORTD LATD TRISD PSPCON MEMCON

SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Bit 6 RD6 Bit 5 RD5 Bit 4 RD4 Bit 3 RD3 Bit 2 RD2 Bit 1 RD1 Bit 0 RD0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 WM1 WM0 0000 ---0-00 --00 Value on all other Resets uuuu uuuu uuuu uuuu 1111 1111 0000 ---0-00 --00

Bit 7 RD7

LATD Data Output Register PORTD Data Direction Register IBF EBDIS OBF IBOV WAIT1 PSPMODE WAIT0

Legend: x = unknown, u = unchanged, = unimplemented, read as 0. Shaded cells are not used by PORTD.

2004 Microchip Technology Inc.

DS39609B-page 113

PIC18F6520/8520/6620/8620/6720/8720
10.5 PORTE, TRISE and LATE Registers
When the Parallel Slave Port is active, three PORTE pins (RE0/RD/AD8, RE1/WR/AD9 and RE2/CS/AD10) function as its control inputs. This automatically occurs when the PSPMODE bit (PSPCON<4>) is set. Users must also make certain that bits TRISE<2:0> are set to configure the pins as digital inputs and the ADCON1 register is configured for digital I/O. The PORTE PSP control functions are summarized in Table 10-9. Pin RE7 can be configured as the alternate peripheral pin for CCP module 2 when the device is operating in Microcontroller mode. This is done by clearing the configuration bit, CCP2MX, in configuration register, CONFIG3H (CONFIG3H<0>). Note: For PIC18F8X20 (80-pin) devices operating in Extended Microcontroller mode, PORTE defaults to the system bus on Power-on Reset.

PORTE is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATE register, read and write the latched output value for PORTE. PORTE is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. PORTE is multiplexed with the CCP module (Table 10-9). On PIC18F8X20 devices, PORTE is also multiplexed with the system bus as the external memory interface; the I/O bus is available only when the system bus is disabled, by setting the EBDIS bit in the MEMCON register (MEMCON<7>). If the device is configured in Microprocessor or Extended Microcontroller mode, then the PORTE<7:0> becomes the high byte of the address/data bus for the external program memory interface. In Microcontroller mode, the PORTE<2:0> pins become the control inputs for the Parallel Slave Port when bit PSPMODE (PSPCON<4>) is set. (Refer to Section 4.1.1 PIC18F8X20 Program Memory Modes for more information on program memory modes.)

EXAMPLE 10-5:
CLRF PORTE ; ; ; ; ; ; ; ; ; ; ;

INITIALIZING PORTE
Initialize PORTE by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RE1:RE0 as inputs RE7:RE2 as outputs

CLRF

LATE

MOVLW

0x03

MOVWF

TRISE

DS39609B-page 114

2004 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720
FIGURE 10-11: PORTE BLOCK DIAGRAM IN I/O MODE
Peripheral Out Select Peripheral Data Out 0 1 D CK Q Q N TRIS Override VSS Pin RE0 RE1 Schmitt Trigger Q D EN RD PORTE Peripheral Data In Note 1: I/O pins have diode protection to VDD and VSS. RE2 RE3 RE4 RE5 RE6 RE7 TRIS OVERRIDE Override Yes Yes Yes Yes Yes Yes Yes Yes Peripheral External Bus External Bus External Bus External Bus External Bus External Bus External Bus External Bus VDD P RD LATE Data Bus WR LATE or WR PORTE I/O pin(1)

Data Latch D WR TRISE CK Q Q

TRIS Latch RD TRISE Peripheral Enable

FIGURE 10-12:

PORTE BLOCK DIAGRAM IN SYSTEM BUS MODE

Q D EN EN RD PORTE

RD LATE Data Bus WR LATE or PORTE D CK Data Latch D WR TRISE CK TRIS Latch RD TRISE Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to VDD and VSS. Q TTL Input Buffer Q Port 0 Data 1 I/O pin(1)

2004 Microchip Technology Inc.

DS39609B-page 115

PIC18F6520/8520/6620/8620/6720/8720
TABLE 10-9:
Name RE0/RD/AD8

PORTE FUNCTIONS
Bit# bit 0 Buffer Type ST/TTL
(1)

Function Input/output port pin, read control for Parallel Slave Port or address/data bit 8 For RD (PSP Control mode): 1 = Not a read operation 0 = Read operation, reads PORTD register (if chip selected) Input/output port pin, write control for Parallel Slave Port or address/data bit 9 For WR (PSP Control mode): 1 = Not a write operation 0 = Write operation, writes PORTD register (if chip selected) Input/output port pin, chip select control for Parallel Slave Port or address/data bit 10 For CS (PSP Control mode): 1 = Device is not selected 0 = Device is selected Input/output port pin or address/data bit 11. Input/output port pin or address/data bit 12. Input/output port pin or address/data bit 13. Input/output port pin or address/data bit 14. Input/output port pin, Capture2 input/Compare2 output/PWM output (PIC18F8X20 devices in Microcontroller mode only) or address/data bit 15.

RE1/WR/AD9

bit 1

ST/TTL(1)

RE2/CS/AD10

bit 2

ST/TTL(1)

RE3/AD11 RE4/AD12 RE5/AD13 RE6/AD14 RE7/CCP2/AD15

bit 3 bit 4 bit 5 bit 6 bit 7

ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1)

Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O or CCP mode and TTL buffers when in System Bus or PSP Control mode.

TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Name TRISE PORTE LATE MEMCON PSPCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR 1111 1111 xxxx xxxx xxxx xxxx WM1 WM0 0-00 --00 0000 --- Value on all other Resets 1111 1111 uuuu uuuu uuuu uuuu 0000 --00 0000 ----

PORTE Data Direction Control Register Read PORTE pin/Write PORTE Data Latch Read PORTE Data Latch/Write PORTE Data Latch EBDIS IBF OBF WAIT1 IBOV WAIT0 PSPMODE

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTE.

DS39609B-page 116

2004 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720
10.6 PORTF, LATF and TRISF Registers
EXAMPLE 10-6:
CLRF PORTF ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

INITIALIZING PORTF
Initialize PORTF by clearing output data latches Alternate method to clear output data latches Turn off comparators Set PORTF as digital I/O Value used to initialize data direction Set RF3:RF0 as inputs RF5:RF4 as outputs RF7:RF6 as inputs

PORTF is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATF register, read and write the latched output value for PORTF. PORTF is multiplexed with several analog peripheral functions, including the A/D converter inputs and comparator inputs, outputs and voltage reference. Note 1: On a Power-on Reset, the RF6:RF0 pins are configured as inputs and read as 0. 2: To configure PORTF as digital I/O, turn off comparators and set ADCON1 value.

CLRF

LATF

MOVLW MOVWF MOVLW MOVWF MOVLW

0x07 CMCON 0x0F ADCON1 0xCF

MOVWF

TRISF

FIGURE 10-13:

PORTF RF1/AN6/C2OUT, RF2/AN7/C1OUT PINS BLOCK DIAGRAM

Port/Comparator Select Comparator Data Out 0 1 VDD P RD LATF Data Bus WR LATF or WR PORTF D CK Q Q N VSS Analog Input Mode Schmitt Trigger Q D EN RD PORTF I/O pin

Data Latch D Q Q

WR TRISF

CK

TRIS Latch

RD TRISF

To A/D Converter

Note 1: I/O pins have diode protection to VDD and VSS.

2004 Microchip Technology Inc.

DS39609B-page 117

PIC18F6520/8520/6620/8620/6720/8720
FIGURE 10-14: RF6:RF3 AND RF0 PINS BLOCK DIAGRAM FIGURE 10-15: RF7 PIN BLOCK DIAGRAM

RD LATF Data Bus WR LATF or WR PORTF

RD LATF Data Bus D Q VDD CK Q P WR LATF or WR PORTF

Q I/O pin

CK Data Latch D Q Schmitt Trigger Input Buffer TTL Input Buffer

Data Latch D WR TRISF Q N I/O pin WR TRISF CK Q VSS Analog Input Mode

CK TRIS Latch

TRIS Latch

RD TRISF RD TRISF Q D EN EN EN RD PORTF SS Input To A/D Converter or Comparator Input Note 1: I/O pins have diode protection to VDD and VSS. Note: I/O pins have diode protection to VDD and VSS. RD PORTF ST Input Buffer

DS39609B-page 118

2004 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720
TABLE 10-11: PORTF FUNCTIONS
Name RF0/AN5 RF1/AN6/C2OUT RF2/AN7/C1OUT RF3/AN8 RF4/AN9 RF5/AN10/CVREF RF6/AN11 RF7/SS Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Buffer Type ST ST ST ST ST ST ST ST/TTL Function Input/output port pin or analog input. Input/output port pin, analog input or comparator 2 output. Input/output port pin, analog input or comparator 1 output. Input/output port pin or analog input/comparator input. Input/output port pin or analog input/comparator input. Input/output port pin, analog input/comparator input or comparator reference output. Input/output port pin or analog input/comparator input. Input/output port pin or slave select pin for synchronous serial port.

Legend: ST = Schmitt Trigger input, TTL = TTL input

TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF

Name TRISF PORTF LATF ADCON1 CMCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR 1111 1111 xxxx xxxx 0000 0000 --00 0000 0000 0000 0000 0000 CM1 CVR1 CM0 CVR0 Value on all other Resets 1111 1111 uuuu uuuu uuuu uuuu --00 0000 0000 0000 0000 0000

PORTF Data Direction Control Register Read PORTF pin/Write PORTF Data Latch Read PORTF Data Latch/Write PORTF Data Latch VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 C1INV CIS CVR3 CM2 CVR2 C2OUT C1OUT C2INV

CVRCON CVREN CVROE CVRR CVRSS

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTF.

2004 Microchip Technology Inc.

DS39609B-page 119

PIC18F6520/8520/6620/8620/6720/8720
10.7 PORTG, TRISG and LATG Registers
make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. Note: On a Power-on Reset, these pins are configured as digital inputs.

PORTG is a 5-bit wide, bidirectional port. The corresponding data direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISG bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATG) is also memory mapped. Read-modify-write operations on the LATG register, read and write the latched output value for PORTG. PORTG is multiplexed with both CCP and USART functions (Table 10-13). PORTG pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTG pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to

The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register, without concern due to peripheral overrides.

EXAMPLE 10-7:
CLRF PORTG ; ; ; ; ; ; ; ; ; ; ; ;

INITIALIZING PORTG
Initialize PORTG by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RG1:RG0 as outputs RG2 as input RG4:RG3 as inputs

CLRF

LATG

MOVLW

0x04

MOVWF

TRISG

FIGURE 10-16:

PORTG BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)

PORTG/Peripheral Out Select Peripheral Data Out 0 RD LATG Data Bus WR LATG or WR PORTG
D CK Q Q

VDD P

I/O pin(1) N TRIS Override Logic VSS

Data Latch D Q Q

WR TRISG

CK

TRIS Latch RD TRISG Peripheral Output Enable(2)

Schmitt Trigger
Q D EN

TRIS OVERRIDE Pin RG0 RG1 RG2 Override Yes Yes Yes Peripheral CCP3 I/O USART1 Async Xmit, Sync Clock USART1 Async Rcv, Sync Data Out CCP4 I/O CCP5 I/O

RD PORTG Peripheral Data In

Note 1:

I/O pins have diode protection to VDD and VSS.

RG3 RG4

Yes Yes

2: Peripheral Output Enable is only active if Peripheral Select is active.

DS39609B-page 120

2004 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720
TABLE 10-13: PORTG FUNCTIONS
Name RG0/CCP3 RG1/TX2/CK2 RG2/RX2/DT2 RG3/CCP4 RG4/CCP5 Bit# bit 0 bit 1 bit 2 bit 3 bit 4 Buffer Type ST ST ST ST ST Function Input/output port pin or Capture3 input/Compare3 output/PWM3 output. Input/output port pin, addressable USART2 asynchronous transmit or addressable USART2 synchronous clock. Input/output port pin, addressable USART2 asynchronous receive or addressable USART2 synchronous data. Input/output port pin or Capture4 input/Compare4 output/PWM4 output. Input/output port pin or Capture5 input/Compare5 output/PWM5 output.

Legend: ST = Schmitt Trigger input

TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG

Name PORTG LATG TRISG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR ---x xxxx ---x xxxx ---1 1111 Value on all other Resets ---u uuuu ---u uuuu ---1 1111

Read PORTF pin/Write PORTF Data Latch LATG Data Output Register Data Direction Control Register for PORTG

Legend: x = unknown, u = unchanged

2004 Microchip Technology Inc.

DS39609B-page 121

PIC18F6520/8520/6620/8620/6720/8720
10.8
Note:

PORTH, LATH and TRISH Registers

PORTH is available only on PIC18F8X20 devices.

FIGURE 10-17:

RH3:RH0 PINS BLOCK DIAGRAM IN I/O MODE

RD LATH Data Bus WR LATH or PORTH

PORTH is an 8-bit wide, bidirectional I/O port. The corresponding data direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISH bit (= 0) will make the corresponding PORTH pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATH register, read and write the latched output value for PORTH. Pins RH7:RH4 are multiplexed with analog inputs AN15:AN12. Pins RH3:RH0 are multiplexed with the system bus as the external memory interface; they are the high-order address bits, A19:A16. By default, pins RH7:RH4 are enabled as A/D inputs and pins RH3:RH0 are enabled as the system address bus. Register ADCON1 configures RH7:RH4 as I/O or A/D inputs. Register MEMCON configures RH3:RH0 as I/O or system bus pins. Note 1: On Power-on Reset, PORTH pins RH7:RH4 default to A/D inputs and read as 0. 2: On Power-on Reset, PORTH pins RH3:RH0 default to system bus signals.

I/O pin(1)
CK

Data Latch
D Q

WR TRISH

CK

TRIS Latch RD TRISH

Schmitt Trigger Input Buffer

D EN EN

RD PORTH Note 1: I/O pins have diode protection to VDD and VSS.

FIGURE 10-18:

RH7:RH4 PINS BLOCK DIAGRAM IN I/O MODE

EXAMPLE 10-8:
CLRF PORTH

INITIALIZING PORTH
; ; ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTH by clearing output data latches Alternate method to clear output data latches

RD LATH Data Bus WR LATH or PORTH

CLRF

LATH

I/O pin(1)
CK

MOVLW MOVWF MOVLW

0Fh ADCON1 0CFh

Data Latch
D Q

MOVWF

TRISH

Value used to initialize data direction Set RH3:RH0 as inputs RH5:RH4 as outputs RH7:RH6 as inputs

WR TRISH

CK

Schmitt Trigger Input Buffer

TRIS Latch RD TRISH

D EN EN

RD PORTH To A/D Converter Note 1: I/O pins have diode protection to VDD and VSS.

DS39609B-page 122

2004 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720
FIGURE 10-19: RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE
Q D EN EN

RD PORTH

RD LATD Data Bus WR LATH or PORTH Port I/O pin(1)

0

Data 1
CK

Data Latch

WR TRISH

CK

TRIS Latch RD TRISH External Enable System Bus Control Address Out Drive System To Instruction Register Instruction Read Note 1: I/O pins have diode protection to VDD and VSS.

TTL Input Buffer

2004 Microchip Technology Inc.

DS39609B-page 123

PIC18F6520/8520/6620/8620/6720/8720
TABLE 10-15: PORTH FUNCTIONS
Name RH0/A16 RH1/A17 RH2/A18 RH3/A19 RH4/AN12 RH5/AN13 RH6/AN14 RH7/AN15 Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Buffer Type ST/TTL
(1)

Function Input/output port pin or address bit 16 for external memory interface. Input/output port pin or address bit 17 for external memory interface. Input/output port pin or address bit 18 for external memory interface. Input/output port pin or address bit 19 for external memory interface. Input/output port pin or analog input channel 12. Input/output port pin or analog input channel 13. Input/output port pin or analog input channel 14. Input/output port pin or analog input channel 15.

ST/TTL(1) ST/TTL(1) ST/TTL ST ST ST ST

(1)

Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave Port mode.

TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH

Name TRISH PORTH LATH ADCON1 MEMCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR 1111 1111 xxxx xxxx xxxx xxxx WM1 WM0 0-00 --00 Value on all other Resets 1111 1111 uuuu uuuu uuuu uuuu --00 0000 0-00 --00

PORTH Data Direction Control Register Read PORTH pin/Write PORTH Data Latch Read PORTH Data Latch/Write PORTH Data Latch EBDIS WAIT1 WAIT0

VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000

Legend: x = unknown, u = unchanged, = unimplemented. Shaded cells are not used by PORTH.

DS39609B-page 124

2004 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720
10.9
Note:

PORTJ, TRISJ and LATJ Registers

PORTJ is available only on PIC18F8X20 devices.

FIGURE 10-20:

PORTJ BLOCK DIAGRAM IN I/O MODE

RD LATJ Data Bus WR LATJ or PORTJ

PORTJ is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISJ bit (= 0) will make the corresponding PORTJ pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATJ) is also memory mapped. Read-modify-write operations on the LATJ register, read and write the latched output value for PORTJ. PORTJ is multiplexed with the system bus as the external memory interface; I/O port functions are only available when the system bus is disabled. When operating as the external memory interface, PORTJ provides the control signal to external memory devices. The RJ5 pin is not multiplexed with any system bus functions. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTJ pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. Note: On a Power-on Reset, these pins are configured as digital inputs.

I/O pin(1)
CK

Data Latch
D Q

WR TRISJ

CK

TRIS Latch RD TRISJ

Schmitt Trigger Input Buffer

D EN EN

RD PORTJ Note 1: I/O pins have diode protection to VDD and VSS.

The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register, without concern due to peripheral overrides.

EXAMPLE 10-9:
CLRF PORTJ ; ; ; ; ; ; ; ; ; ; ; ;

INITIALIZING PORTJ
Initialize PORTG by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RJ3:RJ0 as inputs RJ5:RJ4 as output RJ7:RJ6 as inputs

CLRF

LATJ

MOVLW

0xCF

MOVWF

TRISJ

2004 Microchip Technology Inc.

DS39609B-page 125

PIC18F6520/8520/6620/8620/6720/8720
FIGURE 10-21: RJ4:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE
Q D EN EN

RD PORTJ

RD LATJ Data Bus WR LATJ or PORTJ Port 0 Data

CK 1

I/O pin(1)

Data Latch
D Q

WR TRISJ

CK

TRIS Latch RD TRISJ Control Out System Bus Control External Enable Drive System Note 1: I/O pins have diode protection to VDD and VSS.

FIGURE 10-22:

RJ7:RJ6 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE

Q D EN EN

RD PORTJ

RD LATJ Data Bus WR LATJ or PORTJ

D Q

Port

I/O pin(1)
0

Data 1
CK

Data Latch
D Q

WR TRISJ

CK

TRIS Latch RD TRISJ UB/LB Out System Bus Control Note 1: WM = 01 Drive System I/O pins have diode protection to VDD and VSS.

DS39609B-page 126

2004 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720
TABLE 10-17: PORTJ FUNCTIONS
Name RJ0/ALE RJ1/OE RJ2/WRL RJ3/WRH RJ4/BA0 RJ5/CE RJ6/LB RJ7/UB Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Buffer Type ST ST ST ST ST ST ST ST Function Input/output port pin or address latch enable control for external memory interface. Input/output port pin or output enable control for external memory interface. Input/output port pin or write low byte control for external memory interface. Input/output port pin or write high byte control for external memory interface. Input/output port pin or byte address 0 control for external memory interface. Input/output port pin or chip enable control for external memory interface. Input/output port pin or lower byte select control for external memory interface. Input/output port pin or upper byte select control for external memory interface.

Legend: ST = Schmitt Trigger input

TABLE 10-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ

Name PORTJ LATJ TRISJ Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 Value on all other Resets uuuu uuuu uuuu uuuu 1111 1111

Read PORTJ pin/Write PORTJ Data Latch LATJ Data Output Register Data Direction Control Register for PORTJ

Legend: x = unknown, u = unchanged

2004 Microchip Technology Inc.

DS39609B-page 127

PIC18F6520/8520/6620/8620/6720/8720
10.10 Parallel Slave Port
PORTD also operates as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (PSPCON<4>) is set. It is asynchronously readable and writable by the external world through the RD control input pin, RE0/RD/AD8 and the WR control input pin, RE1/WR/AD9. Note: For PIC18F8X20 devices, the Parallel Slave Port is available only in Microcontroller mode.

FIGURE 10-23:

PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT)

Data Bus
D Q

WR LATD or PORTD

CK

RDx pin TTL

Data Latch Q D EN EN TRIS Latch

The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD/AD8 to be the RD input, RE1/WR/AD9 to be the WR input and RE2/ CS/AD10 to be the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port configuration bits, PCFG2:PCFG0 (ADCON1<2:0>), must be set which will configure pins RE2:RE0 as digital I/O. A write to the PSP occurs when both the CS and WR lines are first detected low. A read from the PSP occurs when both the CS and RD lines are first detected low. The PORTE I/O pins become control inputs for the microprocessor port when bit PSPMODE (PSPCON<4>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs) and the ADCON1 is configured for digital I/O. In this mode, the input buffers are TTL.

RD PORTD

RD LATD

One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>)

Read

TTL

RD

Chip Select TTL Write TTL

CS

WR

Note: I/O pin has protection diodes to VDD and VSS.

DS39609B-page 128

2004 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720
REGISTER 10-1: PSPCON REGISTER
R-0 IBF bit 7 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read IBOV: Input Buffer Overflow Detect bit 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode Unimplemented: Read as 0 Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown R-0 OBF R/W-0 IBOV R/W-0 PSPMODE U-0 U-0 U-0 U-0 bit 0

bit 6

bit 5

bit 4

bit 3-0

FIGURE 10-24:

PARALLEL SLAVE PORT WRITE WAVEFORMS

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CS WR RD PORTD<7:0> IBF OBF PSPIF

2004 Microchip Technology Inc.

DS39609B-page 129

PIC18F6520/8520/6620/8620/6720/8720
FIGURE 10-25: PARALLEL SLAVE PORT READ WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CS WR RD PORTD<7:0> IBF OBF PSPIF

TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Name PORTD LATD TRISD PORTE LATE TRISE PSPCON INTCON PIR1 PIE1 IPR1 Legend: Note 1: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 PSPMODE INT0IE TXIF TXIE TXIP RBIE SSPIF SSPIE SSPIP Read PORTE pin/ Write PORTE Data Latch LATE Data Output bits PORTE Data Direction bits TMR0IF CCP1IF CCP1IE CCP1IP INT0IF TMR2IF TMR2IE TMR2IP RBIF TMR1IF TMR1IE TMR1IP 0000 0000 xxxx xxxx 1111 1111 0000 ---0000 0000 0000 0000 0000 0000 0111 1111 IBOV TMR0IF RCIF RCIE RCIP Value on all other Resets uuuu uuuu uuuu uuuu 1111 1111 0000 0000 uuuu uuuu 1111 1111 0000 ---0000 0000 0000 0000 0000 0000 0111 1111

Port Data Latch when written; Port pins when read LATD Data Output bits PORTD Data Direction bits IBF GIE/ GIEH PSPIF(1) PSPIE(1) PSPIP(1) OBF PEIE/ GIEL ADIF ADIE ADIP

x = unknown, u = unchanged, = unimplemented, read as 0. Shaded cells are not used by the Parallel Slave Port. Enabled only in Microcontroller mode for PIC18F8X20 devices.

DS39609B-page 130

2004 Microchip Technology Inc.