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SERVICE MANUAL FOR 8515

BY: Guangna Zhang Technical Maintenance Department/GTK MTC Oct.2007/R02

8515 N/B Maintenance


Contents
1. Hardware Engineering Specification .
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1.1 Introduction 3 1.2 System Hardware Parts .... 5

t t n e e r c m 2. System View and Disassembly .... e u S c c Do a iT ial M t . 3. Definition & Location of Connectors/Switches n e id f nComponents ... 4. Definition & Location of Major o C
5. Pin Description of Major Component ...

1.3 Other Functions ..... 39 1.4 Peripheral Components 45 1.5 Power Management ... 47
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2.1 System View 50 2.2 Tools Introduction .. 53 2.3 System Disassembly 54


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3.1 Mother Board ................. 72


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4.1 Mother Board ................ 74


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5.1 Intel Merom Processor CPU . 76 5.2 VIA VN896 North Bridge .. 81 5.3 VIA VT8237A South Bridge . 85
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Contents
6. System Block Diagram . 93 7. Trouble Shooting .
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7.1 No Power . 96 7.2 No Display .. 101 7.3 Graphics Controller Test Error LCD No Display ...... 104 7.4 External Monitor No Display 106 7.5 Memory Test Error .... 108 7.6 Keyboard (K/B) or Touch-Pad (T/P) Test Error .... 110 7.7 Hard Disk Drive Test Error . 112 7.8 ODD Drive Test Error ... 115 7.9 USB Port Test Error .. 117 7.10 Audio Test Error .. 119 7.11 LAN Test Error .... 122 7.12 Mini Express (Wireless) Socket Test Error ... 124 7.13 Express Card Socket Test Error ..... 126

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8. Reference Material 128

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1. Hardware Engineer Specification
1.1 Introduction
The 8515 motherboard implements CORE 2 DUO processor for mobile, 667 MT/s (667 MHz) and 800 MT/s (800 MHz) FSB support. 478-pin Micro-FCPGA packages. 8515 platform implements VN896CE/VT8237A core logic. The VN896CE integrates VIAs most advanced system controller with high-performance UniChrome Pro 3D/2D graphics and video controller, LCD panel and TV-Out interfaces. The VN896 provides superior performance between the CPU, PCIe, DRAM, V-link and internal AGP 8x graphics controller with pipelined, burst and concurrent operation. The VN896CE supports 800/667 MHz FSB Intel Pentium M/Merom super-scalar processors. The VN896CE implements a deep In-Order Queue and supports Intel Hyper-Threading Technology to maximize system performance for multithreaded software applications. The VN896 supports 64-bit memory data bus access and up to 2 double-sided DDR2 667 / 533 for 4 GB maximum physical memory. The VN896CE includes a PCI Express 1.0a compliant PCI Express controller, which supports up to two high bandwidth PCIe ports. A 16-Lane port, with up to 4 GB/sec bidirectional data transfer rate, is implemented to support high-end PCI Express compliant graphics controller, and another 1-Lane port designed for PCIe peripheral devices. The VN896CE North Bridge interfaces to the South Bridge through a high speed (up to 533 MB/sec) 8x 66 MHz Data Transfer interconnect bus called V-link interface.

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The VT8237A integrates extensive peripheral controllers for modern, state-of-the-art PC systems: Dual-channel serial ATA/RAID controller Dual-channel enhanced IDE controller IEEE 802.3 compliant 10/100 Mbps Ethernet MAC with MII interface to external PHY receiver Universal serial bus controller with eight USB 2.0 ports Full System Management Bus (SMBus) interface Keyboard controller with PS/2 mouse support Real time clock with 256 bytes extended CMOS Power management unit compliant with ACPI and legacy APM requirements Plug and play functions with steerable PCI interrupts User expendable peripheral interface built on 8515 system are 4 USB ports. 8515 system provides a New card/Express card and Mini PCI-E card. User interface includes internal keyboard, touch pad. Realtek ALC268 High Definition (Azalia) Audio Codec based multimedia interface includes built-in stereo speaker, Microphone-in and headphone-out audio jacks. There are two communication VIA VT6103L Ethernet PHY to support RJ-45 LAN jack and Modem module to support Modem RJ11 jack. A full set of software drivers and utilities are available to allow advanced operating systems such as Windows Vista and Windows XP to take full advantage of the hardware capabilities. Features such as bus mastering IDE, plug and play, Advanced Configuration Power Interface (ACPI) with application restart, software-controlled power shutdown. Following chapters will have more detail description for each individual sub-systems and functions.

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1.2 System Hardware Parts
CPU Core Logic System BIOS Mobile Merom Celeron/Pentium M CPU Thermal spec 35 W TDP VIA VN896CE + 8237A chipset Phoenix BIOS 512 KB flash EPROM Include system BIOS Plug & play capability ACPI 0 MB DDRII 533 SDRAM memory on board 2 memory SO-DIMM slots for memory expansion 1.25-inch height memory module supported 200 pins DDRII 533 SDRAM SO-DIMM memory module Support 2048 MB Support 2.5" 60 GB/80 GB/100 GB/120 GB HDD (9.5 mm) 5400/7200 rpm, PATA, SATA I/F Combo/DVD-Dual, super multi (12.7 mm) 15.4" WXGA, resolution: 1280x800 ICS 953009 and DDR buffer ICS 9P956, LVDS ICS MK1707 Internal VIA VN896CE VIA VT1637 VIA VT6103L Power switch TPS2231 Built-in sound system Azalia I/F (HD Audio codec, ALC268) Built-in stereo speaker Sound volume control by S/W 2 CH

Memory

HDD

ODD Display Clock Generator VGA Control LVDS Transmitter LAN Express Card Audio System

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Continue to previous page
6 Kbps (V.92) fax modem (MDC (Azalia I/F)) and 10/100 (Reserved for 1000) Base-TX LAN Wireless LAN Intel (Mini PCI-E Interface IEEE802.11 b, g) Wireless LAN Keyboard Controller (CIR) WINBOND W83L951D USB2.0 x4 (Individual) USB Modem

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1.2.1 CPU Mobile Intel Merom CPU Processor
1.2.1.1 Mobile Intel Merom CPU Processor
Processor support

CORE 2 DUO processor for mobile

667 MT/s (667 MHz) and 800 MT/s (800 MHz) FSB support

On-die, 2-MB second level cache with advanced transfer cache architecture shared between the two cores Advance gunning transceiver logic (AGTL +) bus driver technology
frequency points

Enhanced Intel speed step technology to enable real-time dynamic switching between multiple voltage and Source synchronous double-pumped (2) address Source synchronous quad-pumped (4) data Other key feature are:

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Support for DBI (Data Bus Invor ersion) Support for MSI (Message signaled interrupt)
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32-bit interface to address up to 4 GB of memory A12 deep In-Order Queue to pipeline FSB commands AGTL+ bus driver with integrated AGLT termination resist 478-pin Micro-FCPGA and 49-ball Micro-FCBGA packages VCCA 1.5 V VCCP 1.05 V

Merom based Intel Pentium M Processor Feature

On-die 1 MB second level cache with advance transfer cache architecture shared between the two cores 478-pin Micro-FCPGA packages VCCA 1.5 V VCCP 1.05 V

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1.2.2 Clock Generator
1.2.2.1 ICS 953009 System Frequency Synthesizer
Recommended Application

VIA VN896CE systems using Intel Merom processors


Output Features

2 0.7 V current-mode differential CPU pairs

1 0.7 V current-mode differential CPU/PCI-Express selectable pair 7 PCI, 33 MHz

2 REF, 14.318 MHz

3 3 V66, 66.66 MHz 1 48 MHz 1 24/48 MHz

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5 PCI-Express 0.7 V current mode differential pairs

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Features/Benefits

Programmable output frequency Programmable asynchronous 3 V66&PCI frequency Programmable asynchronous PCI-Express frequency Programmable output divider ratios Programmable output skew

Programmable spread percentage for EMI control

Watchdog timer technology to reset system if system malfunctions Programmable watch dog safe frequency

Support I2C index read/write and block read/write operations

Uses external 14.318 MHz reference input, external crystal load caps are required for frequency tuning

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1.2.2.2 DDR II Buffer ICS 9P956 System Frequency Synthesizer
Low skew, fanout buffer I2C for functional and output control Single bank 1-6 differential clock distribution

1 pair of differential feedback pins for input to output synchronization Supports up to 2 DDR DIMMs

667 MHz DDR II output frequency support Switching characteristics

Output Output skew: <100 ps

Output rise and fall time for DDR outputs: 650 ps 950 ps Duty cycle: 47% - 53%

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1.2.2.3 VIA VN896CE North Bridge
Defines highly integrated solutions for value notebook PC designs

High performance UMA north bridge: Integrated VIA C7 and Intel Pentium M north bridge with 800 / 667/
533 / 400 MHz FSB support. PCI express bus controller and UniChrome Pro 3D / 2D graphics & video controllers in a single chip

Advanced 64-bit SDRAM controller supporting DDR2 667/533 and DDR 400/333/266/200 SDRAM Combines with VIA VT8237A/VT8237R plus for 10/100 LAN, ATA133 IDE, LPC, USB 2.0, serial ATA
and high definition audio (VT8237A)

37.5x37.5 mm HSBGA package (Ball grid array with heat spreader) with 952 balls and 1.00 mm ball pitch
CPU interface

Supports 800/667/533/400 MHz FSB VIA C7 and Intel Pentium M processors Supports Intel hyper-threading technology Supports DBI (Dynamic Bus Inversion) Supports trust configuration cycle Deep In-order Command Queue (IOQ)

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Integrated CPU-to-DRAM write buffers and CPU-to-DRAM read prefetch buffers


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Built-in phase lock loop circuitry for optimal skew control within and between clocking regions
Memory interface

Supports DDR2 mode Supports DDR2 667/533 memory Supports mixed 64/128/256/512/1024/2048x8/16 DDR2 SDRAMs

Supports 2 unbuffered double-sided DIMMs and up to 4 GB of physical memory Supports CL 2/3/4/5 for DDR2 667/533

Programmable I/O drive capability for memory address, data and control signals DRAM interface pseudo-synchronous with host CPU for optimal memory performance Concurrent CPU, PCIe, internal graphics controller and V-link access for minimum memory access latency Rank interleave and up to16-bank page interleave (i.e., 16 pages open simultaneously) based on LRU to
effectively reduce memory access latency

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Seamless DRAM command scheduling for maximum DRAM bus utilization (e.g., precharge other banks while
accessing the current bank)

CPU read-around-write capability for non-stalled operation


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Speculative DRAM read before snoop result to reduce PCI master memory read latency Supports Burst Read and Write operations with burst length of 4 or 8 Optional dynamic Clock Enable (CKE) control for DRAM power reduction during normal system state (S0) Supports self-refresh and CAS-before-RAS DRAM refresh with staggered RAS timing
Advanced High Bandwidth PCI Express Interface

Supports PCI express 1.0a

Supports up to two PCI express ports

1st port: A 16-Lane port for high end graphics interface. Configurable lane width, 16/8/4/2/1, through hand-shaking for transfer rate up to 4 GB/sec bi-directional Supports two upstream virtual channels 2nd port: A 1-Lane port for peripheral devices

Supports interconnect power management Supports polarity reversal Supports trust configuration cycle Supports hot plug

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Loop-back testing mode for easy debugging mode for PCI express
High bandwidth 533 MB/sec 8-bit V-link host controller

Supports 66 MHz, 4x and 8x transfer modes, V-link interface with 533 MB/sec total bandwidth Half duplex transfers with separate command/strobe for 4x 8-bit mode and full duplex for 8x 4-bit mode Request/data split-transaction

Transaction assurance for V-link host-to-client access eliminates V-link host-client retry cycles Intelligent V-link transaction protocol to minimize data wait-state and throttle transfer latency to avoid data
overflow

Highly efficient V-link arbitration with minimum overhead


Integrated graphics with 2D/3D/video controllers

Optimized Unified Memory Architecture (UMA) Supports 16/32/64 MB frame buffers size

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Graphics engine clocks up to 333 MHz decoupled from memory clock Internal AGP 8x performance
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Two 128-bit internal data paths between north bridge and graphics core for frame buffer and texture/command
access 2D acceleration features

128-bit 2D graphics engine Supports ROP3, 256 operations

Supports 8 bpp, 15/16 bpp and 32 bpp color depth modes

BitBLT (Bit Block Transfer) functions including alpha BLTs Color expansion, source color key and destination color key Bresenham line drawing/style line function Transparency mode

3D acceleration features

3D graphics processor

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- 128-bit 3D graphics engine - Dual pixel rendering pipes - Dual texture units
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- Floating-point setup engine - Internal full 32-bit ARGB format for high rendering quality - 8 K texture cache - Linear address Capability

- Supports ROP2

- Supports various texture formats, including: 16/32 bbp ARGB, 8 bbp palletized (ARGB), YUV 422/420
and compressed texture (DXTC)

- Texture sizes up to 2048x2048

- High quality texture filter for Nearest, Linear, bi-linear, tri-linear and anisotropic modes - Flat and gouraud shading - Vertex fog and fog table

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- Z-Bias, LOD-Bias, polygon offset, edge anti-aliasing and alpha blending - Bump mapping and cubic mapping - Hardware back-face culling
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- Specular Lighting - 16/32-bit Z test and 24+8 Z+ stencil test support Performance - Two textures per pass - Triangle rate up to 4.5 million polygons per second

- Pixel rate up to 400 million pixels per second for 2 textures each - Texel bilinear fill rate up to 266 million texels per second - High quality dithering

Extensive display support for external video output

A dedicated CRT interface

Supports three 12-bit digital video ports

- Multiplexed DVP0 and DVP1 for LVDS transmitter - Dedicated DVP2 for TV encoder CRT display

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- CRT display interface with 24-bit true-color RAMDAC up to 300 MHz pixel rate with gamma correction
capability

- Supports CRT resolutions up to 2048x1536 at 75 Hz 12-bit DDR/18-bit/24-bit LVDS transmitter interface for LCD panel - 12-bit DDR and clock rate up to 165 MHz

- Built-in digital phase adjuster to fine tune signal timing between clock and data bus
Advanced system power management support

ACPI 2.0 and PCI bus power management 1.1 compliant

Supports suspend-to-DRAM (STR) and DRAM self refresh

Supports dynamic Clock Enable (CKE) control for DRAM power reduction during normal system state (S0) Supports SMI, SMM and STPCLK mechanisms Supports enhanced Intel Speedstep technology Low-leakage I/O pads
Advanced graphics power management support

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Built-in reference voltage generator and monitor sense circuits Automatic panel power sequencing and VESA DPMS (Display Power Management Signaling) CRT power-down External I/O signal controlling enabling graphics accelerator into standby/suspend-off state Auto clock gating for each engine to achieve power saving

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High bandwidth 1 GB/sec ultra V-link controller Half duplex, with 16-bit data bus, in 4x mode Request/data split transaction

I2C serial bus and DDC monitor communications for CRT plug-and-play configuration

Supports 16-bit, 66 MHz, 4x and 8x transfer modes, Ultra V-link interface with 1 GB/sec maximum bandwidth Full duplex, with separate 8-bit Up and Down data path and command/strobe, in 8x mode

Transaction assurance for V-link host to client access eliminates V-link host-client retry cycles Intelligent V-link transaction protocol to minimize data wait-state, throttle transfer latency to avoid data overflow Highly efficient V-link arbitration with minimum overhead
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Dual channel serial ATA/RAID controller

Complies with serial ATA specification revision 1.0 Dual Channel master mode PCI On-chip two-channel Serial ATA (S-ATA) PHY for support of up to two S-ATA devices directly S-ATA devices can be configured in multiple RAID configurations supports RAID Level 0, RAID Level 1
and JBOD

S-ATA drive transfer rate is capable of up to 150 MB/s per channel (serial speed of 1.5 Gbit/s) External crystal input for serial ATA port operation Supports defer spin up and port multiplier
High definition (HD) audio controller

High definition audio controller with 192 KHz sample rate, 24-bit per sample and up to 8 channels Microsoft UAA (Universal Audio Architecture) driver support Up to four independent playback streams and audio codecs Multiple recording channels for array microphone Supports jack sensing/retasking
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Universal serial bus controller

Eight USB 2.0 ports with integrated PHY One USB 2.0 root hub and four USB 1.1 root hubs USB 2.0 and Enhanced Host Controller Interface (EHCI) v1.0 compliant

USB 1.1 and Universal Host Controller Interface (UHCI) v1.1 compatible

Integrated physical layer transceivers with optional over-current detection status on USB inputs Eighteen level (doublewords) data FIFO with full scatter and gather capability Legacy keyboard and PS/2 mouse support One USB 2.0 debug port

Fast Ethernet controller

High performance PCI master interface with scatter/gather and bursting capability Standard MII interface to external PHYceiver 1/10/100 MHz full and half duplex operation Independent 2 K byte FIFOs for receive and transmit
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Flexible dynamically loadable EEPROM algorithm Physical, broadcast, and multicast address filtering using hashing function Magic packet and wake-on-address filtering Software controllable power down
Ultra DMA-133/100/66/33 bus master EIDE controller

Dual channel hard disk controller supporting up to four enhanced IDE devices

Data transfer rate up to 133 MB/sec to cover PIO mode 4, multi-word DMA mode 2 and UltraDMA-133 interface Dual DMA engines for concurrent dual channel operation Full scatter gather capability

Supports ATAPI compliant devices including DVD devices Supports PCI native and ATA compatibility modes

Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 compliant Complete software driver support

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System management bus interface

Compliant with System Management Bus (SMBus) revision 2.0 I2C devices compatible Supports SMBus Address Resolution Protocol (ARP) by using host commands through software Supports slave interface for external SMBus masters to control resume events Supports alert on LAN II through a SMBus-interfaced register
Sophisticated mobile power management

ACPI 2.0 and APM v1.2 Compliant

Supports On Now power management

Supports Intel enhanced SpeedstepTM with dedicated pins Supports PCI Express WAKE suspend resume event

Supports CPU clock throttling and clock stop during ACPI C0 / C1 / C2 / C3 states Supports PCI clock run, Power Management Enable (PME) control, and PCI/CPU clock generator stop control Supports multiple system suspend types: power-on suspends (POS) with flexible CPU/PCI bus reset options,
suspend to DRAM (STR), and suspend to disk (soft-off), all with hardware automatic wake-up
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Multiple suspend power plane controls and suspend status indicators Integrates an idle timer, a peripheral timer and a general purpose timer, plus a 24/32-bit ACPI compliant timer Supports normal, doze, sleep, suspend and conserve modes Global and local device power control Supports system event monitoring with two event classes

Primary and secondary interrupt differentiation for individual channels


for system wake-up

Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open/close 32 general purpose input ports and 32 output ports

Multiple internal and external SMI sources for flexible power management models Enhanced integrated Real Time Clock (RTC) with date alarm, month alarm, and century field Thermal alarm on external temperature sensing circuit I/O pad leakage control
Plug and play functions

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Steerable PCI interrupts Steerable interrupts for integrated peripheral controllers Microsoft Windows XPTM, Windows NTTM, Windows 2000TM, Windows 98TM and plug and play BIOS
compliant Integrated legacy functions

Integrated keyboard controller with PS2 mouse support

Integrated DS12885-style real time clock with extended 256 bytes CMOS RAM and day/month alarm for ACPI Integrated DMA, timer, and interrupt controller

Serial IRQ for docking and non-docking applications Fast reset and gate A20 operation

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1.2.3 VT1637 LVDS Transmitter
Supports single/dual LVDS transmitter function Compatible with TIA/EIA-644 LVDS standard Supports LVDS 18-bit Output

Supports dual channel UXGA panel display Supports 2D dither for 18-bit Panel

Supports DVO input mode with 25 to 165 MHz input clock Programmable input clock and strobe select Narrow bus reduces cable size and cost PLL requires no external components

2.5 V core power for low power consumption 48-pin LQFP package (7x7x1.4 mm) Available for lead-free package

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1.2.4 TI TPS2231 Single-Slot PC Card Power Interface Switch
Meets the express card standard (Express card 34 or express card 54) Available in a 32-pin power PAD HTSSOP (Dual) Compliant with the express card compliance checklists 40C to 85C ambient operating temperature range

Available in a 20-pin TSSOP, a 20-pin QFN, or 24-pin power PAD HTSSOP (Single) Fully Satisfies the express card implementation guidelines Supports systems with wake function TTL-logic compatible inputs

Short circuit and thermal protection

1.2.5 Realtek ALC268 High Definition Audio System


Single-chip multi-bit sigma-delta converters with high S/N ratio

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1 stereo DAC supports 16/20/24-bit PCM format with 44.1/48/96/192 KHz sample rate
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2 stereo ADCs support 16/20-bit PCM format with 44.1/48/96 KHz sample rate Applicable for 2-channel 192 KHz DVD-audio solutions Line-out, HP-out, Line 1, Line 2, MIC1, and MIC2 are stereo input and output re-tasking MONO line level output to subwoofer speaker for 2.1 channel applications High-quality differential CD analog input

External PCBEEP input is applicable, and internal BEEP generator is integrated Power-off CD mode supported (Only in ALC268 & ALC268-LF) Power management and enhanced power saving features Power support: digital: 3.3 V; analog: 3.8 V/5.0 V Selectable 2.5 V/3.75 V VREFOUT

Two jack detection pins (Each designed to detect 4 jacks) Supports 44.1/48/96/192 KHz S/PDIF output Supports 44.1/48/96 KHz S/PDIF input

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48-pin LQFP packages (lead (Pb)-free packages also available)


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Supports external volume knob control External PCBEEP Pass-Through when link is in RESET state (Not supported in the ALC268(D)-VE and ALC268(D)-VE-LF) 64 dB ~ +30 dB with 1 dB mixer gain resolution for finer volume control

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Impedance sensing capability for each re-tasking jack Built-in headphone amplifier for each re-tasking jack Supports external volume knob control Supports GPIO (General Purpose Input/Output) for customized applications Compatible with PC 99 desktop line-out Into 10-KW load Internal gain control, which eliminates external gain-setting resistors 2-W/Ch output power Into 3-W load Input MUX select terminal PC-beep input
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Depop circuitry Stereo input MUX Fully differential input Low supply current and shutdown current

t t n e e r c Universal m e 1.2.7 Keyboard System Winbond W83L951D Keyboard Controller u S c c o a D T l i ia M t n e d i f n o C


Surface-mount power packaging 24-Pin TSSOP power PAD Core logic 8-bit turbo 8052 microprocessor code based, speed up to 24 MHz 256 bytes Internal RAM 64 K bytes embedded programmable flash memory 2 K bytes external SRAM Host interface

Software optional with LPC interface Primary programmable I/O address communication port in LPC mode
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SMBus

Support 2 SMBus interface support master mode


Timers

Support four timer signal with three pre-scalars Timer 1 and 2 shard the same pre-scalar and are free-running only
event counter and pulse width measurement PWM

Timer X and Y have individual pre-scalar and support up to four control modes, free. Running, pulse output,

Support four PWM channels

PWM 0 and 1 are 8-bits and programmable frequency from 62 Hz to 7.5 KHz PWM 2 and 3 are 16-bits and programmable frequency from 6 Hz to 3 MHz
Fan Tachometer

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Support two fan tachometer input


A/D converter

Firmware programmable optional with 10-bit or 8-bit resolution


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Support eight channels
D/A converter

8-bit resolution Support two channels


PS2

Support three hardware PS2 channels

Optional PS2 clock inhibit by hardware or firmware


Keyboard controller

Support 16*8 keyboard matrix-scan, expanding to 18*8 and 20*8


GPIO

Support 104 useful GPIO pins totally and bitaddressable to facility firmware coding
Flash

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Support external on-board 64 K flash via matrix interface (GP0, 1, 3)


CIR
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Support decoding for the NEC consumer IR remote control format
RTC

Real time clock generator with 32.768 KHz input


ACPI

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Support ACPI appliance
Secondary programmable I/O address communication port in LPC mode Package 128 pin QFP and 128 pin LQFP package options 512 K x 8 (4 Mbit) Flexible erase capability

Uniform 4 KByte sectors Uniform 64 KByte overlay blocks Chip-erase for PP mode only
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Single 3.0-3.6 V read and write operations

Real time clock generator with 32.768 KHz input


Superior reliability

Endurance: 100,000 cycles (typical) Greater than 100 years data retention
Low power consumption

Active read current: 6 mA (typical) Standby current: 10 A (typical)

Fast sector-erase/byte-program operation

Sector-erase time: 18 ms (typical) Block-erase time: 18 ms (typical) Chip-erase time: 70 ms (typical)

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Byte-program time: 14 s (typical) Chip rewrite time: 8 seconds (typical)


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Two operational modes

Low Pin Count (LPC) interface mode forin-system operation Parallel Programming (PP) mode for fast production programming
LPC interface mode

5-signal LPC bus interface supporting byte read and write 33 MHz clock frequency operation

WP# and TBL# pins provide hardware write protect for entire chip and/or top boot block Block locking registers for individual block write-lock and lock-down protection JEDEC standard SDP command set

Data# polling and toggle bit for end-of-write detection 5 GPI pins for system design flexibility 4 ID pins for multi-chip selection

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Parallel Programming (PP) mode

11-pin multiplexed address and 8-pin data I/O interface


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Supports fast programming in-system on programmer equipment
CMOS and PCI I/O compatibility

1.2.9 VIA VT6103L 10Base T/100Base TX Integrated Ethernet LAN PHY/Transceiver


Single chip 100Base -TX/10Base -T physical layer solution Dual speed 100/10 Mbps Half and full duplex

MII interface to Ethernet controller

MII Interface to Configuration & Status Auto power saving mode

Auto negotiation: 10/100, full/half duplex

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Meet all applicable IEEE 802.3, 10Base -T and 100Base -Tx standards On chip wave shaping no external filters required Adaptive equalizer
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Baseline wander correction LED outputs

Link status Duplex status Speed status Collision

48 pin SSOP package

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1.3 Other Functions
1.3.1 Hot Key Function
Keys Combination Fn + F1 Fn + F2 Fn + F3 Fn + F4 Fn + F5 Fn + F6 Fn + F7 Fn + F8 Fn + F9 Fn + F10 Fn + F11 Fn + F12 Feature Wireless LAN on/off Meaning Enable or disable wireless LAN function

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Mute off/on Panel off/on Suspend to DRAM/HDD

Volume down Audio volume down Volume up Audio volume up LCD/external CRT switching Rotate display mode in LCD only, CRT only and simultaneously display Brightness down Decreases the LCD brightness Brightness up Increases the LCD brightness

Toggle mute on/off Toggle panel on/off Force the computer into either suspend to HDD or suspend to DRAM mode depending on BIOS setup

1.3.2 Quick Key Function


Internet, e-mail, P1
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1.3.3 Power on/off/suspend/resume Button
1.3.3.1 APM Mode
At APM mode, power button is on/off system power

t t n e e r c m e u S c c Do a iT ial M t n 1.3.4 Cover Switch e id f n o C


1.3.3.2 ACPI Mode None Standby

At ACPI mode, windows power management control panel set power button behavior. You could set "standby", "power off or "hibernate (Must enable hibernate function in power management) to power button function.

Continue pushing power button over 4 seconds will force system off at ACPI mode

System automatically provides power saving by monitoring cover switch. It will save battery power and prolong the usage time when user closes the notebook cover

At ACPI mode there are three functions to be chosen at windows XP power management control panel

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Off Hibernate (Must enable hibernate function in power management)

1.3.5 LED Indicators

t t n e e r c m 1.3.5.1 Six LED Indicators Above Keyboard e u S c c Do a iT ial M t n e id f n o C


WLAN power status On: WLAN power on Off: WLAN power off Power status

System has six status LED indicators to display system activity, which include six above keyboard

From left to right that indicates WLAN, power status, battery charge status, caps lock status, num lock status, HDD/ODD status

On: System power on Off: Suspend to RAM power management mode (Flash rate: 1 Hz)
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Off: System power off
Battery charge status

Green: Battery was fully charged (AC mode) Orange: Battery was under charging (AC mode) Red (Flash): Battery low (Under 10%, battery mode, flash rate: 1 Hz)
CAPS lock status

Green: Active state


NUM lock status

Green: Active state


HDD/ODD status

The LED light green when HDD or ODD is working

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C

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1.3.6 Battery Status
1.3.6.1 Battery Warning
System also provides battery capacity monitoring and gives user a warning so that users have chance to save his data before battery dead. Also, this function protects system from mal-function while battery capacity is low

t t n e e r c m e u S c c Do 1.3.6.2 Battery Low State a iT ial M t n e id f n 1.3.6.3 Battery Dead State o C


System will suspend to HDD after 2 minutes to protect users data

Battery warning: Capacity below 10%, battery capacity LED flashes per second, system beeps per 2 seconds

After battery warning state, and battery capacity is below 5%, system will generate beep sound for twice per second

When the battery voltage level reaches 7.4 volts, system will shut down automatically in order to extend the battery packs' life

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1.3.7 Fan Power on/off Management
1.3.7.1 CPU Fan
FAN is controlled by W83L951D embedded controller-using ADM1032 to sense CPU temperature and W83L951D PWM control fan speed. Fan speed is depended on CPU temperature. Higher CPU temperature will get faster fan speed

t t n e e r c m 1.3.8 CMOS Battery e u S c c Do a iT ial M t n e id f n o C

There is a standard CR2032 3 V 220 mAh lithium coin battery to supply RTC power. When AC in or system main battery inside, CMOS battery consumes no power to save coin batterys life cycle

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1.4 Peripheral Components
1.4.1 LCD Panel
15.4" WXGA, resolution: 1280x800

t t n e e r c m e u S c c Do a 1.4.3 ODD iT ial M t n e id f 1.4.4 DDR SO - DIMM n o C


1.4.2 HDD
Combo/DVD-dual, super multi (12.7 mm) 0 MB DDRII 533 SDRAM memory on board 2 memory SO- DIMM slots for memory expansion 200 pins DDRII 533 SDRAM SO-DIMM memory module

Support 2.5" 60 GB/80 GB/100 GB/120 GB HDD (9.5 mm) 5400/7200 rpm, PATA, SATA I/F

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1.4.5 Keyboard
European keyboard layout 19 mm key pitch/3 mm stroke

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C

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1.5 Power Management
The 8515 system has built in several power saving modes to prolong the battery usage. User can enable and configure different degrees of power management modes via ROM CMOS setup (Booting by pressing F2 key). Following are the descriptions of the power management modes supported

1.5.1 System Management Mode


Full on mode

In this mode, each device is running with the maximal speed. CPU clock is up to its maximum
Doze Mode

In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling.
This can save battery power without loosing much computing capability. The CPU power consumption and temperature is lower in this mode Standby Mode

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C

For more power saving, it turns of the peripheral components. In this mode, the following is the status of each
device

- CPU: Stop grant


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- LCD: Backlight off - HDD: Spin down
Suspend to DRAM

The most chipset of the system is entering power down mode for more power saving. In this mode, the
following is the status of each device

- CPU: Off

- Twister K: Partial off - VGA: Suspend

- PCMCIA: Suspend - Audio: Off

- SDRAM: Self refresh


Suspend to HDD

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C

All devices are stopped clock and power-down. System status is saved in HDD. All system status will be
restored when powered on again

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1.5.2 Battery Only Power off Mode
The 8515 system has built in battery only power off mode to prolong the battery usage. In this mode, Universal Keyboard Controller (KBC) will be power off. In addition, the system leakage current shall be less than 0.5 mA, therefore system power consumption is lower in this mode

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C

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2. System View and Disassembly
2.1 System View
2.1.1 Front View

t t n e e r c m e u S c c Do a iT ial M t 2.1.2 Left-side View n e id f n o C


n Top Cover Latch n Power Jack o USB Port*1 q HP Jack r External MIC Jack s Express Card Socket p Ventilation Openings n p o

r q

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2.1.3 Right-side View
n ODD Drive

2.1.4 Rear View


n Kensington Lock o RJ-11 Connector p RJ-45 Connector q USB Port*2 r CRT Connector s USB Port*1

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C

p n o q r]

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2.1.5 Bottom View
n Battery Park o CPU & DDR2 SO-DIMM & Mini Express Card (Wireless) & HDD

o n

t t n e e r c m e u S c c Do a 2.1.6 Top-open View iT ial M t n e id f n o C


n LCD Screen n o Device LED Indicators q Power Button r Keyboard p Mail/Internet/P1 Button o p q r s Stereo Speaker Set t Internal MIC u Touch Pad s t u t
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2.2 Tools Introduction
1. Screw driver with bit size for notebook assembly & disassembly.

2 mm

2. Auto screw driver for notebook assembly & disassembly.

t t n e e 2 mm r c m e u S c c Do a iT ial M t n e id f n o C
Tooling Auto Screwdriver Tor. 2.0-2.5 kg/cm2 Bit Size #0

Bit Size #0

Screw Size 1. M2.0

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2.3 System Disassembly
The section discusses at length each major component for disassembly/reassembly and show corresponding illustrations.Use the chart below to determine the disassembly sequence for removing components from the notebook. NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the notebook is not turned on or connected to AC power.

NOTEBOOK

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Modular Components LCD Assembly Components Base Unit Components

2.3.1 Battery Pack 2.3.2 Keyboard 2.3.3 CPU 2.3.4 DDR2-SDRAM 2.3.5 HDD Module 2.3.6 ODD Drive 2.3.7 LCD ASSY 2.3.8 LCD Panel 2.3.9 Inverter Board 2.3.10 System Board 2.3.11 Modem Card

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2.3.1 Battery Pack
Disassembly 1. Carefully put the notebook upside down. 2. Take the battery pack out of the compartment (n). (Figure 2-1)

Reassembly

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
n n
Figure 2-1 Remove the battery pack

1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you hear a clicking sound.

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2.3.2 Keyboard
Disassembly 1. Remove the battery pack. (Refer to section 2.3.1 Disassembly) 2. Remove one screw then push firmly to slide the easy start buttons cover to the right (n). Then lift the easy start buttons cover up (o). (Figure 2-2, Figure 2-3)

Figure 2-2 Remove one screw

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C

o n

Figure 2-3 Left the keyboard cover

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3. Slightly lift up the keyboard and disconnect the cable from the system board to detach the keyboard. (Figure 2-4)

Reassembly

1. Reconnect the keyboard cable and fit the keyboard back into place. 2. Replace the keyboard cover and secure with one screw. 3. Replace the battery pack. (Refer to section 2.3.1 Reassembly)

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Figure 2-4 Remove the keyboard

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2.3.3 CPU
Disassembly 1. Remove the battery pack. (Refer to section 2.3.1 Disassembly) 2. Remove four screws fastening the CPU cover. (Figure 2-5) 3. Remove three screws that secure the fan, disconnect the fans power cord from system board and remove four screws fastening the heatsink. (Figure 2-6)

Figure 2-5 Remove four screws

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C

Figure 2-6 Free the heatsink and fan

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4. To remove the existing CPU, loosen the screw by a flat screwdriver, upraise the CPU socket to unlock the CPU. (Figure 2-7)

Reassembly

1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pins into the holes. Tighten the screw by a flat screwdriver to locking the CPU. 2. Connect the fans power cord to the system board, replace the fan and heatsink, then secure with seven screws. 3. Replace the CPU cover and secure with four screws. 4. Replace the battery pack. (Refer to section 2.3.1 Reassembly)

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Figure 2-7 Remove the CPU

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2.3.4 DDR2-SDRAM
Disassembly 1. Remove the battery pack. (Refer to section 2.3.1 Disassembly) 2. Remove four screws fastening the CPU cover. (Refer to section 2.3.3 Disassembly) 3. Pull the retaining clips outwards (n) and remove the SO-DIMM (o). (Figure 2-8)

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Figure 2-8 Remove the SO-DIMM

Reassembly 1. To install the DDR2, match the DDR2's notched part with the socket's projected part and firmly insert the SODIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the DDR2 into position 2. Replace the CPU cover and secure with four screws. 3. Replace the battery pack. (See section 2.3.1 Reassembly)
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2.3.5 HDD Module
Disassembly 1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.3.1 Disassembly) 2. Remove four screws fastening the CPU cover. (Refer to section 2.3.3 Disassembly) 3. Remove one screw fastening the HDD, then slide the HDD module out of the compartment. (Figure 2-9)

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Figure 2-9 Remove HDD module

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4. Remove four screws to separate the hard disk drive from the bracket, remove the hard disk drive. (Figure 2-10)

Reassembly

1. Attach the bracket to hard disk drive and secure with four screws. 2. Slide the HDD module into the compartment and secure with one screw. 3. Replace the CPU cover and secure with four screws. 4. Replace the battery pack. (Refer to section 2.3.1 Reassembly)

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Figure 2-10 Remove hard disk drive

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2.3.6 ODD Drive
Disassembly 1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.3.1 Disassembly) 2. Remove one screw fastening the ODD drive. (Figure 2-11) 3. Insert a small rod, such as a straightened paper clip, into ODD drives manual eject hole (n) and push firmly to release the tray. Then gently pull out the ODD drive by holding the tray that pops out (o). (Figure 2-11)

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
n o
Figure 2-11 Remove the ODD drive

Reassembly 1. Push the ODD drive into the compartment and secure with one screw. 2. Replace the battery pack. (Refer to section 2.3.1 Reassembly)
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2.3.7 LCD ASSY
Disassembly 1. Remove the battery pack, keyboard. (Refer to sections 2.3.1 and 2.3.2 Disassembly) 2. Remove four screws fastening the CPU cover. (Refer to step 2 of section 2.3.3 Disassembly) 3. Remove two hinge covers, then carefully put the notebook upside down. (Figure 2-12) 4. Remove four screws. (Figure 2-13)

Figure 2-12 Remove the hinge covers

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C

Figure 2-13 Remove four screws

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5. Disconnect LCD cable from the system board. Remove two screws to free the LCD assembly. (Figure 2-14)

Reassembly

1. Attach the LCD assembly to the base unit and secure with six screws. 2. Reconnect the LCD cable and replace two hinge covers. 3. Replace the CPU cover and secure with four screws. (Refer to section 2.3.3) 4. Replace the keyboard and battery pack. (Refer to sections 2.3.2 and 2.3.1 Reassembly)

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Figure 2-14 Free the LCD assembly

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2.3.8 LCD Panel
Disassembly 1. Remove the battery, keyboard and LCD assembly. (Refer to section 2.3.1, 2.3.2 and 2.3.7 Disassembly) 2. Remove two screws fastening the LCD cover. (Figure 2-15) 3. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out. Repeat the process until the cover is completely separated from the housing. 4. Remove six screws and disconnect two cables. (Figure 2-16)

Figure 2-15 Remove LCD cover

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C

Figure 2-16 Remove six screws and disconnect two cables

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5. Remove four screws that secure with the LCD bracket. (Figure 2-17) 6. Disconnect the LCD cable to free the LCD panel. (Figure 2-18)

Figure 2-17 Remove four screws

Reassembly

1. Reconnect the LCD cable to the LCD panel. 2. Attach the LCD panels bracket back to LCD panel and secure with four screws. 3. Replace the LCD panel into LCD housing, fasten the LCD panel by six screws. 4. Replace the LCD cover and secure with two screws. 5. Replace the LCD assembly, keyboard, battery pack. (See sections 2.3.7, 2.3.2 and 2.3.1Reassembly)

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C

Figure 2-18 Free the LCD panel

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2.3.9 Inverter Board
Disassembly 1. Remove the battery, keyboard, LCD assembly and LCD panel. (Refer to section 2.3.1, 2.3.2, 2.3.7 and 2.38 Disassembly) 2. Remove three screws and free the inverter board. (Figure 2-19)

Reassembly

1. Fit the inverter board back into place and secure with three screws. 2. Replace the LCD Panel, LCD assembly, keyboard and battery pack. (Refer to sections 2.3.8, 2.3.7, 2.3.2 and 2.3.1 Reassembly)

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Figure 2-19 Remove three screws

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2.3.10 System Board
Disassembly 1. Remove the battery, keyboard, CPU, DDR2, HDD, ODD drive and LCD assembly. (Refer to sections 2.3.1, 2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6 and 2.3.7 Disassembly) 2. Remove fifteen screws and two hex nuts fastening the housing. (Figure 2-20, Figure 2-21)

Figure 2-20 Remove fifteen screws

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C

Figure 2-21 Free the system board

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3. Remove two screws and disconnect the two speakers cables, then free the system board. (Figure 2-22)

Reassembly

1. Replace the system board back into the housing, secure with two screws and reconnect two speakers cables. 2. Replace the top cover into the housing. 3. Secure with fifteen screws and two hex nuts fasten the housing. 4. Replace the LCD assembly, DDR2, ODD, HDD, CPU, keyboard and battery pack. (Refer to previous section reassembly)

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Figure 2-22 Free the system board

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2.3.11 Modem Card
Disassembly 1. Remove the battery, keyboard, CPU, DDR2, HDD, ODD, LCD assembly and system board. (Refer to sections 2.3.1, 2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6, 2.3.7 and 2.3.10 Disassembly) 2. Disconnect the modem cable and remove two screws, then free the modem card. (Figure 2-23)

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Figure 2-23 Remove the modem card

Reassembly 1. Replace the modem card back into the system board and secure with two screws, then reconnect the cable. 2. Replace the system board, the LCD assembly, ODD, HDD, DDR2, CPU, keyboard and battery pack. (Refer to previous section reassembly)
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3. Definition & Location of Connectors/Switches
3.1 Mother Board (Side A)

PJ501 J506

J503

J501

J504

J502 J505 J507

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
J512 J514 J510 J513,J515 J518 J516 J519 PJ502 J511

PJ501 : Power Jack PJ502 : Battery Connector J501 : CRT Connector J502 : RJ11 & RJ45 Connector J503, J506 : USB Port J504 : USB Port*2 J505 : MDC Jump Wire Connector J507 : MDC Connector J510 : SATA HDD Connector J512 : HP Jack J514 : External MIC Jack J513, J515 : DDR2 SO-DIMM Socket J516 : Mini Express (Wireless) Connector J518, J519 : Stereo Speaker Connector

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3. Definition & Location of Connectors/Switches
3.1 Mother Board (Side B)

J4

SW6

SW7

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
SW5 J1 SW2 SW3 SW4 J3 J2

J1 : LCD Inverter Connector J2 : Internal Keyboard Connector J3 : Touch-Pad Connector J4 : Express Card Socket

SW2 : Mail Button SW3 : Internet Button SW4 : P1 Button SW5 : Power Button SW6 : Touch-Pad Left Button SW7 : Touch-Pad Right Button

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4. Definition & Location of Major Components
4.1 Mother Board (Side A)

U507

U513

U512 U506

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
U514

U506 : LAN Controller VT6103L U507 : Intel Merom Socket U512 : Clock Generator ICS953009 U513 : VIA VN896 North Bridge U514 : VIA VT8237A South Bridge

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4. Definition & Location of Major Components
4.1 Mother Board (Side B)

U21

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
U10

U10 : W83L951D Keyboard Controller U21 : System BIOS

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5. Pin Descriptions of Major Components
5.1 Intel Merom Processor CPU -1
CPU Pin Description
Signal Name A[35:3]# Type I/O Description A[35:3]# (Address) define a 2*36-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the Celeron FSB. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted. Note: When paired with a chipset limited to 32-bit addressing, A[35:32] should remain unconnected If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20(A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processors address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. Signals Associated Strobe REQ[4:0]#, A[16:3]# ADSTB[0]# A[35:17]# ADSTB[1]# The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.

CPU Pin Description (Continued)


Signal Name BNR# Type I/O Description BNR# (Block next request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner can not issue any new transactions. BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all Celeron FSB agents. This includes debug or performance monitoring tools. BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must connect the appropriate pins of both FSB agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. BR0# is used by the processor to request the bus. The arbitration is done between Celeron processor (Symmetric Agent) and (G) MCH-M (High Priority Agent). BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. The table defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. The Celeron processor 500 series operates at a 533-MHz system bus frequency (133MHz BCLK[1:0] frequency). BSE[2:0] Encoding for BCLK Frequency BCLK BSEL[2] BSEL[1] BSEL[0] Frequency L L L Reserved L L H 133MHz COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. Refer to the platform design guides for more implementation details.

A20M#

ADS#

I/O

ADSTB[1:0]#

I/O

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
BPM[2:1]# BPM[3,0]# I/O BPRI# I BR0# I/O BSEL[2:0] O COMP[3:0] Analog

BCLK[1:0]

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5.1 Intel Merom Processor CPU -2
CPU Pin Description (Continued)
Signal Name D[63:0]# Type I/O Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the FSB agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#. Quad-Pumped Signal Groups Data Group DSTBN#/DSTBP# DINV# D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]# 3 3 Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high. DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal. DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both FSB agents. DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of both FSB agents.

CPU Pin Description (Continued)


Signal Name DINV[3:0]# Type I/O Description DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. DINV[3:0]# Assignment To Data Bus Bus Signal Data Bus Signals DINV[3]# D[63:48]# DINV[2]# D[47:32]# DINV[1]# D[31:16]# DINV[0]# D[15:0]# DPRSTP# is not used by the Celeron processor. For termination requirements please refer to the platform design guide DPSLP# when asserted on the platform causes the processor to transition from the Sleep state to the Deep Sleep state. In order to return to the Sleep state, DPSLP# must be deasserted. DPSLP# is driven by the ICH8M I/O controller. DPWR# is a control signal used by the chipset to reduce power on the processor data bus input buffers. This is not utilized by the Celeron processor 500 series. DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents. Data strobe used to latch in D[63:0]#. Signals Associated Strobe D[15:0]#, DINV[0]# DSTBN[0]# D[31:16]#, DINV[1]# DSTBN[1]# D[47:32]#, DINV[2]# DSTBN[2]# D[63:48]#, DINV[3]# DSTBN[3]#

DBR#

DBSY#

I/O

DEFER#

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DPRSTP# DPSLP# I I DPWR# I DRDY# I/O DSTBN[3:0]# I/O

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5.1 Intel Merom Processor CPU -3
CPU Pin Description (Continued)
Signal Name DSTBP[3:0]# Type I/O Description Data strobe used to latch in D[63:0]#. Signals Associated Strobe D[15:0]#, DINV[0]# DSTBP[0]# D[31:16]#, DINV[1]# DSTBP[1]# D[47:32]#, DINV[2]# DSTBP[2]# D[63:48]#, DINV[3]# DSTBP[3]# FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# assertion indicates that an unmasked floating point error has been detected. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS* type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. In both cases, assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event. For additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to Volume 3 of the Intel Architecture Software Developers Manual and the Intel Processor identification and CPUID instruction application note. For termination requirements please refer to the appropriate platform design guide. GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 VCCP . GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1.Please refer to the appropriate platform design guide for details on GTLREF implementation. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.

CPU Pin Description (Continued)


Signal Name IGNNE# Type I Description IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT#(Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers, The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output Write Instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction, INIT# must connect the appropriate pins of both FSB agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Selt-Test(BIST). LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration.

FERR#/PBE#

GTLREF

HIT# HITM#

I/O I/O

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INIT# I LINT[1:0] I

IERR#

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5.1 Intel Merom Processor CPU -4
CPU Pin Description (Continued)
Signal Name LOCK# Type I/O Description LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of both FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the FSB,it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock. Probe Ready signal used by debug tools to determine processor debug readiness. Probe Request signal used by debug tools to request debug operation of the processor. As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. TCC will remain active until the system deasserts PRCCHOT#. For termination requirements please refer to the appropriate platform design guide. This signal may require voltage translation on the motherboard. Processor Power Status Indicator signal. This signal is asserted when the processor is in a lower state (Deep Sleep). Please refer to the IMVP-6 Mobile processor and Mobile chipset voltage regulation with power status indicator(PSI) specification for more details on the PSI# signal. PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. Clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout the boundary scan operation. REQ[4:0]#(Request Command) must connect the appropriate pins of both FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[0]#.

CPU Pin Description (Continued)


Signal Name RESET# Type I Description Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents will deassert their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted. There is a 55-(normal) on die pull up resistor on this signal. I RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of both FSB agents. Reserved/ These pins are RESERVED and must be left unconnected on the No Connect board. However, it is recommended that routing channels to these pins on the board be kept open for possible future use. Please refer to the appropriate platform design guide for more details. I SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state. I SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs.

PRDY# PREQ# PROCHOT#

O I I/O

PSI#

PWRGOOD

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RS[2:0]# RSVD SLP# SMI#

REQ[4:0]

I/O

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5.1 Intel Merom Processor CPU -5
CPU Pin Description (Continued)
Signal Name STPCLK# Type I Description STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TEST1 and TEST2 must have a stuffing option of separate pull down resistor to Vss. For testing purposes it is recommended, but not required, to route the TEST3 and TEST4 pins through a ground referenced 55 ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection. Thermal Diode Anode. Thermal Diode Cathode. The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both FSB agents. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. Processor core power supply. Vcca provides isolated power for the internal processor core PLLs. Processor I/O Power Supply.

CPU Pin Description (Continued)


Signal Name Vcc_sense Type O Description Vcc_sense together with Vss_sense are voltage feedback signals to Intel MVP6 that control the 2.1 mohm loadline at the processor die. It should be used to sense or measure power near the silicon with little noise. VID[6:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (Vcc). Unlike some previous generations of processors, these are CMOS signals that are driven by the Celeron processor. The voltage supply for these pins must be valid before the VR can supply Vcc to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. The VR must supply the voltage that is requested by the pins, or disable itself. Vss_sense together with Vcc_sense are voltage feedback signals to Intel MVP6 that control the 2.1mohm loadline at the processor die. It should be used to sense or measure ground near the silicon with little noise.

VID[6:0]

TCK TDI TDO

I I O

TEST1, TEST2 TEST3, TEST4

THERMDA THERMDC THERMTRIP#

Other Other O

TMS TRDY#

I I

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Vss_sense O

TRST# Vcc Vcca Vccp

I I I I

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5.2 VIA VN896 North Bridge -1
CPU Interface Signals
Signal Name HA[31:3]# Type IO Description Host CPU Address Bus. Connect to the address bus of the host CPU. Inputs during CPU cycles and driven by the North Bridge during cache snooping operations. Host Address Strobe. (P4 Host Protocol) Source synchronous strobes used to transfer HA[31:3]# and HREQ[4:0]# at a 2x transfer rate. HADSTB1# is the strobe for HA[31:17]# and HADSTB0# is the strobe for HA[16:3] and HREQ[4:0]#. (V4 Host Protocol) HADSTB0P# / HADSTB0N# are negativeedge going data strobes used to latch HA[30, 16:3]# and HREQ[2:0]# on even and odd data beat transfers respectively. Note: The ball HADSTB0# means HADSTB0P# in V4 Bus. Host CPU Data. These signals are connected to the CPU data bus. Host CPU Dynamic Bus Inversion. Driven along with HD[63:0]# to indicate if the associated signals are inverted or not. Used to limit the number of simultaneously switching signals to 8 for the associated 16-bit data pin group (HDBI3# for HD[63:48]#, HDBI2# for HD[47:32]#, HDBI1# for HD[31:16]#, and HDBI0# for HD[15:0]#). HDBIn# is asserted such that the number of data bits driven low for the corresponding group does not exceed 8. Host CPU Differential Data Strobes. Source synchronous strobes used to transfer HD[63:0]# and HDBI[3:0]# at a 4x transfer rate. HDSTB3P#/HDSTB3N# are the strobes for HD[63:48]# & HDBI3#; HDSTB2P#/HDSTB2N# are the strobes for HD[47:32]# & HDBI2#; HDSTB1P#/HDSTB1N# are the strobes for HD[31:16]# & HDBI1#; and HDSTB0P#/HDSTB0N# are the strobes for HD[15:0]# & HDBI0#. Address strobe: The CPU asserts ADS# in T1 of the CPU bus cycle. Data Bus Busy. Used by the data bus owner to hold the data bus for transfers requiring more than one cycle. Data Ready. Asserted for each cycle that data is transferred.

CPU Interface Signals (Continued)


Signal Name HREQ[4:0]# Type IO Description Request Command. Asserted during both clocks of the request phase. In the first clock, the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second clock, the signals carry additional information to define the complete transaction type. Host Target Ready. Indicates that the target of the processor transaction is able to enter the data transfer phase. Response Signals. Indicates the type of response per the table below: RS[2:0]# Response type RS[2:0]# Response type 000 Idle State 100 Hard Failure 001 Retry 101 Normal Without Response Data 010 Defer 110 Implicit Response Writeback 011 Reserved 111 Normal With Data Data Bus Power Reduction. Request to reduce power on the mobile CPU data bus input buffer. Connect to mobile CPU if used. Bus Request 0. Bus request output to CPU. Priority Agent Bus Request. The owner of this signal will always be the next bus owner. This signal has priority over symmetric bus requests and causes the current symmetric owner to stop issuing new transactions unless the HLOCK# signal is asserted. The VN896 drives this signal to gain control of the processor bus. Block Next Request. Used to block the current request bus owner from issuing new requests. This signal is used to dynamically control the processor bus pipeline depth. Defer. The VN896 uses a dynamic deferring policy to optimize system performance. The VN896 also uses the DEFER# signal to indicate a processor retry response. CPU Reset. Reset output to CPU. External pullup and filter capacitor to ground should be provided per CPU manufacturers recommendations.

HADSTB0P# (HADSTB0#) HADSTB0N# HADSTB1#

IO

HD[63:00]# HDBI[3:0]#

IO IO

HDSTB[3:0]P# HDSTB[3:0]N#

IO

HADS# HDBSY# HDRDY# HHIT#

IO IO IO IO

HHITM# HLOCK#

IO IO

Hit. Indicates that a caching agent holds an unmodified version of the requested line. Also driven in conjunction with HITM# by the target to extend the snoop window. Hit Modified. Asserted by the CPU to indicate that the address is modified in the L1 cache and needs to be written back. Host Lock. All CPU cycles sampled with the assertion of HLOCK# and ADS# until the negation of HLOCK# must be atomic.

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HRS[2:0]# O HDPWR# O HBREQ0# HBPRI# IO O HBNR# IO HDEFER# O CPURST# O

HTRDY#

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5.2 VIA VN896 North Bridge -2
V-Link Signal Descriptions
Signal Name VD[7:0] Type IO Description V-Link Data Bus. During system initialization, VD[7:0] are used to transmit strap information from the South Bridge. Check the strapping table for details. Parity. V-Link Byte Enable. V-Link Command from Client (South Bridge) to Host (North Bridge). V-Link Strobe from Client to Host. V-Link Complement Strobe from Client to Host. V-Link Command from Host (North Bridge) to Client (South Bridge). V-Link Strobe from Host to Client. V-Link Complement Strobe from Host to Client.

DDR SDRAM Memory Controller Signal Descriptions


Signal Name MD[63:0] MA[13:0] MSRAS# MSCAS# MSWE# MBA[2:0] Type IO O O Description Memory Data. These signals are connected to the DRAM data bus. Memory Address. DRAM address lines. Row Address, Column Address and Write Enable Command Indicator Set. Bank Address: defines which bank will receive an ACTIVE, READ, WRITE, or PRECHARGE command. Chip Select. Chip select of each bank. DDR Data Mask. Data mask of each byte lane. DDR Data Strobe. Data strobe of each byte . Clock Enables. Clock enables for each DRAM bank for powering down the SDRAM or clock control for reducing power usage and for reducing heat/temperature in highspeed memory systems. Memory Detect: Strap low for DDR. Strap high for DDR2. On Die Termination. Enables termination resistance internal to the DDR2 SDRAM

VPAR VBE# VUPCMD VUPSTB+ VUPSTB VDNCMD VDNSTB+ VDNSTB

IO IO I I I O O O

Clock Signal Descriptions


Signal Name VCLK Type I

HCLK+

HCLK PEXCLK+ PEXCLK

I I

MCLKO+ MCLKOMCLKI DISPCLKI

O O I I

V-Link Clock. This signal receives the 66 MHz clock used to generate the internal clocks required by V-Link interface between the North Bridge and South Bridge. Host Clock. This signal receives the host CPU clock (100/133/166/200 MHz). This clock is used by all VN896 logic that is in the host CPU domain. Host Clock Complement. Used for Quad Data Transfer on host CPU bus. PCI Express Differential Clock. These signals receive the 100 MHz clock used by the internal PCI Express logic. Multiplied up to 2.5 GHz onchip for use by the integrated PCI Express PHY to transmit/receive data. Memory (SDRAM) Clock. Output from internal clock generator to external memory interface clock buffer (if required for fanout) Memory (SDRAM) Clock Complement. Memory (SDRAM) Clock Feedback. Input from MCLKO. Dot Clock (Pixel Clock) In. Used for external EMI reduction circuit if used. Connect to GND if external EMI reduction circuit not implemented. Dot Clock (Pixel Clock) Out. Used for external EMI reduction circuit if used. NC if external EMI reduction circuit not implemented.

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O MCS[3:0]# O MDQM[7:0]# MCKE[3:0] O MDQS[7:0]+/IO O MEMDET I

Description

MODT[3:0]

CRT and Serial Bus Signal Descriptions


Signal Name Type AO O Description CRTAR, CRTAG, CRTAB CRTHSYNC CRTVSYNC CRTRSET Analog Red/Green/Blue. DAC outputs. Horizontal Sync. Output to CRT. Vertical Sync. Output to CRT.

AI IO IO

DVPSPCLK DVPSPD CRTSPCLK CRTSPD

Reference Resistor. Tie to GND through an external resistor to control the RAMDAC full-scale current value. DVPSPCLK is typically used for I2C communications DVPSPD is typically used for I2C communications Serial Port Clock and Data. Clock for serial data transfer. Data signals used for serial data transfer. It is typically used for CRT display DDC communications.

DISPCLKO

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5.2 VIA VN896 North Bridge -3
PCIe-multiplexed Digital Video Port Interface Signal
Signal Name DVP0D[11:0] DVP1D[11:0] Type O Description 12-Bit LVDS Mode: DVP1D[11:00] is for 12-Bit LVDS Interface. 18-Bit LVDS Mode: DVP0D[11:06, 03:00] and DVP1D[11:10, 07:02] are for 18-Bit LVDS Interface. 24-Bit LVDS Mode: DVP0D[11:00] and DVP1D[11:00] are for 24-Bit LVDS Interface. Horizontal Sync. 24-bit mode or DVP0 in 12-bit mode. Vertical Sync. 24-bit mode or DVP0 in 12-bit mode. Data Enable. 24-bit mode or DVP0 in 12-bit mode. Clock Out. 24-bit mode or DVP0 in 12-bit mode. Horizontal Sync. For DVP1 in 12-bit mode. Vertical Sync. For DVP1 in 12-bit mode. Data Enable. For DVP1 in 12-bit mode.

Power Signal Descriptions (Analog Power/Ground)


Signal Name VCCA33HCK GNDAHCK VCCA33MCK GNDAMCK VCCA33PLL[3:1] GNDAPLL Type P P P P P P Description Power for Host CPU Clock PLL (3.3V 5%). 400 MHz for CPU/DRAM frequencies of multiples of 100, 133, and 200 MHz. Ground for Host CPU Clock PLL. Connect to main ground plane. Power for Memory Clock PLL (3.3V 5%) Ground for Memory Clock PLL. Connect to main ground plane. Power for Graphics Controller PLL (3.3V 5%). Ground for Graphics Controller PLL. Connect to main ground plane. Power for DAC. (3.3V 5%)

DVP0HS DVP0VS DVP0DE DVP0CLK DVP1HS DVP1VS DVP1DE DVP1DET DVP1CLK

O O O O O O O I O

Display Detect. For DVP1 in 12-bit mode. Clock Output. For DVP1 in 12-bit mode.

Dedicated Digital Video Interface Signals


Signal Name DVP2D[11:00] DVP2HS DVP2VS DVP2CLK DVP2TVCLKR/ DVP2DET DVP2DE Type O O O O I O Data Output [11:00]. Horizontal Sync. Vertical Sync. Clock Output. Clock Return. Data Enable.

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VCCA33DAC[2:1] GNDADAC GNDAPEX[2:0] GNDAPEXCK P P P P VCCA33PEX[2:0] VCCA33PEXCK P P
Signal Name Type P VTT

Ground for DAC. Connect to main ground plane. Ground for PCI Express Ports. Ground for PCI Express Clock. Power for PCI Express Port.

Power for PCI Express Clock.

Power Signal Descriptions (Digital Power/Ground)


Description Power for CPU I/O Interface Logic. Voltage is CPU dependent. See Design guide for details. Power for Memory I/O Interface Logic. 2.5V (DDR)/1.8V (DDR2) 5%. Power for V-Link I/O Interface Logic. 1.5V 5% Power for PCIe I/O Interface Logic. 3.3V 5% Power for internal Logic. 1.5V 5%

Description

VCCMEM VCC15VL

VCC33PEX VCC15

VCC33GFX VSUS15 GND

Power for Graphics Display I/O Logic. 3.3V 5% Suspend power. 1.5V 5% Digital Ground. Connect to main ground plane.

VSUS15PEX

PCI Express Suspend Power. 1.5V 5%

LCD Panel Power Control Signal Descriptions


Signal Name LVDSENVDD LVDSENBLT Type O O Enable Panel VDD Power. Enable Panel Back Light. Description

T r u s t e d P la t fo r m M id u le S ig n a l D e s c r ip tio n s
S ig n a l N a m e TCSEN # Ty p e I D e s c r ip tio n T r u s te d C o n f ig u r a tio n S p a c e E n a b le .

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5.2 VIA VN896 North Bridge -4
Reset, Power Control, GPIO, Interrupt and Test Signal Descriptions
Signal Name XIN Type I Description Reference Frequency Input. External 14.31818 MHz clock source. All internal graphics controller clocks are synthesized on chip using this frequency as a reference. Power OK. Connect to South Bridge and Power Good circuitry. Suspend Status. For implementation of the Suspend-to-DRAM feature. Connect to an external pull-up to disable. Reset. Input from the South Bridge chip. When asserted, this signal resets the VN896 and sets all register bits to the default value. The rising edge of this signal is used to sample all power-up strap options. Input from SLP# of South Bridge chip. This signal is used to inform North Bridge when the processor is in C3/C4 state. Busy. Indicates that master cycles are pending in the chip. Used by the power management system to avoid changing the system power state while a master cycle is in progress. General Purpose Output. This signal reflects the state of SRD[0].

Compensation Signal Descriptions


Signal Name VLCOMPP VLCOMPN HGTLCOMPP HGTLCOMPN MEMCOMP PEXCOMP0 PEXREXT0 PEXREXT1 PEXREXT2 PEXCOMP1 PEXCOMP2 Type AI AI AI AI AI V-Link P Compensation. V-Link N Compensation. AGTL P Compensation. AGTL N Compensation. DRAM Compensation. Memory interface IO buffer calibration. PCI Express Port G Compensation 0. PCI Express Port G External Resistor 0. PCI Express Port G External Resistor 1. PCI Express Port 0 Compensation Resistor. PCI Express Port G Compensation 1. PCI Express Port 0 Compensation. Description

PWROK SUSST# RESET#

I I I

CPUSLPIN# BUSY#

I O

GPOUT GPO0 PEXWAKE#

O O OD

PEXPMESCI#

OD

PEXHPSCI#

OD

PEXINTR#

OD

INTA# PEXDET TESTEN#

O I I

General Output Port. When SR1A[4] is cleared, this pin reflects the state of CR5C[0]. PCI Express Wake. Indicates that a system wake event has occurred on the PCI Express bus. Used to waken the chip from deep sleep mode (S3/S4/S5 states). Wire-OR with other system WAKE# signals (including PEWAKE# on the PCI Express bus connector) and connect to the South Bridge PME input. PCI Express PME SCI. System Control Interrupt to indicate Power Management Event. Connect to South Bridge SCI input (GPIO pin). PCI Express Hot-Plug SCI. System Control Interrupt to indicate Hot Plug occurred. Connect to South Bridge SCI input (GPIO pin). PCI Express Interrupt. Connect to South Bridge interrupt input to indicate that an interrupt condition was detected on PCI Express bus or the internal APIC. Interrupt. PCI interrupt output (handled by the interrupt controller in the south bridge). PCI Express Detect. Used to determine the presence of an external PCI Express device Test Enable. This signal is used for testing.

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AI AI AI AI AI AI
Signal Name Type P HGTLVREF[1:0] MEMVREF[1:0] VLVREF P P

Reference Voltage Signal Descriptions


Description Host CPU Interface AGTL+ Voltage Reference. 2/3 VTT 2% typically derived using a resistive voltage divider. See design guide. Memory Voltage Reference. VCCMEM 2% typically derived using a resistive voltage divider. V-Link Voltage Reference. 0.45V / 0.625V 2% derived using a resistive voltage divider.

PC I Express Interface Signals


Signal N am e Type I PEX R X [15:00]+/ PEX T X [15:00]+/ PEX R X 16+/ PEX T X 16+/

D escription

O I O

PC I Express Port G D ifferential R eceive D ata [15:00]. These signals are multiplexed w ith D igital V ideo Port Signal. PC I Express Port G D ifferential Transmit D ata [15:00]. PC I Express Port 0 D ifferential Transm it D ata 0.

PC I Express Port 0 D ifferential R eceive D ata 0.

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5.3 VIA VT8237A South Bridge -1
V-Link Interface Signals
Signal Name VD[15:0] Type IO Description Data Bus. All bits 15-0 are implemented for use with VIA north bridge chips which support this capability (if not, only bits 7-0 are used). VD[7:0] are also used to send strap information to the chipset north bridge (see strap table below for details). The specific interpretation of these straps is north bridge chip design dependent. Parity. If the VPAR function is implemented in a compatible manner on the north bridge, this pin should be connected to the north bridge VPAR. If VPAR is not implemented in the north bridge chip or is incompatible with the VT8237A (4x V-Link north bridges) connect this signal to an 8.2 K pullup to 2.5 V. Byte Enable. Connect to same named pin on north bridge. V-Link Clock. 66 MHz. Supplied by clock gennerator. Command from Client-to-Host. Connect to same named pin on north bridge. Command from Host-to-Client. Connect to same named pin on north bridge. Strobe from Client-to-Host. Connect to same named pin on north bridge. Complement Strobe from Client-to-Host. Connect to same named pin on north bridge. Strobe from Host-to-Client. Connect to same named pin on north bridge. Complement Strobe from Host-to-Client. Connect to same named pin on north bridge.

CPU Interface Signals


Signal Name A20M# Type OD Description A20 Mask. Connect to A20 mask input of the CPU to control address bit-20 generation. Logical combination of the A20GATE input (from internal or external keyboard controller) and Port 92 bit-1 (Fast_A20). Numerical Coprocessor Error. This signal is tied to the coprocessor error signal on the CPU. Internally generates interrupt 13 if active. Ignore Numeric Error. This signal is connected to the CPU ignore error pin. Initialization. The VT8237A asserts INIT# if it detects a shut-down special cycle on the PCI bus or if a soft reset is initiated by the register. CPU Interrupt. INTR is driven by the VT8237A to signal the CPU that an interrupt request is pending and needs service. Non-Maskable Interrupt. NMI is used to force a non-maskable interrupt to the CPU. The VT8237A generates an NMI when PCI bus SERR# is asserted. Sleep. Used to put the CPU to sleep.

FERR#

VPAR

IO

VBE# VCLK UPCMD DNCMD UPSTB+ UPSTBDNSTB+ DNSTB-

IO I O I O O I I

General Purpose Output Interface Signals


Signal Name GPO0 GPO1 GPO2/SUSA# GPO3/SUSST# GPO4/SUSCLK GPO5/CPUSTP# GPO6/PCISTP# GPO7/GNT5# GPO9 Type O O O O O O O O O

General Purpose Output 0. General Purpose Output 1. General Purpose Output 2. General Purpose Output 4.

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IGNNE# INIT# OD OD INTR NMI OD OD SLP# OD SMI# OD STPCLK# OD I THRMTRIP#/GPI1

System Management Interrupt. SMI# is asserted by the VT8237A to the CPU in response to different Power-Management events. Stop Clock. STPCLK# is asserted by the VT8237A to the CPU to throttle the processor clock. Thermal Detect Power Down. This signal is to indicate a thermal trip from the processor.

Serial ATA Interface Signals


Signal Name Type I I SRX0+/ SRX1+/ STX0+/ STX1+/ SXI SXO SATALED# SREXT

Description

Description

SATA Port 0 Differential Receiver. SATA Port 1 Differential Receiver.

O O I

SATA Port 0 Differential Transmitter. SATA Port 1 Differential Transmitter.

General Purpose Output 3. General Purpose Output 5. General Purpose Output 6. General Purpose Output 7. General Purpose Output 9.

SATA Crystal In. SATA Crystal Out. SATA LED SATA External Resistor.

O O AI

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5.3 VIA VT8237A South Bridge -2
PCI Bus Interface Signals
Signal Name AD[31:0] Type IO Description Address/Data Bus. Multiplexed address and data. The address is driven with FRAME# assertion and data is driven or received in following cycles. Command/Byte Enable. The command is driven with FRAME# assertion. Byte enables corresponding to supplied or requested data are driven on following clocks. Device select. The VT8237A asserts this signal to claim PCI transactions through positive or subtractive decoding. As an input, DEVSEL# indicates the response to a VT8237A-initiated transaction and is also sampled when decoding whether to subtractively decode the cycle. Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that one more data transfer is desired by the cycle initiator. Initiator Ready. Asserted when the initiator is ready for data transfer. Target Ready. Asserted when the target is ready for data transfer. Stop. Asserted by the target to request the master to stop the current transaction. System Error. SERR# can be pulsed active by any PCI device that detects a system error condition. Upon sampling SERR# active, the VT8237A can be programmed to generate an NMI to the CPU. Parity Error. PERR#, sustained tri-state, is only for the reporting of data parity errors during all PCI transactions except for a Special Cycle. Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]#. PCI Interrupt Request. The INTA# through INTD# pins are typically connected to the PCI bus INTA#-INTD# pins per the table below. INTE-H# are enabled by setting. BIOS settings must match the physical connection method. INTA# INTB# INTC# INTD# PCI Slot 1 INTA# INTB# INTC# INTD# PCI Slot 2 INTB# INTC# INTD# INTE# PCI Slot 3 INTC# INTD# INTE# INTF# PCI Slot 4 INTD# INTE# INTF# INTG# PCI Slot 5 INTE# INTF# INTG# INTH# PCI Slot 6 INTF# INTG# INTH# INTA#

PCI Bus Interface Signals (Continued)


Signal Name REQ5#/GPI7, REQ4#, REQ3#, REQ2#, REQ1#, REQ0# GNT5#/GPO7, GNT4#, GNT3#, GNT2#, GNT1#, GNT0# PCIRST# PCICLK Type I Description PCI Request. These signals connect to the VT8237A from each PCI slot (or each PCI master) to request the PCI bus

CBE[3:0]#

IO

DEVSEL#

IO

FRAME#

IO

IRDY# TRDY# STOP# SERR#

IO IO IO I

PERR#

PAR INTA# INTB# INTC# INTD# INTE#/GPI12,/ GPO12, INTF#/GPI13,/ GPO13, INTG#/GPI14,/ GPO14, INTH#/GPI15,/ GPO15

IO I

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O O I CLKRUN# IO

PCI Grant. These signals are driven by the VT8237A to grant PCI access to a specific PCI master.

PCI Reset. This signal is used to reset devices attached to the PCI

PCI Clock. This signal provides timing for all transactions on the PCI bus. PCI Bus Clock Run. This signal indicates whether the PCI clock is or will be stopped (high) or running (low). The VT8237A drives this signal low when the PCI clock is running (default on reset) and releases it when it stops the PCI clock. External devices may assert this signal low to request that the PCI clock be restarted or prevent it from stopping.

SMBus Interface Signals


Signal Name Type OD OD SMBCK1 SMBDT1

Description

SMB/I2C Channel 1 Clock. Mater Mode. SMB/I2C Channel 1 Data. Mater Mode. SMB/I2C Channel 2 Clock. Slave Mode. SMB/I2C Channel 2 Data. Slave Mode.

SMBCK2/GPI27/ GPO27 SMBDT2/GPI26/ GPO26 SMBALT#

OD OD I

SMB SMB Alert. Enabled by System Management Bus I/O space. When the chip is enabled to allow it, assertion generates an IRQ or SMI interrupt or a power management resume event.

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5.3 VIA VT8237A South Bridge -3
CPU Speed Control Interface Signals
Signal Name VGATE/GPI8/ GPO8 VIDSEL/GPI28/ GPO28 Type I OD Description Voltage Gate. Signal from the CPU voltage regulator. High indicates the voltage regulator output os stable. Voltage Regulator ID Select. Connected to the CPU voltage regulator. Low selects the voltage ID from the CPU; high selects a different fixed voltage ID (the lower voltage used for CPU deep sleep mode). Voltage Regulator Deep Sleep. Connected to the CPU voltage regulator. High selects the proper voltage for deep sleep mode. CPU Speed Select. Connected to the CPU voltage regulator, used to select high speed (L) or low speed (H). CPU Deep Sleep. Used to put the CPU into a deeper sleep mode. CPU Missing. Used to detect the physical presence of the CPU chip in its socket. High indicates no CPU present. Connect to the CPUMISS signal of the CPU socket. The state of this signal may be read in the SMBus 2 registers. AGP Busy. Low indicates that an AGP master cycle is in progress (CPU speed transitions will be postponed if this input is asserted low). Connected to the AGP Bus AGPBZ# pin.

MII Interface Signals


Signal Name MCOL MCRS MDC MDIO Type I I O IO I Description MII Collision Detect. From the external PHY. MII Carrier Sense. Asserted by the external PHY when the media is active. MII Management Data Clock. Sent to the external PHY as a timing reference for MDIO. MII Management Data I/O. Read from the MDI bit or written to the MDO bit. MII Receive Clock. 2.5 or 25 MHz clock recovered by the PHY.

VRDSLP/GPI29/ GPO29 GHI#/GPI22/ GPO22 DPSLP#/GPI23/ GPO23 CPUMISS/GPI17

OD OD OD I

AGPBZ#/GPI6

APIC Interface Signals


Signal Name APICD1/GPIO11 APICD0/GPIO10 APICCLK/GPI19 Type O O I Internal APIC Data 1. Internal APIC Data 0. Internal APIC Clock.

S er ia l IR O In te r fa c e S ig n a ls
S ig n a l N a m e S E R IR Q Ty p e I

S e ria l IR Q . T h is sig n al h a s a n in te rn a l p u ll-u p re sisto r.

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MRXC MRXD[3:0] MRXDV MRXER MTXC I I I I MTXD[3:0] MTXEN O O PHYRST# O
Description

MII Receive Data. Parallel receive data lines driven by the external PHY synchronous with MRXC. MII Receive Data Valid.

MII Receive Error. Asserted by the PHY when it detects a data decoding error. MII Transmit Clock. Always active 2.5 or 25 MHz clock supplied by the PHY. MII Transmit Data. Parallel transmit data lines synchronized to MTXC. MII Transmit Enable. Signals that transmit is active from the MII port to the PHY. External PHY Reset. PHY Power Down. Output when PHY is in power state as D1 hot, D2 hot or D3 hot with no PME and WOL enable.

PHYPWRDN#

PC/PCI DMA Interface Signals


Signal Name Type I I PCREQA/GPI24/ GPO24 (GPIOA) PCREQB/GPI25/ GPO25 (GPIOB) PCGNTA/GPI30/ GPO30 (GPIOC) PCGNTB/GPI31/ GPO31 (GPIOD)

Description

PC/PCI Request A. PC/PCI Request B.

D es cr ip tio n

O O

PC/PCI Grant A.

PC/PCI Grant B.

Programming Chip Selects Signals


Signal Name PCS0#/AZSDIN2/ GPIO20 PCS1#/AZSDIN3/ GPIO21 Type O Description Programmable Chip Select 0. AZSDIN2 is multiplexed with this pin. PCS0# can optionally be used as GPIO20. Programmable Chip Select 1. AZSDIN3 is multiplexed with this pin. PCS1# can optionally be used as GPIO21.

Low Signal Count Pin Interface Signals


Signal Name LPCAD[3-0] LPCFRAM E# LPCDRQ[1-0]# Type IO O I LPC Address/Data. LPC Frame. LPC DMA/Bus M aster Request 0. Description

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5.3 VIA VT8237A South Bridge -4
USB 2.0 Interface Signals
Signal Name USBP0+/ USBP1+/ USBP2+/ USBP3+/ USBP4+/ USBP5+/ USBP6+/ USBP7+/ USBCLK USBOC0# USBOC1# USBOC2# USBOC3# USBOC4# USBOC5# USBOC6# USBOC7# USBREXT Type IO IO IO IO IO IO IO IO I I I I I I I I I AI Description USB Port 0 Differential Data. USB Port 1 Differential Data. USB Port 2 Differential Data. USB Port 3 Differential Data. USB Port 4 Differential Data. USB Port 5 Differential Data. USB Port 6 Differential Data. USB Port 7 Differential Data.

General Purpose Input Interface Signals


Signal Name GPI0 GPI1/THRMTRIP# GPI2/EXTSMI# GPI3/RING# GPI4/LID# GPI5/BATLOW# GPI6/AGPBZ# GPI7/REQ5# GPI8/GPO8/ VGATE GPI9 Type I I I I I I General Purpose Input 0. General Purpose Input 1. General Purpose Input 2. General Purpose Input 3. General Purpose Input 4. General Purpose Input 5. General Purpose Input 7. General Purpose Input 8. Description

USB Clock. 48 MHz clock input for the USB interface

USB Port 0 Over Current Detect. Port 0 is disabled is disabled of low. USB Port 1 Over Current Detect. Port 1 is disabled is disabled of low. USB Port 2 Over Current Detect. Port 2 is disabled is disabled of low. USB Port 3 Over Current Detect. Port 3 is disabled is disabled of low. USB Port 4 Over Current Detect. Port 4 is disabled is disabled of low. USB Port 5 Over Current Detect. Port 5 is disabled is disabled of low. USB Port 6 Over Current Detect. Port 6 is disabled is disabled of low. USB Port 7 Over Current Detect. Port 7 is disabled is disabled of low. USB External Resistor.

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I I I I GPI16/ INTRUDER# GPI17/CPUMISS GPI18/THRM#/ AOLGPI GPI19/APICCLK I I I I
Signal Name Type IO IO M SCK M SDT KBCK KBDT IO IO

General Purpose Input 6.

General Purpose Input 9. General Purpose Input 16.

General Purpose Input 17. General Purpose Input 18.

General Purpose Input 19.

Internal K eyboard Controller Interface Signals


Description M ouse Clock. From internal mouse controller. M ouse Data. From internal mouse controller. Keyboard Clock. From internal keyboard controller.

Keyboard Data. From internal keyboard controller.

Serial EEPROM Interface Signals


Signal Name SEECS SEECK SEEDO SEEDI Type O O I O Serial EEPROM clock. Serial EEPROM Data Output. Connect to EEPROM Data Out pin. Serial EEPROM Data Input. Connect to EEPROM Data In pin. Description Serial EEPROM chip select.

S peaker Interface Sign als


S ig na l N am e SPK R Typ e O D escrip tion S peaker. Strap lo w to enable (high to disab le) C P U freq uency strap ping.

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5.3 VIA VT8237A South Bridge -5
Enhanced IDE Interface Signals
Signal Name PDIORDY/ PDDMARDY/ PDSTROBE Type I Description EIDE Mode: Primary I/O Channel Ready. Device read indicator UltraDMA Mode: Primary Device DMA Ready. Output flow control. The device may assert PDDMARDY to pause output transfers Primary Device Strobe. Input data strobe (both edges). The device may stop PDSTROBE to pause input data transfers EIDE Mode: Secondary I/O Channel Ready. Device ready indicator UltraDMA Mode: Secondary Device DMA Ready. Output flow control. The device may assert SDDMARDY to pause output transfers Secondary Device Strobe. Input data strobe (both edges). The device may stop SDSTROBE to pause input data transfers EIDE Mode: Primary Device I/O Read. Device read strobe UltraDMA Mode: Primary Host DMA Ready. Primary channel input flow control. The host may assert PHDMARDY to pause input transfers Primary Host Strobe. Output data strobe (both edges). The host may stop PHSTROBE to pause output data transfers EIDE Mode: Secondary Device I/O Read. Device read strobe UltraDMA Mode: Secondary Host DMA Ready. Input flow control. The host may assert SHDMARDY to pause input transfers Second Host Strobe. Output strobe (both edges). The host may stop SHSTROBE to pause output data transfers EIDE Mode: Primary Device I/O Write. Device write strobe UltraDMA Mode: Primary Stop. Stop transfer: Asserted by the host prior to initiation of an UltraDMA burst; negated by the host before data is transferred in an UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst

Enhanced IDE Interface Signals (Continued)


Signal Name SDIOW#/SSTOP Type O Description EIDE Mode: Secondary Device I/O Write. Device write strobe UltraDMA Mode: Secondary Stop. Stop transfer: Asserted by the host prior to initiation of an UltraDMA burst; negated by the host before data is transferred in an UltraDMA burst Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst. Primary Device DMA Request. Primary channel DMA request

SDIORDY/ SDDMARDY/ SDSTROBE

PDIOR#/ PHDMARDY/ PHSTROBE

SDIOR#/ SHDMARDY/ SHSTROBE

PDIOW#/PSTOP

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PDDREQ I SDDREQ I PDDACK# SDDACK# IRQ14 IRQ15 O O I I PDCS1# PDCS3# SDCS1# O O O SDCS3# O PDA[2:0] O SDA[2:0] O PDD[15:0] SDD[15:0] IO IO

Secondary Device DMA Request. Secondary channel DMA request Primary Device DMA Acknowledge. Primary channel DMA acknowledge Secondary Device DMA Acknowledge. Secondary channel DMA acknowledge Primary Channel Interrupt Request. Secondary Channel Interrupt Request. Primary Master Chip Select. This signal corresponds to CS1FX# on the primary IDE connector. Primary Slave Chip Select. This signal corresponds to CS3FX# on the primary IDE connector. Secondary Master Chip Select. This signal corresponds to CS17X# on the secondary IDE connector. Secondary Slave Chip Select. This signal corresponds to CS37X# on the secondary IDE connector. Primary Disk Address. PDA[2:0] are used to indicate which byte in either the ATA command block or control block is being accessed. Strap information is communicated to the north bridge via VD[6:4]. Secondary Disk Address. SDA[2:0] are used to indicate which byte in either the ATA command block or control block is being accessed. Primary Disk Data. Secondary Disk Data.

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5.3 VIA VT8237A South Bridge -6
General Purpose Input/Output Interface Signals
Signal Name GPIO8/VGATE/ SLPBTN# GPIO10/APICD0 GPIO11/APICD1 GPIO12/INTE# GPIO13/INTF# GPIO14/INTG# GPIO15/INTH# GPIO20/AZSDIN2/ PCS0# GPIO21/AZSDIN3/ PCS1# GPIO22/GHI# GPIO23/GPI23/ DPSLP# GPIO24/GPIOA/ PCREQA GPIO25/GPIOB/ PCREQB GPIO26/SMBDT2 GPIO27/SMBCK2 GPIO28/VIDSEL GPIO29/VRDSLP GPIO30/GPIOC/ PCGNTA GPIO31/GPIOD/ PCGNTB Type IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO General Purpose I/O 8. General Purpose I/O 10. General Purpose I/O 11. General Purpose I/O 12. General Purpose I/O 13. General Purpose I/O 14. General Purpose I/O 15. General Purpose I/O 20. General Purpose I/O 21. General Purpose I/O 22.
AZSYNC AZSDOUT AZSDIN0 AZSDIN1 O O I I

High Definition Audio Interface Signals


Signal Name AZRST# AZBITCLK Type O O Description High definition audio reset. High definition audio bit clock. 24MHz High Definition Audio Sync. 48 KHz Frame Sync and outbound tag signal High definition audio serial data output. Bussed serial data output signal 0. High definition audio serial data input 0. Point-to-point serial data input signal 0. High definition audio serial data input 1. Point-to-point serial data input signal 1. High definition audio serial data input 2. Point-to-point serial data input signal 2. AZSDIN2 is multiplexed with PCS0#. AZSDIN2 can optionally be used as GPIO20. High Definition Audio Serial Data Input 3 Point-to-point serial data input signal 3. AZSDIN3 is multiplexed with this pin PCS1#. AZSDIN3 can optionally be used as GPIO21.

Description

General Purpose Output 23. General Purpose I/O A/24. General Purpose I/O B/25. General Purpose I/O 26. General Purpose I/O 27. General Purpose I/O 28. General Purpose I/O 29.

General Purpose I/O C/30.

General Purpose I/O D/31.

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AZSDIN2/PCS0#/ GPIO20 I AZSDIN3/PCS1#/ GPIO21 I
Signal N am e Type AI P V LCO M P V LV REF

C om pensation and R eference V oltage Signal D escription


D escription V-Link Compensation. V-Link Voltage Reference.

Analog Power and Ground (PLL Analog)


Signal Name Type P P Description VCCA25PLL PLL Analog Power. 2.5V 5%. Connect to VCC through a ferrite bead. PLL Analog Ground. Connect to GND through a ferrite bead.

Analog Power and Ground (SATA Controller)


Signal Name VCCA25SXO GNDASXO VCCA25RXSATA VCCA25TXSATA GNDARXSATA GNDATXSATA Type P P P P P P SATA Oscillator Ground. SATA Analog Power. 2.5V 5%. SATA Analog Power. 2.5V 5%. SATA Analog Ground. SATA Analog Ground. Description SATA Oscillator Power. 2.5V 5%.

GNDAPLL

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5.3 VIA VT8237A South Bridge -7
Power Management and Event Signals
Signal Name PWRBTN# Type I Description Power Button. Used by the Power Management subsystem to monitor an external system on/off button or switch. Internal logic powered by VSUS33. Sleep Button. Used by the Power Management subsystem to monitor an external sleep button or switch. Resume Reset. Resets the internal logic connected to the VSUS33 power plane and also resets portions of the internal RTC logic. Internal logic powered by VBAT. External System Management Interrupt. When enabled to allow it, a falling edge on this input causes an SMI# to be generated to the CPU to enter SMI mode. EXTSMI# can optionally be used as GPI2 Power Management Event.

Power Management and Event Signals (Continued)


Signal Name SUSB# Type O Description Suspend Plane B Control. Asserted during power management STR and STD suspend states. Used to control the secondary power plane. Suspend Plane C Control. Asserted during power management STD suspend state. Used to control the tertiary power plane. Also connected to ATX power-on circuitry. Suspend Status 1. Typically connected to the North Bridge to provide information on host clock status. Asserted when the system may stop the host clock, such as Stop Clock or during POS, STR, or STD suspend states. Suspend Clock. It is an output clock of the RTC generator circuit to use by other chips for refresh clock. CPU Missing. Used to detect the physical presence of the CPU chip in its socket. High indicates no CPU present. Connect to the CPUMISS pin of the CPU socket. The state of this pin may be read in the SMBus 2 registers. This signal may be used as CPUMISS and GPI17 at the same time. Alert On LAN. The state of this pin may be read in the SMBus 2 registers. This signal may be used as AOLGPI, GPI18 and THRM# all at the same time.

SLPBTN#/ VGATE/GPIO8 RSMRST#

I I

SUSC#

EXTSMI#/GPI2

IO

PME# SMBALT# LID#/GPI4

I I I

INTRUDER#/ GPI16 THRM#/GPI18/ AOLGPI

I I

RING#/GPI3

BATLOW#/GPI5 CPUSTP#/GPO5 PCISTP#/GPO6 WAKE# SUSA#/GPO2

I O O I O

SMB Alert. When programmed to allow it, assertion generates an IRQ, SMI, or power management event. Notebook Computer Display Lid Open / Closed Monitor. Used by the Power Management subsystem to monitor the opening and closing of the display lid of notebook computers. Can be used to detect either low-to-high or high-to-low transitions to generate an SMI#. LID# can optionally be used as GPI4. Intrusion Indicator. INTRUDER# can optionally be used as GPI16. Thermal Alarm Monitor. This signal is to enable the throttling mode for the duty cycle control of stop clock. AOLGPI is multiplexed with this pin. THRM# can optionally be used as GPI18. Ring Ondicator. May be connected to external modem circuitry to allow the system to be re-activated by a received phone call. RING# can optionally be used as GPI5. Battery Low Indicator. BATLOW# can optionally be used as GPI5. CPU Clock Stop. Signals the system clock generator to disable the CPU clock outputs. Not connected if not used. PCI Clock Stop. Signals the system clock generator to disable the PCI clock outputs. Not connected if not used. For a Wake-up Event. Connect to PCI Express PEWAKE# signal. Suspend Plane A Control. Asserted during power management POS, STR, and STD suspend states. Used to control the primary power plane.

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SUSST#/GPO3 O SUSCLK O I CPUMISS/GPI17 AOLGPI/GPI18/ THRM# I
Signal Name Type I PWRGD PWROK O PCIRST# OSC O I RTCX1 RTCX2 TEST TPO I O I O Test.

Resets, Clock and Power Status Interface Signals


Description Power Good. Connected to the Power Good signal on the Power Supply. Power OK. Internal logic powered by VSUS33.

PCI Reset. Active low reset signal for the PCI bus. The VT8237A will assert this pin during power-up or from the control register. Oscillator. 14.31818 MHz clock signal used by the internal Timer. RTC Crystal Input: 32.768 KHz crystal or oscillator input. RTC Crystal Output: 32.768 KHz crystal output.

Test Pin Output. Output pin for test mode.

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5.3 VIA VT8237A South Bridge -8
Digital Power and Ground
Signal Name VCC25 Type P Description Core Power. 2.5V 5%. This supply is turned on only when the mechanical switch on the power supply is turned on and the PWRON signal is conditioned high. I/O Power. 3.3V 5%. RTC Battery. Battery input for internal RTC (RTCX1, RTCX2). Ground. Connect to primary motherboard ground plane. V-Link Compensation Circuit Voltage. 2.5V 5%. Suspend Power. 2.5V 5%.

VCC33 VBAT GND VCC25VL VSUS25 VSUS33

P P P P P P

VCC33MII VSUS25MII VCC33USB GNDUSB VSUS25USB

P P P P P

Suspend Power. 3.3V 5%. Always available unless the mechanical switch of the power supply is turned off. If the soft-off state is not implemented, then these signal balls can be connected to VCC33. MII Power. 3.3V 5% I/O Power for LAN Media Independent Interface (interface to external PHY). MII Suspend Power. 2.5V 5%. USB Power. 3.3V 5%. USB Ground.

USB Suspend Power. 2.5V 5%.

Analog Power and Ground (USB Controller)


Signal Name VCCA25PLLUSB GNDAPLLUSB Type P P

USB PLL Analog Voltage. Connect to VCC through a ferrite bead. 2.5V 5%. USB PLL Analog Ground. Connect to GND through a ferrite bead.

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Description

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6. System Block Diagram
14.318 MHz

CLOCK GENERATOR ICS953009

U507 CPU Intel Merom


FSB 533/667/800 MHz 15.4 WXGA DVO

Quick Keys E-mail Internet PI (Reserved)

USB 0/1/2/3

PWR S/W G577D5U

NEW CARD

Mini-PCIE Wireless

THM Sensor G781f Fan

12 MHz

Keyboard BIOS WINBOND W83L951D


KEY MATRIX

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DDR2 400/533/667 MHz

U513 North Bridge VIA VN896

VIA VT1637

LVDS

LCD PANEL

RGB

CRT

V-Link 4X/8X 533 MHz

USB

PCI-EXPRESS/USB

PCI-EXPRESS/USB

U514 South Bridge VIA VT8237A

32.768 KHz

CD ROM

PATA

SATA/PATA

HDD

AZALIA

LPC BUS

MII BUS

PHY

10/100 LAN VIA VT6103L

25 KHz

MDC Module

Audio codec ALC268

SYSTEM

BIOS 512 K

6 LEDs AC+Battery, Charger, WLAN, ODD & HDD, Num, Caps


RJ45/RJ11

AMPLIFIER APA2056
EXT MIC HP SPEAKER SPEAKER JACK

PS/2

I-LIMIT

TOUCH PAD

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7. Trouble Shooting
7.1 No Power (*1) 7.2 No Display (*2) 7.3 Graphics Controller Test Error LCD No Display 7.4 External Monitor No Display 7.5 Memory Test Error

7.6 Keyboard (K/B) or Touch-Pad (T/P) Test Error 7.7 Hard Disk Drive Test Error 7.8 ODD Drive Test Error 7.9 USB Port Test Error 7.10 Audio Test Error 7.11 LAN Test Error

7.12 Mini Express (Wireless) Socket Test Error 7.13 Express Card Socket Test Error

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C

94

8515 N/B Maintenance


*1: No Power Definition
Base on ACPI Spec. We define the no power as while we press the power button, the system cant leave S5 status or none the PG signal send out from power supply. Judge condition: Check whether there are any voltage feedback control to turn off the power.

t t n e e r c m *2: No Display Definition e u S c c Do a iT ial M t n e id f n o C


Judge condition: Check which power will cause no display. Check which reset signal will cause no display. Check which Clock signal will cause no display.

Check whether no CPU power will cause system cant leave S5 status.

If there are not any diagram match these condition, we should stop analyzing the schematic in power supply sending out the PG signal. If yes, we should add the effected analysis into no power chapter.

Base on the digital IC three basic working conditions: working power, reset, Clock. We define the no display as while system leave S5 status but cant get into S0 status.

Base on these three conditions to analyze the schematic and edit the no display chapter.

Keyword:
S5: Soft Off S0: Working For detail please refer the ACPI specification.
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8515 N/B Maintenance


7.1 No Power -1
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

No Power

Check following parts and signals:

Is the notebook connected to power (either AC adaptor or battery)?

No

Yes Try another known good battery or AC adapter.

Connect AC adaptor or battery.

Power OK? Yes Replace the faulty AC adaptor or battery.

No

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Where from power source problem (first use AC to power it)? AC Power Replace Motherboard Battery

Parts:

Signals:
+PWR_VDDIN +DVMAIN ADINP LEARNING ADEN# I_LIMIT

U10 PU501 PU506 PF1 PQ1 PQ2 PD4 PD2 PR5 EL545

Check following parts and signals: Parts: Signals:


BATT BATT_T BATT_V BATT_C BATT_D

U10 PU506 PJ502 PF502 PQ516 PD512 PD501 PQ520 PL505

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7.1 No Power -2
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

Main Voltage Map

P27

POWER IN

PF1

PR5 PQ1

PJ501

PD2

P27

+PWR_VDDIN
U9,F2

P21

+VDD3_ALW

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
PF501,EL534,PQ516,PL505 PU506,PD512 P26

PU502,EL523,PQ509,PQ507,PQ508,PQ510 PQ511,PQ512,PL503,PL504

P25

+CPU_CORE

BATT

Charge

PQ520,PR45,PR46, PQ8,PQ7

Discharge

P27

P27

ADINP

PD4

EL514,PU503

+DVMAIN

PQ504A,PQ504B PL501

P24

+3V_P
P24

PQ503,PQ505 PL502

+5V_P

Discharge

PD501

P19

EL544,PU3

PQ519,PQ518,PL506

P23

EL524

+VDD3_KBC_AVREF
P21

+1.8V_P

Q502

P21

+VDD3_AVREF
P11

Q507

+VDD3S

Q504

P21

PR37

P23

+3V

+0.9V_P

EL6

P12

D11

+VDD3S_SB
P19

+VDD3_RTC

EL525

+VDD3S_KBC
P21

U510

+VDD2.5S

NOTE :
P30 : Page 30 on M/B circuit diagram. PD708 : Through by part PD708.

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8515 N/B Maintenance


7.1 No Power -3
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

PD2 EC10QS04 A K

+PWR_VDDIN
PD4 PDS1040 3 PC579 1000P PC583 PC577 1000P 1000P

POWER IN
1 2

PF1 6.5A/32VDC

PD1 PD3 BZV55C24 BZV55C24

EL545 120Z/100M

PJ501

EC1 18P

EC560 18P

P19

U10 KBC W83L951D

35

LEARNING

PR6 0

110

I_LIMIT

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
PQ1 AO4419 3 2 1 8 7 6 5 PR5 0.01

ADINP

+DVMAIN
PR45 100K PC587 1000P

PC589 1000P

PR3 470K

PR1 4.7K

3 4

PR2 4.7K

GND

PC29 470P

PR44 226K

GND

PR4 100K

GND

ADEN#

3 2 1 S PQ520 AO4409 D 8 7 6 5 G

PQ7 DTC144WK

PR46 33K PQ8 2N7002K

PQ2 2N7002K

PJO1 OPENSMT4

GND

BATT
PC582 1000P PC580 1000P

GND

PR7 1M

PR502 10

4 5 6

RS+ RS-

P27

VCC

GND

GND

OUT1

PU501

GND1 2 1 GND0

PC504 0.1U

PR62 0

PR501 10

GND PC502 1U

GND

98

8515 N/B Maintenance


7.1 No Power -4
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

Charge
PQ516 AO4419

P26 ADINP

PF501 TR/3216FF-3A

EL534 120Z/100M

PC556 1000P

PC557 1000P

D CHARGING G S From P19 U10 PC565 0.1U PQ3 2N7002K

PC563 1000P

PR566 10K

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
D G S PC558 4.7U PR556 4.7K PR558 4.7K PC569 4.7U PC571 4.7U PC573 4.7U PD509 B340A PQ514 MMBT2222A PR564 100K PD508 BAS32L BATTERY_TYPE To P19 U10 D G PQ4 DTA144WK S I_CTRL From P19 U10 8,11 PR568 0 12 13 C1,C2 VCC

3 2 1

8 7 6 5

PL505 33UH

BATT
PC570 4.7U PD512 B340A PR24 20K

PC574 1000U

PR22 23.7K

PR21 13.7K

PR20 332K

PQ6 2N7002K

D G S PQ5 2N7002K

P26

2IN+

16 2

2IN+

CHARGING

PR571 47K

OUTPUTCTRL CT RT

1IN-

From P19 U10

5 6

PU506

TL594C
2IN15

FEEDBACK

PR573 6.19K

PR572 2.49K

14

REF

DTC

PJS2 SHORT-SMT3

PR570 10K

PC10 0.01U

PC566 0.1U

REF

PC564 1U PR567 100K

PC567 0.1U

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8515 N/B Maintenance


7.1 No Power -5
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

Discharge
+PWR_VDDIN
8 7 6 5

PD501 EC10QS04

+DVMAIN
3 2 1

ADEN#

+VDD3S_KBC P19
3

U10
1 107 BAT_TEMP BAT_VOLT C68 0.1U 2

Keyboard BIOS

111

+VDD3S_KBC

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
D S PC29 470P PQ520 AO4409 G 4

PR45 100K

ADINP

PR44 226K

PQ7 DTC144WK

PR46 33K

PJ502

PQ8 2N7002K

PF502 TR/SFT-10A 1,2 PC576 0.1U PC578 0.1U

P27

BATT

+VDD3_KBC_AVREF
PR41 4.99K

PC33 0.1U

D9 BAV70LT1

PR576 499K

Battery Connector

R61 22

BATT_T

5 PR43 0

BATT_V

C69 0.1U

R63 22

PC28 0.1U

PR42 20K

PC575 0.1U

PR575 100K

W83L951D
41 42

R42 2.7K

R49 2.7K BAT_CLK BAT_DATA

R48 22 BATT_C BATT_D R41 22

PR48 0

3 4

PR47 0 ZD15 BAV99 +VDD3_KBC_AVREF ZD14 BAV99 +VDD3_KBC_AVREF

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8515 N/B Maintenance


7.2 No Display -1
There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good.
No Display Yes Refer to port error code description section to find out which part is causing the problem.

Monitor or LCD module OK? Yes

No

Replace monitor or LCD.

Make sure that CPU module, DIMM memory are installed Properly.

Display OK? No

Yes

Correct it.

1.Try another known good CPU module, DIMM module. 2.Remove all of I/O device ( HDD, ODD.) from motherboard except LCD or monitor.

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
System BIOS writes error code to port by Mini PCI-E debug card? No Board-level Troubleshooting Parts: Replace Motherboard
U507 U10 U21 U516 U513 U512 U514 U511 J511 X504 SW5 Q10A Q10B Q17A Q17B J4 J516

Check system clock, reset circuit and reference power

Check following parts and signals: Signals:


SMBDATA SMBCLK USBCLK_SB OSC_SB VCLK_SB PCICLK_SB CPU_STOP# STOP_PCI# HCLK_CPU+/PCICLK_KBC PCICLK_FWM PCIECLK_NCARD+/PCIEREQ_NCARD# PCIECLK_MINI+/PCIEREQ_MINI# VCLK_NB PCIECLK_NB+/HCLK_NB+/SB_PWRGD PCI_RESET# KBC_PCIRST# FWM_PCIRST# NB_PCIRST# RSMRST#

Display OK? No

Yes

1. Replace faulty part. 2. Connect the I/O device to the M/B one at a time to find out which part is causing the problem.

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8515 N/B Maintenance


7.2 No Display -2
****** System Clock Check ******
+3VS
EL532 120Z/100M

+VDD3S_SB
Q10B 2N7002DW R98 4.7K R582 4.7K SMBDATA Q10A 2N7002DW

+3.3VS_CLK
1,3.. 48

R84 4.7K

R83 4.7K

+3VS
C573 22U

VCLK_NB

R638 R616 R620 R594 R597 R116

22 33 33 33 33 22

P5 P6

PCIECLK_NB+ PCIECLK_NBHCLK_NB+ HCLK_NB-

U513 North Bridge VIA VN896


19

GUICLK

PCIECLK_NCARD+ PCIECLK_NCARDPCIEREQ_NCARD#

R137 R140

Express Card Connector

P15

18 16

J4
P15

13

PCIECLK_MINI+ PCIECLK_MINIPCIEREQ_MINI#

R624 R628

Wireless LAN Card Connector

11

J516

C579 10P

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
31 27 44 43 54 23 5 R631 22 R589 22 27 R636 22 22

P11
SMBCLK

P12

USBCLK_SB OSC_SB VCLK_SB PCICLK_SB

U514 South Bridge

P8

11

R608

53 4

34

D503 BAT54 D504 BAT54

CPU_STOP#

VIA VT8237A

U512

33

STOP_PCI#

33 33

42 41

36

Clock Generator

51

R600

33

HCLK_CPU+

P3

U507 CPU Intel Merom

33 33

38

ICS953009

37

50

R605

33

HCLK_CPU-

35

17

R623

22

PCICLK_KBC

51

6 1 X504 14.318MHz 2 7 18 R627 22 PCICLK_FWM 31 C578 10P

U10 Keyboard Controller W83L951D


P19 P20

U21

System BIOS

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8515 N/B Maintenance


7.2 No Display -3
****** Power Good & Reset Circuit Check ******
JL501 JP_NET10 KBC_PCIRST#

+VDD3_ALW

R543 10K 6 PWRBTN# C13 1000P

R17 1K

P19

U10
50 KBC_RESET# R541 100K 2 1

U508
RESET# GND VCC

KBC W83L951D
29 37 30 53

P21

MN

SB_PWRBTN# SB_PWRGD RSMRST# KBC_PCIRST#

IDE_PCIRST#

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
SW5 P11 P12
1 3 2 4 5 ZJO14

JL506 JP_NET10

FWM_PCIRST#

R508 100

P20
22

U21 System BIOS

U514

+3VS
5

U511 AHC1G08DBV 1 2

P6

SB_PWRGD

+VDD3S_KBC

South

PCI_RESET#

JL505 JP_NET10

NB_PCIRST#

U513 North Bridge VIA VN896

R544 10K

Bridge

C548 0.01U

VIA

JL502 JP_NET10

R286 0

MINIPCIE_PCIRST#

22

P15

J516
Wireless LAN Card Connector

VT8237A

JL504 JP_NET10

+5VS
Q17B DDC144TU Q17A DDC144TU R218 10K R211 33

+5VS

J511
5

R204 10K

P13

ODD Connector

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8515 N/B Maintenance


7.3 Graphics Controller Test Error LCD No Display -1
There is no display or picture abnormal on LCD although power-on-self-test is passed.
Graphics Controller Test Error LCD No Display

1. Confirm LCD panel or monitor is good and check the cable are connected properly. 2. Try another known good monitor or LCD module.

Display OK? No

Yes

Replace faulty LCD or monitor.

Remove all the I/O device & cable from motherboard except LCD panel or extended monitor.

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Parts Replace Motherboard
U513 U504 U514 U10 U6 J1 EL540 EL541 EL542 EL543

Check if J1 is cold solder? No

Yes

Re-soldering.

One of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Signals
LCD_A_TXD0+/LCD_A_TXD1+/LCD_A_TXD2+/LCD_A_CLK+/LTX0+/LTX1+/LTX2+/LCLK+/ENVDD_NB PANEL_ID0/1 LCD_SPCLK LCD_SPD +DVMAIN BLADJ ENABKL_LCD H8_ENABKL +3VS

EL4 EL1 Q5 Q4 ER512 ER513

Display OK? No

Yes

Connect the I/O device & cable to the M/B one at a time to find out which part is causing the problem.

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7.3 Graphics Controller Test Error LCD No Display -2
There is no display or picture abnormal on LCD although power-on-self-test is passed.

J1
P6
ENVDD_NB

U513
LCD_SPCLK

North Bridge VIA VN896

LCD_SPD

P9

U504
16,18,21,24 15,17,20,23

LVDS Encoder VT1637


P11

U514
PANEL_ID0 PANEL_ID1

South Bridge VIA VT8237A

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
LCD_SPD LCD_A_TXD[0..2]-,LCD_A_CLKChange to LCD_A_TXD[0..2]+,LCD_A_CLK+ Change to

ENVDD_NB

1,2

LCD_SPCLK

P10
8

LTX[0..2]-,LCLK-

9,15,21,27

LCD
11,17,23,29

LTX[0..2]+,LCLK+

LCD/Inverter Connector

PANEL_ID0 PANEL_ID1

5 4

Inverter Board
14,16

+D/VMAIN

P19

U10

H8_ENABKL

Change to

ENABKL_LCD

22

KBC W83L951D

BLADJ

BLADJ

24

105

8515 N/B Maintenance


7.4 External Monitor No Display -1
There is no display or picture abnormal on CRT monitor, but it is OK for LCD.

External Monitor No Display

1. Confirm monitor is good and check the cable are connected properly. 2. Try another known good monitor.

Display OK? No

Yes

Replace faulty monitor.

Remove all the I/O device & cable from motherboard except monitor.

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Parts:
U513 U517 U518 J501 Q1A/B EL501 EL502 EL505 EL506 EL507 EL22 EL28

Check if J501 is cold solder?

Yes Re-soldering.

No

One of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Signals:
+5VS +3VS CON_DDDA CON_HSYNC CON_VSYNC CON_DDCK CON_RED CON_GREEN CON_BLUE CRT_BLUE CRT_GREEN CRT_RED CRT_DDC_DATA CRT_DDC_CLK CRT_VSYNC CRT_HSYNC CRT_IN#

Replace Motherboard

Display OK? No

Yes

Connect the I/O device & cable to the M/B one at a time to find out which part is causing the problem.

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7.4 External Monitor No Display -2
There is no display or picture abnormal on CRT monitor, but it is OK for LCD.

CRT_DDC_DATA

P6

CRT_DDC_CLK

U513

CRT_VSYNC

CRT_HSYNC

VIA VN896 North Bridge

CRT_RED

CRT_GREEN

CRT_BLUE

U10 KBC W83L951D

P19

CRT_IN#

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Change to Change to Change to Change to Change to Change to Change to

J501
CON_DDDA 12

P10
CON_DDCK 15

CON_VSYNC

14

External CRT Connector

CON_HSYNC

13

CON_RED

CON_GREEN

CON_BLUE

CRT_IN#

11

107

8515 N/B Maintenance


7.5 Memory Test Error -1
Extend DDR2 SO-DIMM is test error or system hangs up.
Memory Test Error

1. Check the extend SO-DIMM module is installed properly. ( J513, J515) 2. Confirm the SO-DIMM socket (J513, J515) is ok, no band pins.

Test OK? No

Yes

If your system host bus clock running at 533/667 MHZ then make sure that SO-DIMM module meet require of PC4200/PC5400.

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Parts: Correct it. Replace Motherboard
U513 U19 U514 J513 J515 Q10A/B R249 R250 R251 R252 R254 R253 R256 R255

One of the following components or signals on the motherboard may be defective ,Use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement. Signals:
DDR_A_DQ[0..63] DDR_A_DM[0..7] DDR_A_BS[0..2] DDR_A_MA[0..13] DDR_A_RAS# DDR_A_CAS# DDR_A_WE# DDR_CS#[0..3] DDR_CKE[0..3] DDR_ODT[0..3] DDR_A_DQS[0..7] DDR_A_DQS#[0..7] DDR_CLK[0..3]+ DDR_CLK[0..3]SMB_DATA SMB_CLK +1.8V +3VS

Test OK? No

Yes

Replace the faulty DDR2 SODIMM module.

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8515 N/B Maintenance


7.5 Memory Test Error -2
Extend DDR2 SO-DIMM is test error or system hangs up.

P5

J513
DDR_A_DQ[0..63], DDR_A_DQS[0..7], DDR_A_DQS#[0..7] DDR_A_DQ[0..63], DDR_A_DQS[0..7], DDR_A_DQS#[0..7] DDR_A_MA[0..13], DDR_CKE[0..3], DDR_CS#[0..3]

U513 North Bridge VIA VN896

DDR_A_RAS#, DDR_A_CAS#, DDR_A_WE#

DDR_A_DM[0..7], DDR_A_BS[0..2], DDR_ODT[0..3]

P8

DDR_CLK[0,1]+, DDR_CLK[0,1]-

U19 ICS9P956

DDR_CLK[2,3]+, DDR_CLK[2,3]-

P12

U514 South Bridge VIA VT8237A

SMBCLK SMBDATA

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
SMB_DATA SMB_CLK Change to SMB_CLK Change to SMB_DATA

DDR_A_MA[0..13], DDR_CKE[0..3], DDR_CS#[0..3] DDR_A_RAS#, DDR_A_CAS#, DDR_A_WE# DDR_A_DM[0..7], DDR_A_BS[0..2], DDR_ODT[0..3]

P7

DIMM1

DDR_CLK[0,1]+, DDR_CLK[0,1]-

J515
P7 DIMM0

DDR_CLK[2,3]+, DDR_CLK[2,3]-

DDR_A_DQ[0..63], DDR_A_DQS[0..7], DDR_A_DQS#[0..7] DDR_A_MA[0..13], DDR_CKE[0..3], DDR_CS#[0..3] DDR_A_RAS#, DDR_A_CAS#, DDR_A_WE# DDR_A_DM[0..7], DDR_A_BS[0..2], DDR_ODT[0..3]

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7.6 Keyboard (K/B) or Touch-Pad (T/P) Test Error -1
Error message of keyboard or touch-pad test error is shown or any key does not work.
Keyboard(K/B) or Touch-Pad(T/P) Test Error

Is K/B or T/P cable connected to notebook properly?

No

Yes

Try another known good Keyboard or Touch-pad.

Test Ok? No

Yes

Replace the faulty Keyboard or Touch-Pad.

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Correct it. Replace Motherboard Parts
U514 U10 J2 J3 SW6 SW7 EL30 EL31 EL26

Check J2, J3 are cold solder?

Yes Re-soldering.

No

One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement. Signals
+5V KI[0..7] KO[0..15] T_CLK T_DATA TP_CLK TP_DATA TP_LEFT TP_RIGHT LPC_AD[0..3] LPC_FRAME#

110

8515 N/B Maintenance


7.6 Keyboard (K/B) or Touch-Pad (T/P) Test Error -2
Error message of keyboard or touch-pad test error is shown or any key does not work.

P11 P12

LPC_FRAME# SERIRQ LPC_AD[0..3] RSMRST#

U514 South Bridge VIA VT8237A

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
95..102 79..94 77 KI[0..7]

J2
3..10

Internal Keyboard Connector

P19

P19

KO[0..15]

11..26 2

KBD_US/JP

U10

52

54

56..59 30

Keyboard BIOS

W83L951D

J3
11,12 9,10

48 47

T_CLK

Change to

TP_CLK

T_DATA

Change to

TP_DATA

P20

SW6 SW_LEFT
2 4 5

1 3

TP_LEFT

7,8

TP_RIGHT

5,6

SW7

+5V

1,2

1 3

2 4 5

SW_RIGHT

Touch-Pad

111

8515 N/B Maintenance


7.7 Hard Disk Drive Test Error -1
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing data to hard disk.
Hard Disk Drive Test Error

1. Check if BIOS setup is OK?. 2. Try another working drive.

Re-boot OK? No

Yes

Replace the faulty parts.

Check the system driver for proper installation.

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Parts: Replace Motherboard
U514 J510 J509 R269 R268 R267 R266

One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement. Signals:
SATA_RX0+/SATA_TX0+/HDD_DD[0..15] IDE_PDD[0..15] HDD_DA[0..2] IDE_PDA[0..2] IDE_PDCS[1,3]# HDD_DCS[1,3]# IDE_PDACK# HDD_DACK# IDE_PIRDY HDD_IRDY IDE_PIRQ HDD_IRQ HDD_DIOR# IDE_PDIOR# HDD_DREQ IDE_PDREQ IDE_PDIOW# HDD_DIOW#

Re - Test OK? No

Yes End

112

8515 N/B Maintenance


7.7 Hard Disk Drive Test Error -2
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing data to hard disk.

P12

U514

South Bridge

VIA VT8237A

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
SATA_RX0+ SATA_RX0SATA_TX0+ SATA_TX0-

J510
P13

SATA HDD Connector

113

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7.7 Hard Disk Drive Test Error -3
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing data to hard disk.

P11

HDD_DD[0..15] HDD_DREQ

U514 South Bridge VIA VT8237A

HDD_DA[0..2] HDD_DCS1# HDD_IRDY

HDD_DCS3# HDD_IRQ

HDD_DIOW# HDD_DIOR#

HDD_DACK#

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Change to Change to Change to Change to Change to Change to Change to Change to Change to Change to

J509
3,4

+5VS
IDE_PDD[0..15] IDE_PDREQ IDE_PDA[0..2] IDE_PDCS1#

P13

Primary EIDE Connector

27~42 24 9,10,12 8 18 7 14 22 20 20

IDE_PIRDY IDE_PDCS3# IDE_PIRQ IDE_PDIOW# IDE_PDIOR# IDE_PDACK#

114

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7.8 ODD Drive Test Error -1
An error message is shown when reading data from ODD drive.
ODD Drive Test Error

1. Try another known good compact disk. 2. Check install for correctly.

Test OK? No

Yes

Replace the faulty parts.

Check the ODD drive for proper installation.

Re - Test OK? No

Yes

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Parts:
U514 U511 J511 R648 Q17A Q17B

One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement. Signals:
+5VS +3VS ODD_DD[0..15] ODD_DA[0..2] ODD_DCS[1,3]# ODD_DIOR# ODD_DIOW# ODD_DACK# ODD_IRDY ODD_DREQ ODD_RST# ODD_LED# ODD_IRQ

Replace Motherboard

End

115

8515 N/B Maintenance


7.8 ODD Drive Test Error -2
An error message is shown when reading data from ODD drive.

ODD_DD[0..15]

P12

U514

ODD_DA[0..2] ODD_IRQ

ODD_DACK#

South Bridge

ODD_DIOR#

ODD_DIOW# ODD_DREQ

VIA VT8237A

ODD_IRDY

ODD_DCS[1,3]#

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
D5 CL-190G

J511
+5VS
32

D7 BAT54A

+3VS

ODD_LED# 37

P13

ODD_DD[0..15]

6..21

ODD Connector

ODD_RST# Refer Section 8.2(No display-3)

ODD_RST# ODD_DA[0..2] ODD_IRQ ODD_DACK# ODD_DIOR# ODD_DIOW# ODD_DREQ ODD_IRDY ODD_DCS[1,3]#

5 31,33,34 29 28 24 25 22 27 35,36

116

8515 N/B Maintenance


7.9 USB Port Test Error -1
An error occurs when a USB I/O device is installed.
USB Port Test Error

Check if the USB device is installed properly.

Test OK? No

Yes

Correct it.

Replace another known good USB device.

Re-test OK? No

Yes

Correct it.

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Parts:
U514 U505 U4 J504 J506 J503 EL509 EL510 EL521 EL508 EL2 EL516 EL3 EL515

Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Signals:
USBP0+/USBP1+/USBP2+/USBP3+/+5V_USB_1 +5V_USB_2 +5V_USB_3 +5V_USB_4 USB_OC0 USB_OC1 SW_VDD3

Replace Motherboard

117

8515 N/B Maintenance


7.9 USB Port Test Error -2
An error occurs when a USB I/O device is installed.
P14

J503
USBP3USBP32

USB Port

USBP3+

P11
USB_OC1

USBP2-

U514

USBP2+

South Bridge
USBP0USBP0+

VIA VT8237A
USBP1USBP1+

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
U10
Page 19

USBP3+

3 1

+3V U505
VOUT 5 3

+5V_USB_4

+5V

VIN CE

SW_VDD3

P14
GND

FLG

P14

J506
+5V_USB_3 1

USB Port

USBP2-

USBP2+

J504
USBP02 USBP0+ 3

P14 USB Port

USBP1-

A2

USBP1+

A3 1 A1

+3V U4
VOUT 5 3

+5V_USB_1 +5V_USB_2

U10
Page 19

+5V
SW_VDD3

4 1

VIN CE

P14
GND

FLG

USB_OC0

118

8515 N/B Maintenance


7.10 Audio Test Error -1
No sound from speaker after audio driver is installed.
Audio Test error

1. Check if speaker cables are connected properly. 2. Make sure all the drivers are installed properly.

Test OK? No Try another known good speaker, CD-ROM.

Yes

Correct it.

Re-test OK? No

Yes

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting 1.If no sound cause of line out, check the following parts & signals: Parts: Signals:
U10 U14 U17 J519 J518 J512 EL537 EL536 EL539 EL538 EL24 EL27

Check the following parts for cold solder or one of the following parts on the motherboard may be defective,use an oscilloscope to check the following signal or replace parts one at a time and test after each replacement. 2. If no sound cause of MIC, check the following parts & signals: Parts:
U17 U514 U10 U14 J514 EL34 EL35 R236 R231 R238 R226

Signals:
+5VS +3VS MIC1_VREFR MIC1_VREFL MIC1_R MIC1_L MIC_SENSE# ACZ_RST# ACZ_SYNC ACZ_SDIN0 ACZ_BITCLK ACZ_SDOUT

Replace Motherboard

Correct it.

ROUTP/N LOUTP/N HP_OUTR/L HP_SENSE# SPK_OFF AMP_RIGHT AMP_LEFT HP_RIGHT HP_LEFT

119

8515 N/B Maintenance


7.10 Audio Test Error -2 (Audio In)
No sound from speaker after audio driver is installed.

+3VS P12
ACZ_SDIN0 ACZ_SDOUT ACZ_SYNC

U514 South Bridge VIA VT8237A

ACZ_RST# ACZ_BITCLK

SPK_OFF To next page

P19

U10
72 KBC_BEEP Change to

KBC W83L951D

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
13 SENSE_A Change to 1,9 DVDD1,2 32 MIC1_VREFR MIC1_VREFL 8 5

HP_SENSE# From next page MIC_SENSE# MIC1_VREFR MIC1_VREFL

P17

J514
5 4 3 6 2 1 7 8

P17

28

10 11 6

U17

21

MIC1_L

22

MIC1_R

External MIC

Audio Codec

36

AMP_RIGHT

ALC268

AMP_RIGHT To next page

35

AMP_LEFT HP_RIGHT

AMP_LEFT To next page

41

HP_RIGHT To next page

39

HP_LEFT

PC_BEEP

12

PCBEEP

HP_LEFT To next page

120

8515 N/B Maintenance


7.10 Audio Test Error -3 (Audio Out)
No sound from speaker after audio driver is installed.

+5V

AMP_LEFT From previous page AMP_RIGHT From previous page

AMP_LEFT

AMP_RIGHT

HP_RIGHT From previous page HP_LEFT From previous page

HP_RIGHT HP_LEFT

Change to SPK_OFF From previous page

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
19 HVDD

P18

ROUT+ ROUT-

22 21

ROUTP

J519
1 2

ROUTN

P18

U14

J518
1 2

LOUT+ LOUT-

8 9

LOUTP

Internal Speaker Connector

INL_A

LOUTN

P18

INR_A

Audio

4 6

Amplifier APA2056

P18

INR_H INL_H

J512
5 4 3 6 2 1 7 8

HP_SENSE# To previous page

17 18

HP_OUTR HP_OUTL

SPK_OFF#

26

HP Jack

121

8515 N/B Maintenance


7.11 LAN Test Error -1
An error occurs when a LAN device is installed.
LAN Test Error

1.Check if the driver is installed properly. 2.Check if the notebook connect with the LAN properly.

Test OK? No Check if BIOS setup is ok.

Yes

Correct it.

Re-test OK?
No

Yes

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Board-level Troubleshooting Parts: Replace Motherboard
U514 U506 U503 J502 EL518 EL519 X501 R519 RP503

Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Signals:
RJ45_PJ7 RJ45_PJ4 PJRX+/PJTX+/LAN_TXP/N LAN_RXP/N LAN_DATAIO LAN_DCLK LAN_MTXC LAN_MRXD[0..3] LAN_MTXD[0..3] LAN_MTXE LAN_COL LAN_CRS LAN_MRXC LAN_MRXDV LAN_MRXER +3V

Correct it.

122

8515 N/B Maintenance


7.11 LAN Test Error -2
An error occurs when a LAN device is installed.

LAN_DATAIO

LAN_DCLK

P11

LAN_MRXDV

LAN_MRXC

U514

LAN_MRXER

LAN_MRXD[0..3]

South Bridge

LAN_COL

LAN_CRS

VIA VT8237A

LAN_MTXC

LAN_MTXD[0..3]

LAN_MTXE

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
43 20,21,22,23

+3V

44

P16

J502
PJTX+ PJTXPJRX+ PJRX8 7

35

LAN_TXP

10 9 16 15

P16

P16 RJ45 LAN Connector

34

LAN_TXN

6 3

27

LAN_RXP

U506

U503

45..48

26

LAN_RXN

NS681680P

11

R506 75

R503 75

RJ45_PJ4

4,5

15

LAN

EL520 130Z/100M

16

+3V_LAN

14

R505 75 C504 1000P

R504 75

RJ45_PJ7 1,2

Controller

C526 0.1U

40

XI

11..14

39

10

VT6103L

XO

R519 300K

R518 300

C529 22P

X501 25MHZ

C533 22P

123

8515 N/B Maintenance


7.12 Mini Express (Wireless) Socket Test Error -1
An error occurs when a wireless card device is installed.
Mini Express (Wireless) Socket Test Error

1. Check if the wireless card device is installed properly. 2. Confirm wireless driver is installed ok.

Test OK? No Try another known good wireless card device.

Yes

Correct it

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Replace Motherboard Parts:
U512 U513 U514 J516 C605 C605 C606 R653. R654 R655 R656 R657 R658 R659 R624 R628

Board-level Troubleshooting

Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Signals
+3VS PCIEREQ_MINI# PCIECLK_MINI+/SIO_48M PCI_EXP_RX0+/PCI_EXP_TX0+/LPC_AD[0..3] LPC_FRAME# LPC_DRQ#0 SERIRQ LPC_DBG_CLK WLAN_PD# USBP4+/SMB_CLK SMB_DATA

Re-test OK? No

Yes

Change the faulty part then end.

124

8515 N/B Maintenance


7.12 Mini Express (Wireless) Socket Test Error -2
An error occurs when a wireless card device is installed.

J516
P8
24 35 37 38 31 48 SIO_48M PCIEREQ_MINI# PCIECLK_MINI17 7 11 13 30 32

U512

Clock Generator

ICS953009

U513 P6 North Bridge VIA VN896

P11

U514

P12

South Bridge

VIA VT8237A

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
PCIECLK_MINI+ SMB_CLK SMB_DATA MINIPCIE_PCIRST# Refer Section 8.2(No display-3) PCI_EXP_TX0PCI_EXP_TX0+ PCI_EXP_RX0PCI_EXP_RX0+ LPC_AD[0..3] LPC_FRAME# LPC_DRQ#0 SERIRQ WLAN_PD# USBP4USBP4+

P15

Mini Express (Wireless) Connector 125

22

31 33 23 25

37..43 45 47 49 20 36 38

8515 N/B Maintenance


7.13 Express Card Socket Test Error -1
An error occurs when a express card device is installed.
Express Card Socket Test Error

1. Check if the express card device is installed properly. 2. Confirm express card driver is installed ok.

Test OK? No Try another known good express card device.

Yes

Correct it

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
Replace Motherboard Parts:
U512 U513 U514 U516 U20 J4 C322 C333 R278 R693

Board-level Troubleshooting

Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Signals
+3V +3VS +3.3VS_CARD USBP5+/SMB_CLK SMB_DATA PCIEREQ_NCARD# PCIECLK_NCARD+/PCI_EXP_RX16+/PCI_EXP_TX16+/CPUSB# CARD_RST# CPPE# PCIE_WAKE_UP# NCARD_TX16+/-

Re-test OK?

Yes

Change the faulty part then end.

No

126

8515 N/B Maintenance


7.13 Express Card Socket Test Error -2
An error occurs when a express card device is installed.

J4 U512
P8
36 41 42 31 48 PCIEREQ_NCARD# PCIECLK_NCARDPCIEREQ_NCARD# PCIECLK_NCARD16 18 19 7 8

Clock Generator

ICS953009

U513 P6 North Bridge VIA VN896

P11 P12

U514

South Bridge

t t n e e r c m e u S c c Do a iT ial M t n e id f n o C
PCIECLK_NCARD+ SMB_CLK PCIECLK_NCARD+ SMB_CLK SMB_DATA SMB_DATA PCI_EXP_TX16Change to Change to NCARD_TX16PCI_EXP_TX16+ PCI_EXP_RX16NCARD_TX16+ PCI_EXP_RX16+

P15

24

Express Card Connector

25 21 22

+3V
5

U516 AHC1G08DBV 1 2

4 SB_CARD_PCIRST# 1

P15

CARD_RST# CPUSB# CPPE#

13 4 17

PCI_RESET#

U20

11 12

G577D5U

PCIE_WAKE_UP# USBP5-

PCIE_WAKE_UP# USBP5-

11 2 3

USBP5+

VIA VT8237A

USBP5+

127

Reference Material
Intel Merom Processor VIA VN896 North Bridge VIA VT8237A South Bridge 8515 Hardware Engineering Specification System Explode Views Intel.Inc VIA.Inc VIA.Inc Technology.Corp./MITAC Technology.Corp./MITAC

SERVICE MANUAL FOR


Sponsoring Editor : Ally Yuan Author : Guangna Zhang

8515

Publisher : MiTAC Technology Corp. Address : No.269, Road 2, Export Processing Zone, Kunshan, P.R.C Tel : 086-512-57367777 Second Edition : Oct.2007 E-mail : Ally.Yuan @ mic.com.tw Web : http: //www.mitac.com http: //www.mtc.mitacservice.com Fax : 086-512-57385099