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Bipolar Fundamentals

VBE Emitter Base V CB Collector SC


1E-1

IC0
1E-2 1E-3

IB 0

IC

Ec Ev

IB

Current (A A)

IC IB
Ec Ev x

1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 0.4

-WE

Base current = holes injected from base into emitter. Collector current = electrons j from emitter into base. injected
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AE = 9 m 2

0.6

0.8

1.2

1.4

Emitter-base voltage (V)


1

Current Gain =IC/IB

Ideal I-V Characteristics


Saturation region
C

Non-saturation region

VCB
B

IC
VCE

IB = 5 4 3

VBE
E

2 1 0 VCE

Saturation region: VCE < VBE -- both E-B diode and C-B diode are forward biased Non-saturation region: g VCE > VBE -- E-B diode forward biased, C-B diode reverse biased
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Quasi-Fermi Level
Non-equilibrium:

pn = ni2 exp q( p n ) / kT

]
Ec Ef Ev

A forward biased p-n junction:


Ec Ef Ev -q q n -q p qV app >0

Na

-x p

xn

Nd

Excess electrons: np(x=-xp)=(ni2/Na)exp(qVapp/kT) Excess holes: pn(x (x=x xn) )=(n (ni2/Nd)exp(qVapp/kT) So collector current is inversely proportional to base doping, And base current is inversely proportional to emitter doping doping.
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Excess Electrons in the p-Region


d kT dn dn n n0 n 1 J n = Jn = qnn kT R G = = Rn + Gn = 0 n n dx qn dx n dx n t q x d 2 n p n p n p0 kT n n = 0 , L D = where is the n n n 2 2 q dx Ln 1 minority carrier diffusion length length.
Noma alized excess s electron de ensity
0.8

Boundary conditions: n p = n p 0 exp qVapp / kT at x=0, 0 and

W/L = 0.2
0.6 0.4

n p = n p0

exp(-x/L)
0.2

at x x=W W (ohmic contact).

0.5
0 0 0.5

1.0
1 1.5

2.0
2 2.5 3

n p n p 0 = n p 0 exp( qVapp
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sinh i h[(W x ) / Ln ] . / kT ) 1 sinh(W / Ln )

x/L
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Bipolar Design Considerations


Reach-through E
n+

B Emitter Base Collector Subcollector


p

E
n+ p

p n n+

p n

n n+ p

Base: --Thin base means higher current gain and smaller stored charge, therefore higher performance. --Doping Doping must be high enough to keep base resistance low and avoid E-C p punchthrough. g Collector: --Higher collector doping reduces base widening. --Higher doping also means higher B-C capacitance. --Need Need highly highl doped s sub-C bC to minimize resistance.
5

C
(a) (b)

Emitter: --Doping as high as possible. --Deep emitter gives higher current gain, but difficult to control thin base width. idth
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Intrinsic-Base Resistance
W

Intrinsic base sheet resistance


B1 E B2 L

RSbi = q

WB

pp ( x ) p ( x )dx

One base contact only


B1
rbx

E
rbi C

B2

rbi =

1 W R Sbi 3 L
1 W R Sbi 12 L

Two-sided base contact


rb i =

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Emitter-Collector Punchthrough
punchthrough

E-C punchthrough when base width becomes so small that VBC starts to affect the potential barrier of E-B diode. (like drain-induced barrier lowering in MOSFET.) When operated near punchthrough, collector current is no longer controlled by VBE. Depletion-layer width of a onesided n+-p diode,
Normal

Wd =

2 si (

bi

V app )

Ec Ev

Punch through

qN a

Ec Ev
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To avoid punchthrough as the base width is reduced, the base doping NB should be increased as NB (WB)2.

Base Widening at Low/High Currents


E B NB C NC

(x )
WB0

NC
+ + + + + +

Low currents: Mobile electrons adds to space charge in base basecollector diode spacecharge region. Electric field in B-C B C junction is reduced.
x

x B0

Zero-biased Zero biased

_ _ _ _ _ _

x C0

NB
_ + Bound charges Mobile electrons

( x)
WB

(NC n)
+ + + + + +

xB

_ _ __ _

xC

Forward-biased
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(NB +n)

High currents: When electron concentration entering collector region is larger than NC, quasineutrality requires that p ~ n > NC. The excess hole distribution in collector becomes an extension of the p p-type t pe base base, ca causing sing base widening.
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Base Widening and Collector Design


Circuit Delay

Performance degrades rapidly with current when collector current density is large enough to cause significant base widening.
Conc. li ibl p negligible NC n << NC x B-C jcn
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fT

Collector Current Density

Conc. n >> NC p >> NC NC

x B-C jcn
9

Maximum JC without significant base widening is ~ 0.3qvsatNC.

Polysilicon Emitter Bipolar Transistor


xjE

C
n+ polysilicon p+ polysilicon
Concentrat tion (cm-3 )

Polysilicon

xjB

p+ polysilicon

1E+21 1E+20 1E+19

N-type yp

p+

p n

p+ n+

P type P-type

1E+18 1E+17 1E+16

N-type

n+ subcollector ppolysilicon-filled deep trench isolation

0.2

0.4

0.6

0.8

Depth (m)

IB = [qAEDpEnieE2/NEWE]exp(qVBE/kT) IC = [qAEDnBnieB2/NBWB]exp(qVBE/kT)
3/9/2010 Source: Tak Ning, IBM

2 nieB DnB N EWE 0 = 2 nieE D pE N BWB

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General Expression for Collector Current


dn nieB q ( p n ) / kT d n = q n = constant e J n ( x ) = qn p n pp dx dx
2

pp d q ( p n ) / kT = JC e 2 dx qD nB nieB
Since

q ( p n ) / kT W B 0

= e qV BE / kT , integration yields

JC = JC0exp(qVBE/kT) where

JC 0 =

WB

q pp (x) DnB ( x )n ( x )
2 ieB

dx

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Small-Signal Equivalent Circuit


VC (t)

C B C

iB(t) = IB+ ib(t)


VB (t)

iC(t) = IC+ ic(t)

VE = 0

C E

r0

gm vbe E

iE(t) = IE + ie(t)

(parasitic resistances neglected) Transconductance gm relates ic to vbe b : Input resistance r relates ib to vbe: Output resistance r0 relates ic to vce: gm = IC/VBE = qIC/kT r = VBE/IB = kT/qIB = 0/gm r0 = VCE/IC = VA/IC

Base-collector depletion capacitance: C = CdBC Capacitance of emitter-base diode:


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C = CdBE + CDE
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Early Voltage
I B1

IC

I B2 I B3 I B4 I B5

As VC increases, the base-collector depletion layer widens so the base width decreases and Ic i increases.

0 VA

VCE

IC V A IC VCE

2 Q pB qDnB (WB ) nieB q (WB ) WB N B ( x) VA d dx 2 0 C dBC C dBC DnB ( x ) nieB ( x )

where C dBC dQ pB / dV CB
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and

Q pB = q

WB

p p ( x ) dx
13

Source: Tak Ning, IBM

The VA Product
2 (WB ) WB qDnB (WB )nieB NB ( x) VA dx 2 0 CdBC DnB ( x )nieB ( x )

Since 0 = JC0/JB0 and J C 0 =

WB

q pp (x)
2 DnB ( x ) n B i B (x) ieB

dx

0V A

2 q 2 D nB (W B ) n ieB (W B ) = C dBC J B 0

VA product is a commonly used figure of merit in analog circuits. VA product depends on base doping profile only indirectly through the nieB term. Typical VA ~ 4000 V (VA ~ 40, ~ 100)
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Current Gain Cutoff Frequency, fT


ib B C E r gm vbe C C ic E

fT = transition frequency at which short-circuit load, small-signal current gain drops to unity. unity

ic = g m v be j C v be
1 ib = + j C + j C v be r i ( ) = c ib
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Neglecting parasitic resistances:

1 kT =F + (CdBE + CdBC ) 2 fT qIC

F = (tB + tE + tBE + tBC)


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Base Transit Time


Assume narrow base: Electron current in base is constant. Jn = qDn(dn/dx) = qDnn(0)/W Total excess charge in base QB = qn(o)W/2 Base transit time tB given by tB QB/Jn = W2/2Dn

W E-B junction
QB = q
WB

For WB = 100 nm, NB = 2E18 cm3, tB = (WB)2q/2DnB ~ 6 ps.


2 n ieB d np pp 2 p p dx n ieB

n p ( x ) dx
WB

J C = qD nB

tB =
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2 WB p p ( x ) nieB i B ( x) dx dx 2 x pp ( x) DnB ( x )nieB ( x )

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Collector Design Trade-off


100

Cut-off fr requency (G GHz)

Rbi = 15 - 26 K ohm/sq 80 VCB = 1 V AE = 0.5x2.9 m2


60 40

NC = 2E18 /cm3

1E18 /cm3
20 0 0.1 0.2 0.5 1 2 5 10 20 50

Collector current (mA)


Reference: E.F. Crabbe et al., 1993 IEDM

However, higher NC means High CdBC Low B-C breakdown voltage Q pB Small VA V
A

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C dBC

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SiGe Bipolar p
Eg(Si) 1.12 eV Eg(Ge) 0.66 eV Incorporation of Ge into Si reduces bandgap of the alloy.
Ec cubic Si Eg = 1.17 eV Ev 0.02 02 eV Ec = 0 strained Ge0.2 Si 0.8 Eg = 1.0 eV 0.15 15 eV Ev = 0
Ec cubic Si Eg = 1.17 eV Ev 0.02 02 eV Ec = 0 strained Ge0.5 Si 0.5 Eg = 0.78 eV Ev = 0.37 eV

After R R. People People, IEEE J J. QE QE, QE QE-22, 22 p p. 1696 (1986)

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npn Transistor with SiGe Base


Ec Ef Ev n+ Si p+ SiGe Ec Ec Ev n+ Si p+ SiGe Ev
0 Ec Ef Ev p-type SiGe x

Ec Ev
% Ge

Base grading:

Barrier for hole injection into n+ Si has not changed, i.e., no effect on base current. Barrier for electron injection j into p p+ SiGe is lowered by the Eg in SiGe, which increases collector current.
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Graded SiGe Base


Emitter n+ Si Base p Si or SiGe Collector Without Ge With Ge G Ec n Si % Ge Boron 0
2 ieB

JC = JC0exp(qVBE/kT)

JC 0 =

Ge x

Ev

WB

q pp (x) DnB (x) B ( x )n


2 i B ieB

dx

2 p0 (Eg )n0 (Eg ) nie = ni2 exp(Eg / kT )

E g , SiGe x n (SiGe) = n (Si)exp kT W B


2 ieB

E g , SiGe / kT J C 0 (SiGe) (SiGe) = = J C 0 (Si) (Si) 1 exp ( E g , SiGe / kT )


3/9/2010 Source: Tak Ning, IBM 20

Early Voltage: SiGe Base


2 qDnB (WB )nieB (WB ) WB NB ( x) VA dx 2 0 CdBC DnB ( x )nieB ( x )

V A (SiGe) kT exp E g ,SiGe / kT 1 = V A (Si) E g ,SiGe


Figure of merit: VA product:

[ (

) ]

(SiGe)V A (SiGe) = exp( E g ,SiGe / kT ) (Si)V A (Si)


For uniform Ge distribution:

0(SiGe) = 0(Si)exp(Eg/kT)

% Ge 0
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But no change in Early voltage. VA(SiGe)/ VA(Si) = exp(Eg/kT)

Same as the linearly graded base base.


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Base Transit Time


tB QB / J C

where

QB = q

WB

n p ( x ) dx

2 2 p p ( x ) nieB q ( p n ) / kT J C nieB ( x) WB n p ( x) = e dx = 2 x pp q p p ( x) D nB ( x ) nieB ( x )

tB =

WB

2 p p ( x ) ( x ) WB nieB dx dx 2 x pp ( x) DnB ( x )nieB ( x )

2kT tB(SiGe) kT 1 1 exp Eg,SiGe / kT = tB(Si) Eg,SiGe Eg,SiGe

))

For uniform Ge distribution, no change in base transit time.


3/9/2010 Source: Tak Ning, IBM 22

Comparison of Uniform and Linearly G d dG Graded Ge P Profiles fil ( (same t total t l Ge) G )
% Ge

Assume amount of bandgap narrowing is proportional to Ge concentration. For the same amount of total integrated g Ge in the base layer, Eg(linear grading) = 2Eg(uniform).
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Comparison of Uniform and Linearly G d dG Graded Ge P Profiles fil ( (same t total t l Ge) G )
1E+4 Gain (linear) 1E+3 VA (linear) tB (linear)

Gain (uniform) VA (uniform) tB (uniform)

(SiGe) / (Si)

1E+2 1E+1 1E+0 1E-1

10

Eg(linear grading)/kT
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Source: Tak Ning, IBM

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Any Merit with Uniformly Narrow B Base B Bandgap? d ?


Current gain improvement can be very large large. No change in other device parameters. The large current gain can be traded off for much smaller base resistance. -- Early y voltage g is increased. -- However, increase in intrinsic base doping concentration will increase CdBE. The large current gain cannot be used to reduce emitter doping concentration (like in compound-semiconductor HBTs), without regineering the polysilicon emitter process.
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Heterojunction Bipolar Transistor?


Traditional heterojunction emitter: Emitter bandgap larger than the Ec b base b bandgap d at t th the E E-B Bj junction. ti Base Emitter Base current suppressed by the Ev large hole injection barrier. Emitter doping concentration can be very low. CdBE much smaller than nonCollector heterojunction emitter transistor. transistor Emitter Base Without With t Ge G With Ge Collector current not affected. p Si or
n+ Si

SiGe-base bipolar as an HBT: n Si Emitter parameters not affected by base bandgap engineering. Base current not affected. No change in CdBE. Graded SiGe base bipolar not an HBT in traditional sense sense.
3/9/2010 Source: Tak Ning, IBM

SiGe

Ec Ev

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SiGe ECL Delays


Transit time reduction

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Maximum fT Limited by B-C Breakdown


8 Si-base SiGe-base 6

BVCEO (V) B )

4 2 0

20

40

60

80

100

120

fT ( (GHz) )
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SiGe Base Bipolar Transistor SiGe-Base


220 200 180 Cutoff f frequency (GH Hz) 160 140 120 100 80 60 40 20 0 1E-4 1E-3 Ic (A)
* Electron Device Letters Jan 2001 IBM 0.18 m generation

VCB = 1V
InP low current optimized* optimized

IBM SiGe next generation

1E-2

After K. Washio et al., 1997 IEDM


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Bipolar and MOSFET Comparison


Bipolar
IC = IC0exp(qVBE/kT)

MOSFET
Ids = (1/2)Cox(W/L)(Vg-Vt)2 or Ids = CoxWvsat(Vg-Vt)

gm = IC/(kT/q) CBE = t qIC/kT fT = 1/2 t

gm = 2Ids/(Vg-Vt) or Ids/(Vg-Vt) Cg = CoxWL + 2CovW fT = vsat/2 L (intrinsic)

Transit time t ~ 0.1-1 0 1 1 ps


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The Magic of CMOS Circuit


Vdd
Negligible standby power dissipation.
on

pMOS
High High

Focus all power budget to switching events. Key to VLSI integration with low activity factors. The only known circuit with such properties.

In
Low

Out
Low

nMOS
on

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VLSI Density and Feature Size vs. Time


1E+10 # of trans sistors pe er chip 1E+9 1E+8
16Mb 1GHz 200MHz 1Mb CMOS DRAM 1Gb

2 1 0.5

1E+7 1E+6 1E+5 1E+4


4Kb 2MHz 64Kb 5MHz MPU 25MHz

Lithography

0.2 0.1 2000 0.05 2010

1E+3 1970
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1980

1990 Year

Minimum featur re size (m)


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