A non-volatile Flip-Flop in Magnetic FPGA chip

W.Zhao
1
, E. Belhaire
1
, V. Javerliac
2
, C. Chappert
1
, B. Dieny
2
1. Institut dElectronique Fondamentale, Universit Paris Sud, CNRS, France
2. SPINTEC, CEA (Commissariat lEnergie Atomique) Grenoble/CNRS, France
E-Mail: zhao@ief.u-psud.fr


Abstract In this paper, we propose a non-volatile flip-flop,
which presents simultaneously low power dissipation and high
speed. This flip-flop is based on MRAM (Magnetic RAM)
technology on standard CMOS. In this non-volatile flip-flop
design, we use Magnetic Tunnel Junctions (MTJ) as storage
element. Contrary to the complex sense amplifier circuit in
standard MRAM circuits, a simple one based on SRAM cell is
used to couple with two MTJs per bit in Magnetic logic circuit.
The flip-flop works exactly as a classical flip-flop but the
information is stored simultaneously in the two MTJs, which
makes this flip-flop non-volatile. As the writing frequency has
a strong impact on the power consumption, the MTJ writing
frequency is designed to be defined by the users depending on
different usage. During the startup or reset phase, the flip-flop
master stage is used as the MTJ sense amplifier and the flip-
flop is initialized to the previously stored state in about 200 ps.
This figure has been demonstrated by electrical simulation on
a 90 nm CMOS technology and with a complete and precise
MTJ model.

Keywords SRAM, MRAM, non-volatile, high speed,
low power, MTJ, SOC, Magnetic, flip-flop
I.INTRODUCTION

n the last 10 years, FPGA[1] circuits has developed
rapidly, because of their flexibility, their ease of use and
the low cost to design a function with them. However, the
internal memories used in FPGA circuits could limit their
future development. Most FPGA circuits use SRAM based
flip-flop [2] as internal memory; but as the SRAM is
volatile both their configuration and the information stored
in their internal registers are lost when the power is turned
down. The configuration is then also stored in an external
PROM and downloaded in the FPGA at startup.
Internal Flash technology is now sometime used to
replace the external memory [3]. However, its slow
reprogramming and its limited number of writing cycles (up
to 10
6
) prevent its use to replace the SRAM based internal
registers working at very high frequency [2].
By working at high writing and reading speed, MRAM
(Magnetic RAM) technology [4] is one of the best solutions
to bring a complete non-volatility to the FPGA technology
while keeping the power dissipation low. A Magnetic
Junction Tunnel (MTJ), as MRAM storage element, can be
re-programmed more than 10
12
times and has a large
retention time up to 10 years. This technology is now
mature and a lot of progress in its development has been
done lately, especially by IBM [5], Freescale [6] and
Samsung [7].
MRAM technology has been proposed to implement
the non-volatile configuration in FPGA [8]; however this
non-volatile configuration FPGA circuit isnt completely
non-volatile, because all the data proceeded are saved in the
flip-flop and they will still be lost when the circuit turned
off. In this paper, a magnetic flip-flop is proposed to make
the FPGA circuit completely non-volatile. The circuit
previous state restoration at startup takes about 200 pico
seconds.
Another advantage [4] of MRAM technology is that the
storage element MTJ does not take much die area, because
it is processed over the chip surface (Fig. 1.1) and the
dimension of every MTJ is also very small (e.g.
200nm100nm). Thereby the actual layout of
semiconductor circuit is barely affected.



Figure 1.1 the position of MTJs

In this paper, we introduce the magnetic flip-flop in the
second section; a magnetic flip-flop improved in terms of
power consumption, called a Magnetic Standard mixed
Flip-Flop, is presented in the third section and its
simulation results are shown in the fourth section. For our
electrical simulations, two 90nm and 130nm technologies
have been used for the CMOS part; and a complete
simulation model has been developed by CEA
(Commissariat lEnergie Atomique) for the magnetic part
(for a more complete description refers to [9]). This model
is based on FIMS (Field induced magnetic switching)
writing approach [4-6].
II.MAGNETIC FLIP-FLOP

In a FPGA circuit, flip-flops are used as registers to
temporarily store the results proceeded and synchronize
I
0-780J-9727-4/06/S20.00 @2006 lEEE
them with the global clock. It is one of the most important
components in FPGA circuit as it determines the data
processing speed and defines a large part of the total power
consumption. SRAM [2] based master-slave flip-flops are
widely used applied in the current FPGA circuits. The
master and slave two parts are both clock-controlled latches
(see Fig. 2.1). The master part is used to write the
information in the flip-flop and the slave part is used to
output the information, the global clock and its anti-phase
clock control the process.


Figure 2.1 SRAM based Master-Slave Flip-Flop
structure
In this paper, we propose a magnetic SRAM based D
flip-flop in which a sense amplifier and a magnetic writing
circuit replace the master part (see Fig. 2.3 to 2.4).


Figure 2.2 Magnetic Flip-Flop structures

Figure 2.3 schema of SRAM based sense amplifier

In this magnetic flip-flop design a SRAM based sense
amplifier [10] and a two-MTJ complementary structure are
used per bit (see Fig. 2.3). By programming the two MTJ on
the left and right in a complementary fashion, this structure
simplifies the reading circuit. One MTJ has then a higher
resistance value than the other one and the magnetic bit of
information can be read by this difference of resistance. It is
sense by briefly turning on the switch MN2 to put the
SRAM cell in a metastable state. When MN2 is turned off,
the SRAM leaves its metastable state to restore a digital
level whose value depends on the bit stored in the couple of
MTJ.
As it is currently used by most of MRAM
demonstrators, Field Induced Magnetic Switching (FIMS)
MTJ writing approach is applied here [1-3]. This writing
approach needs a high current to create a magnetic field
able to modify the information stored in the MTJ. The
writing current is generated by a two-direction current
generator (Fig. 2.4).


Figure 2.5 the simulation of magnetic Flip-Flop


Figure 2.4 Magnetic writing circuits

This magnetic flip-flop can be used to store
permanently all the intermediate results so it makes the
FPGA circuit more secure in case of shutdown (hazardous
or not) as all the processing results can be latter restored.
Moreover the magnetic flip-flop allows a real instant
restart of the FPGA of about 200ps in our simulation (see
Fig. 2.5).
The use of Magnetic flip-flop brings non-volatility to
the FPGA circuit and allows also the high speed data
processing. However, the main drawback of this
component, with the FIMS technique, is that it requires a
quite high current to write the information in the MTJs and,
as the flip-flop works with a very high frequency, this leads
to high power dissipation in the writing circuit. In our
simulation, when the clock frequency is as low as 10MHz,
the power dissipation in the writing circuit is about 351uw,
which is far too much for normal operating conditions.
Therefore, we developed an energy improved structure,
called the mixed Magnetic-Standard non-volatile flip-flop.
It is presented in the next section.
III.MAGNETIC STANDARD NON-VOLATILE FLIP-
FLOP

As already mentioned, a SRAM based sensing structure is
used to read the information of the MTJ. By using this
structure for two different functions, a magnetic standard
mixed non-volatile Flip-Flip has been developed (Fig. 3.1a).
When the transistor MN2 is switched off, it works as a
conventional flip-flop and the sense amplifier becomes a
two inverter stage. This stage is controlled by the clock
through the transistors MN5 and MN4. At the same time,
the writing circuit writes the MTJs but in a low, user
defined frequency through the signal NW. During a start-up
or reset phase, the NR signal is applied and the last
proceeded data, stored in the MTJ couple is loaded in the
master stage. This reading phase lasts about two hundred
picoseconds as demonstrated by electrical simulation (Fig.
2.5). By this way, the flip-flop keeps the non-volatility of
1/X times (X is the ratio of processing frequency and the
low, user defined frequency) and the power dissipation
could be well reduced compared to the cell presented in
previous section.


(a)


(b)
Figure 3.1 (a) Magnetic Standard mixed Flip-Flop
schema (b) Magnetic Standard mixed Flip-Flop symbol
IV.MSFLIP-FLOP SIMULATION

In the magnetic-standard flip-flop simulation, the low
frequency control signal NW is 10 KHz, the clock
frequency is 500MHz and the input frequency is 250MHz.
The propagation delay of Magnetic Standard flip-flop is
the same as of standard SRAM based flip-flop, lower than
200ps (see Fig. 4.1). Its power dissipation is a little higher
(3.51uw in the MTJ writing circuit) than SRAM based flip-
flop; the total access time of the flip-flop is about 650 ps.




(a)


(b)
Figure 4.1 the simulation results of magnetic standard
non-volatile Flip-Flop
(a) The last Data saved in MTJ is 1
(b) The last Data saved in MTJ is 0

The product of power and delay (PDP) [2] is routinely
used to determine the performance of flip-flop; Magnetic
Standard mixed flip-flop doesnt only keep the non-
volatility, but also has a good performance in the energy
and propagation time. The comparison among the three
types of flip-flop is presented in Table 4.1. We could
conclude that Magnetic Standard mixed flip-flop is the best
compromise to integrate non-volatility while keeping low
power dissipation in the flip-flop.

Table 4.1 Comparison among three types of Flip-Flop
Flip-Flop Non-volatility Tp* P*
SRAM based flip-flop No 200ps low
Magnetic flip-flop Yes 540ps high
Magnetic Standard
Mixed flip-flop
Yes (1/X times) 200ps low
V.CONCLUSION
We proposed this new architecture of Magnetic Standard
flip-flop which features simultaneously non-volatility, high
speed and low power dissipation. This flip-flop can also be
used to replace all the registers in SOC (System-on-chip)
then makes these chips non-volatile and secure. Therefore it
could be advantageously used in the field of aviation and
space where the security of information is one of the most
important considerations. By using the CEA complete
simulation model for the MTJ, this magnetic component has
been simulated to evaluate the magnetic circuit
performances. However, in addition to the high power
dissipations, the classical writing approach of MRAM
called FIMS, also imposes some big transistors in the
writing circuit and alternative writing approaches, like TAS
[11], [12] (Thermal assisted switching) and Spin torque
transfer [13], [14] are under investigation in our laboratory.

ACKNOWLEDGMENT
The work and results reported were obtained with research
funding from the European Community under the sixth
Framework, Contract Number 510993: MAGLOG. The
views expressed are solely those of the authors, and the
other Contractors and/or the European Community cannot
be held liable for any use that may be made of the
information contained herein.
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