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SL.NO   NAME OF THE EXPERIMENT PAGE NO 1 Simulation and realization of all logic

SL.NO

 

NAME OF THE EXPERIMENT

PAGE NO

1

Simulation and realization of all logic gates.

2-6

2

Write a HDL code to describe the functions of half adder, half subtractor and Full subtractor.

7-9

3

Write HDL codes for the following combinational circuits.

10-22

a)

2 to 4 decoder 8 to 3 encoder 8 to 1 multiplexer 4 bit binary to gray converter Multiplexer De-multiplexer

b)

c)

d)

e)

f)

g)

1 bit comparator

h)

4 bit comparator

4

Write HDL code to describe the functions of a full Adder Using three modeling styles.

23-27

5

Write a model for 32 bit ALU using the schematic diagram shown below.

28-29

6

Develop the HDL code for the following flip flop: T, D, SR, JK.

30-35

7

Design 4 bit Binary, BCD Counter (Synchronous reset and Asynchronous reset and any sequence counters.

36-40

8

Simulation and realization of Ring counter.

41-57

Experiment No. 1

AIM: Simulation and realization of all logic gates.

COMPONENTS REQUIRED: FPGA board, FRC’s, jumper and power supply.

Truth table with symbols

of all logic gates. COMPONENTS REQUIRED: FPGA board, FRC’s, jumper and power supply. Truth table with

Black Box

LOGIC GATES
LOGIC GATES
LOGIC GATES

LOGIC

GATES

GATES
LOGIC GATES
LOGIC GATES
LOGIC GATES
LOGIC GATES
LOGIC GATES
LOGIC GATES
LOGIC GATES
LOGIC GATES
LOGIC GATES
LOGIC GATES
LOGIC GATES
LOGIC GATES

cBlack Box LOGIC GATES d a b e f g h i Truth table Basic gates:

d Black Box LOGIC GATES c a b e f g h i Truth table Basic gates:

a

a b

b

Black Box LOGIC GATES c d a b e f g h i Truth table Basic

eBlack Box LOGIC GATES c d a b f g h i Truth table Basic gates:

fBlack Box LOGIC GATES c d a b e g h i Truth table Basic gates:

gBlack Box LOGIC GATES c d a b e f h i Truth table Basic gates:

hBlack Box LOGIC GATES c d a b e f g i Truth table Basic gates:

iBlack Box LOGIC GATES c d a b e f g h Truth table Basic gates:

Truth table Basic gates:

a

b

c

d

E

f

g

h

i

0

0

0

0

1

1

1

0

1

0

1

0

1

1

1

0

1

0

1

0

0

1

0

1

0

1

0

1

1

1

1

0

0

0

0

1

VHDL CODE

VERILOG CODE

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOG IC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gates is Port ( a,b : in std_logic; c,d,e,f,g,h,i : out std_logic); end gates;

architecture dataflw of gates is

begin

c<= a and b; d<= a or b; e<= not a; f<= a nand b; g<= a nor b; h<= a xor b; i<= a xnor b; end dataflw;

module allgate ( a, b, y ); input a,b; output [1:6] y; assign y[1]= a & b; assign y[2]= a | b, assign y[3]= ~a , assign y[4]= ~(a & b), assign y[5]= ~(a | b), assign y[6]= a ^ b; endmodule

Procedure to view output on Model sim 1) After the program is synthesized create a Test bench, load the input. 2) Highlight the tbw file and click onto Modelsim Simulate behavioral model.

3) Now click the waveform and zoom it to view the result.

Modelsim Output

the waveform and zoom it to view the result. Modelsim Output Output (c to i) PROCEDURE

Output (c to i)

PROCEDURE TO DOWNLOAD ONTO FPGA

1)

Create a UCF (User Constraints File).

2)

Click on UCF file and choose assign package pins option as shown in the figure below.

(User Constraints File). 2) Click on UCF file and choose assign package pins option as shown

3)Assign the package pins as shown in fig below

3)Assign the package pins as shown in fig below 3) save the file. 4) Click on

3)

save the file.

4)

Click on the module and choose configure device option.

5)

The following icon will be displayed.

5
5

6)

Right click on the icon and select program option.

7)

Program succeeded message will be displayed.

8)

Make connections to main board and daughter boards( before configuring ) , give necessary inputs from DIP SWITCH and observe the output on LEDs.

NET "a" LOC = "p74" ; NET "b" LOC = "p75" ; NET "c" LOC = "p84" ; NET "d" LOC = "p114" ; NET "e" LOC = "p113" ; NET "f" LOC = "p115" ; NET "g" LOC = "p117" ; NET "h" LOC = "p118" ; NET "i" LOC = "p121" ;

Repeat the above Procedure to all the Programs.

RESULT: The logic gates design has been realized and simulated using HDL codes.

Experiment No. 2

AIM: Write a HDL code to describe the functions of half adder, half subtractor and Full subtractor.

COMPONENTS REQUIRED: FPGA board, FRC’s, jumper and power supply.

(a) HALF ADDER

TRUTH TABLE

INPUTS

OUTPUTS

A

B

S

C

0

0

0

0

0

1

1

0

1

0

1

0

1

1

0

1

BOOLEAN EXPRESSIONS:

BASIC GATES

1 0 1 1 0 1 BOOLEAN EXPRESSIONS: BASIC GATES S=A ⊕ B C=A B VHDL

S=A B C=A B

VHDL CODE

VERILOG CODE

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOG IC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HA is Port ( a, b : in std_logic; s, c : out std_logic); end HA;

module ha ( a, b, s, c) input a, b; output s, c; assign s= a ^ b; assign c= a & b; endmodule

architecture dataflow of HA is

begin s<= a xor b; c<= a and b; end dataflow;

(b)HALF SUBTRACTOR

TRUTH TABLE

 

INPUTS

OUTPUTS

A

B

D

Br

0

0

0

0

0

1

1

1

1

0

1

0

1

1

0

0

BASIC GATES

 
0 1 0 1 1 0 0 BASIC GATES   BOOLEAN EXPRESSIONS: D = A ⊕

BOOLEAN EXPRESSIONS:

D = A B

Br =

_

A B

VHDL CODE

VERILOG CODE

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOG IC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hs is Port ( a, b : in std_logic; d, br : out std_logic);

module hs ( a, b, d, br) input a, b; output d, br; assign d= a ^ b; assign br= ~a & b; endmodule

end hs;

architecture dataflow of hs is

begin d<= a xor b; br<= (not a) and b;

end dataflow;

(C)FULL SUBTRACTOR

TRUTH TABLE

 

INPUTS

OUTPUTS

A

B

Cin

D

Br

0

0

0

0

0

0

0

1

1

1

0

1

0

1

1

0

1

1

0

1

1

0

0

1

0

1

0

1

0

0

1

1

0

0

0

1

1

1

1

1

BASIC GATES

 

BOOLEAN EXPRESSIONS:

D= A B C

_

Br= A B + B Cin +

_

A Cin

D= A ⊕ B ⊕ C _ Br= A B + B Cin + _ A

VHDL CODE

VERILOG CODE

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOG IC_ARITH.ALL;

module fs ( a, b, c, d, br) input a, b, c; output d, br; assign d= a ^ b ^ c; assign br=(( ~a)& (b ^ c)) | (b & c); endmodule

use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fs is Port ( a, b, c : in std_logic;

d, br

: out std_logic);

 

end fs;

architecture dataflw of fs is begin d<= a xor b xor c; br<= ((not a) and (b xor c)) or (b and c); end datafolw;

RESULT:The half adder, half subtractor and full subtractor designs have been realized and simulated using HDL codes.

Experiment No. 3

AIM: Write HDL codes for the following combinational circuits.

COMPONENTS REQUIRED: FPGA board, FRC’s, jumper and power supply.

a) 2 TO 4 DECODER

BLACK BOX

2 to 4 Decoder

2 to 4

Decoder

2 to 4 Decoder
2 to 4 Decoder
2 to 4 Decoder
2 to 4 Decoder
2 to 4 Decoder
2 to 4 Decoder
2 to 4 Decoder

Y0power supply. a) 2 TO 4 DECODER BLACK BOX 2 to 4 Decoder Sel 0 Sel

Sel 0

Sel 1

2 TO 4 DECODER BLACK BOX 2 to 4 Decoder Y0 Sel 0 Sel 1 E

E

Y12 TO 4 DECODER BLACK BOX 2 to 4 Decoder Y0 Sel 0 Sel 1 E

4 DECODER BLACK BOX 2 to 4 Decoder Y0 Sel 0 Sel 1 E Y1 Y2

Y24 DECODER BLACK BOX 2 to 4 Decoder Y0 Sel 0 Sel 1 E Y1 Y4

DECODER BLACK BOX 2 to 4 Decoder Y0 Sel 0 Sel 1 E Y1 Y2 Y4

Y4DECODER BLACK BOX 2 to 4 Decoder Y0 Sel 0 Sel 1 E Y1 Y2 Truth

Truth Table of 2 to 4 decoder

E

Sel1

Sel0

Y3

Y2

Y1

Y0

1

0

0

0

0

0

1

1

0

1

0

0

1

0

1

1

0

0

1

0

0

1

1

1

1

0

0

0

0

X

X

0

0

0

0

DATA FLOW

VHDL CODE

VERILOG CODE

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

module dec2_4 (a,b,en,y0,y1,y2,y3) input a, b, en; output y0,y1,y2,y3; assign y0= (~a) & (~b) & en; assign y1= (~a) & b & en; assign y2= a & (~ b) & en; assign y3= a & b & en; end module

entity dec2_4 is port (a, b, en :in std_logic ; y0, y1, y2, y3:out std_logic); end dec2_4;

architecture data flow of dec2_4 is begin y0<= (not a) and (not b) and en; y1<= (not a) and b and en; y2<= a and (not b) and en; y3<= a and b and en; end dataflow;

 

NET "e" LOC = "p74"; NET "sel<0>" LOC = "p75"; NET "sel<1>" LOC = "p76"; NET "y<0>" LOC = "p112"; NET "y<1>" LOC = "p114"; NET "y<2>" LOC = "p113"; NET "y<3>" LOC = "p115";

Simulation is done using Modelsim Waveform window : Displays output waveform for verification.

window : Displays output waveform for verification . Output b) 8 TO 3 ENCODER WITH PRIORITY

Output

b) 8 TO 3 ENCODER WITH PRIORITY

  i7Z3
 
  i7Z3

i7Z3

 
  i7Z3   8:3   Z1     Parity Z0 Encoder   enx i0   V
8:3   Z1
8:3   Z1

8:3

 
8:3   Z1

Z1

 
 

Parity

  Parity Z0

Z0

Encoder

Encoder
 

enx

i0

i0
 
i0   V

V

 

en

   

Truth table

En

I7

I6

I5

I4

I3

I2

I1

I0

Z2

Z1

Z0

enx

V

1

X

X

X

X

X

X

X

X

1

1

1

1

1

0

1

1

1

1

1

1

1

1

1

1

1

1

0

0

1

1

1

1

1

1

1

0

1

1

1

0

1

0

1

1

1

1

1

1

0

X

1

1

0

0

1

0

1

1

1

1

1

0

X

X

1

0

1

0

1

0

1

1

1

1

0

X

X

X

1

0

0

0

1

0

1

1

1

0

x

X

X

X

0

1

1

0

1

0

1

1

0

X

X

X

X

X

0

1

0

0

1

0

1

0

X

X

X

X

X

X

0

0

1

0

1

0

0

X

X

X

X

X

X

X

0

0

0

0

1

VHDL CODE

VERILOG CODE

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder8_3 is Port ( i : in std_logic_vector(7 downto 0); en : in std_logic; enx,V : out std_logic; z : out std_logic_vector(2 downto 0)); end enco2;

module enc8_3 (I, en, y, v); input [7:0]I; input en; output v; output [2:0]y; sig y; sig v; always @ (en, I) begin if(en= =0)

v=0;

 

else

architecture behavioral of encoder8_3 is begin

v=1;

end if ( I[7]= =1 & en= =1)

 

y=3’b111;

else if ( I[6]==1 & en==1) else if ( I[5]==1 & en==1) else if ( I[4]==1 & en==1) else if ( I[3]==1 & en==1) else if ( I[2]==1 & en==1) else if ( I[1]==1 & en==1) else if ( I[0]==1 & en==1) else y=3’b000; end end module

y=3’b110;

end behavioral ;

y=3’b101;

y=3’b100;

y=3’b011;

y=3’b010;

y=3’b001;

y=3’b000;

#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "en" LOC = "p84"; NET "i<0>" LOC = "p85"; NET "i<1>" LOC = "p86"; NET "i<2>" LOC = "p87"; NET "i<3>" LOC = "p93"; NET "i<4>" LOC = "p94"; NET "i<5>" LOC = "p95"; NET "i<6>" LOC = "p100"; NET "i<7>" LOC = "p74"; NET "enx" LOC = "p112"; NET "V" LOC = "p114"; NET "z<0>" LOC = "p113"; NET "z<1>" LOC = "p115"; NET "z<2>" LOC = "p117";

Output
Output

c) 8 TO 1 MULTIPLEXER

a

b

c

d

e

f

g

h

sel(2 to 0)

Truth table

8:1Mux

8:1Mux
8:1Mux
8:1Mux
1 MULTIPLEXER a b c d e f g h sel(2 to 0) Truth table 8:1Mux
1 MULTIPLEXER a b c d e f g h sel(2 to 0) Truth table 8:1Mux
1 MULTIPLEXER a b c d e f g h sel(2 to 0) Truth table 8:1Mux
1 MULTIPLEXER a b c d e f g h sel(2 to 0) Truth table 8:1Mux
1 MULTIPLEXER a b c d e f g h sel(2 to 0) Truth table 8:1Mux
1 MULTIPLEXER a b c d e f g h sel(2 to 0) Truth table 8:1Mux
1 MULTIPLEXER a b c d e f g h sel(2 to 0) Truth table 8:1Mux
1 MULTIPLEXER a b c d e f g h sel(2 to 0) Truth table 8:1Mux

Z

Sel2

Sel1

Sel0

Z

0

0

0

A

0

0

1

B

0

1

0

C

0

1

1

D

1

0

0

E

1

0

1

F

1

1

0

G

1

1

1

H

VHDL CODE

VERILOG CODE

entity mux8_1 is port(I: in std_logic_vector (7 downto 0); S: in std_logic_vector (2 downto 0); en: in std_logic; y: out std_logic); end mux8_1; architecture behavioral of mux8_1 is begin process (I,s,en) is begin if en=’1’ then if S=”000” then y<=I(0); elsif S=”001” then y<=I(1); elsif S=”001” then y<=I(2); elsif S=”001” then y<=I(3); elsif S=”001” then y<=I(4); elsif S=”001” then y<=I(5); elsif S=”001” then y<=I(6); else y<=I(7); end if; else y<=’0’; end if; end process; end mux8_1;

module mux8_1 input [7:0]I; output [2:0]S; output y; input en; reg y; always @(en,S,I,y); begin if (en= =1) begin if (s= =000 y=I[0]; else if (s==001) y=I[1]; else if (s==001) y=I[2]; else if (s==001) y=I[3]; else if (s==001) y=I[4]; else if (s==001) y=I[5]; else if (s==001) y=I[6]; else if (s==001) y=I[7]; end else y=0; end end endmodule

else if (s==001) y=I[5]; else if (s==001) y=I[6]; else if (s==001) y=I[7]; end else y=0; end
else if (s==001) y=I[5]; else if (s==001) y=I[6]; else if (s==001) y=I[7]; end else y=0; end
else if (s==001) y=I[5]; else if (s==001) y=I[6]; else if (s==001) y=I[7]; end else y=0; end

Output

d)

4-BIT BINARY TO GRAY COUNTER CONVERTER

Black Box

clk

clk   4 bit  
 

4 bit

 

en

en Binary to   q(3 downto 0)  

Binary to

 
en Binary to   q(3 downto 0)  

q(3 downto 0)

 

rst

 

gray

 
 
 

Truth table

 

Rst

Clk

En

B3

B2

B1

B0

G3

G2

G1

G0

1

X

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

1

0

0

0

1

0

1

1

0

0

1

0

0

0

1

1

0

1

1

0

0

1

1

0

0

1

0

0

1

1

0

 

1

0

0

0

1

1

0

0

1

1

0

 

1

0

1

0

1

1

1

0

1

1

0

 

1

1

0

0

1

0

1

0

1

1

0

 

1

1

1

0

1

0

0

0

1

1

1

0

0

0

1

1

0

0

0

1

1

1

0

0

1

1

1

0

1

0

1

1

1

0

1

0

1

1

1

1

0

1

1

1

0

1

1

1

1

1

0

0

1

1

1

 

1

0

0

1

0

1

0

0

1

1

1

 

1

0

1

1

0

1

1

0

1

1

1

 

1

1

0

1

0

0

1

0

1

1

1

 

1

1

1

1

0

0

0

VHDL CODE

VERILOG CODE

entity bintogray is Port ( rst,clk : in std_logic; g : inout std_logic_vector(3 downto 0)); end bintogray;

module b2g(b,g); input [3:0] b; output [3:0] g; xor (g[0],b[0],b[1]),

(g[1],b[1],b[2]),

architecture Behavioral of bintogray is signal b: std_logic_vector( 3 downto 0); begin process(clk,rst) begin if rst='1' then b<="0000"; elsif rising_edge(clk) then b<= b+’1’; end if; end process; g(3)<= b(3); g(2)<= b(3) xor b(2); g(1)<= b(2) xor b(1); g(0)<= b(1) xor b(0); end Behavioral;

(g[2],b[2],b[3]);

assign g[3]=b[3]; endmodule

(g[2],b[2],b[3]); assign g[3]=b[3]; endmodule Binary to gray Output PACE: Start of Constraints generated

Binary to gray Output

PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments NET "b<0>" LOC = "p84"; NET "b<1>" LOC = "p85"; NET "b<2>" LOC = "p86"; NET "b<3>" LOC = "p87"; NET "g<0>" LOC = "p112"; NET "g<1>" LOC = "p114"; NET "g<2>" LOC = "p113"; NET "g<3>" LOC = "p115";

e)

MULTIPLEXER(4 TO 1)

Black Box

a

b

c

d

sel (1 to 0)

   
   
4:1

4:1

4:1
Mux  

Mux

 
    4:1 Mux  

Truth Table

Z

Sel1

Sel0

Z

0

0

a

0

1

b

1

0

c

1

1

d

VHDL CODE

VERILOG CODE

entity mux1 is Port ( en,I : in std_logic; sel:in std_logic_vector(1downto 0); y : out std_logic);

module mux4_1(I0,I1,I2,I3,s2,s1,y,en) input I0,I1,I2,I3,s2,s1,en; output y;

assigny<=((~s2)&(~s1)&en&I0)|

 

((~s2)&(s1)&en&I1)|(s2&(~s1)&en&I2)|(s2&s1&

end mux1; architecture dataflow of mux1 is begin z<= I0 when sel= "00" else I1 when sel= "01" else I2 when sel= "10" else

I3;

en&I3);

endmodule

end dataflow;

else I2 when sel= "10" else I3; en&I3); endmodule end dataflow; Multiplexer Output 17

Multiplexer Output

f)

DE-MULTIPLEXER ( 1 TO 4)

Black Box

a en 1:4 Demux sel(1 downto 1)
a
en
1:4
Demux
sel(1 downto 1)

Truth table

Y(3 downto 0)

a

En

Sel1

Sel0

Y3

Y2

Y1

Y0

1

0

0

0

0

0

0

1

1

0

0

1

0

0

1

0

1

0

1

0

0

1

0

0

1

0

1

1

1

0

0

0

0

1

X

X

0

0

0

0

VHDL CODE

VERILOG CODE

entity demux is Port ( I,en : in std_logic; sel: in std_logic_vector(1 downto 0);

y:outstd_logic_vector(3downto0));

end demux; architecture dataflow of demux is signal x: std_logic_vector( 1 downto 0); begin x<= en & a; y <="0001" when sel="00" and x="01" else "0010" when sel="01" and x="01" else "0100" when sel="10" and x="01" else "1000" when sel="11" and x="01" else

"0000";

end dataflow;

module demux (s2,s1,I,en,y0,y1,y2,y3) input s2,s1,I,en; output y0,y1,y2,y3; assign y0=(~s2)&(~s1)& I& en; assign y1=(~s2)& s1& I& en; assign y2=s2&(~s1)& I & en; assign y3=s2& s1 & I & en; endmodule

output NET "a" LOC = "p84"; NET "en" LOC = "p85"; NET "sel<0>" LOC =

output

output NET "a" LOC = "p84"; NET "en" LOC = "p85"; NET "sel<0>" LOC =

NET "a" LOC = "p84"; NET "en" LOC = "p85"; NET "sel<0>" LOC = "p86"; NET "sel<1>" LOC = "p87"; NET "y<0>" LOC = "p112"; NET "y<1>" LOC = "p114"; NET "y<2>" LOC = "p113"; NET "y<3>" LOC = "p115";

NET "y<3>" LOC = "p115"; Output g) 1- BIT COMPARATOR ( STRUCTURAL ) Black Box 1bit

Output

g) 1-BIT COMPARATOR (STRUCTURAL)

Black Box

1bit

Comparat

or

a

a b

b

LOC = "p115"; Output g) 1- BIT COMPARATOR ( STRUCTURAL ) Black Box 1bit Comparat or

LLOC = "p115"; Output g) 1- BIT COMPARATOR ( STRUCTURAL ) Black Box 1bit Comparat or

ELOC = "p115"; Output g) 1- BIT COMPARATOR ( STRUCTURAL ) Black Box 1bit Comparat or

GLOC = "p115"; Output g) 1- BIT COMPARATOR ( STRUCTURAL ) Black Box 1bit Comparat or

Truth table

A

B

L

E

G

0

0

0

1

0

0

1

1

0

0

1

0

0

0

1

1

1

0

1

0

VHDL CODE

VERILOG CODE

entity b_comp1 is port( a, b: in std_logic; L,E,G: out std_logic);

module b_comp1 (a, b, L, E,G); input a, b; output L, E, G; wire s1, s2; not X1(s1, a); not X2 (s2, b); and X3 (L,s1, b); and X4 (G,s2, a); xnor X5 (E, a, b); end module

end;

architecture structural of b_comp1 is component not_2 is port( a: in std_logic; b: out std_logic); end component;

component and_2 is port( a, b: in std_logic; c: out std_logic); end component;

 

component xnor_2 is port( a, b: in std_logic; c: out std_logic); end component; signal s1,s2: std_logic; begin X1: not_2 port map (a, s1); X2: not_2 port map (a, s2); X3: and_2 port map (s1, b, L); X4: and_2 port map (s2, a, G); X5: xnor_2 port map (a, b, E); end structural;

output NET "a" LOC = "p74" ; NET "b" LOC = "p75" ; NET "E"
output
NET "a" LOC = "p74" ;
NET "b" LOC = "p75" ;
NET "E" LOC = "p86" ;

NET "G" LOC = "p85" ; NET "L" LOC = "p84" ;

1-BIT COMPARATOR (DATA FLOW)

VHDL CODE

VERILOG CODE

entity bcomp is port( a, b: in std_logic; c, d, e: out std_logic); end bcomp;

module bcomp (a, b, c, d, e) input a, b; output c, d, e; assign c= (~a) & b; assign d= ~(a ^ b); assign e= a & (~b); end module

architecture dataflow of bcomp is begin c<= (not a) and b; d<= a xnor b; e<= a and (not b); end dataflow;

h) 4-BIT COMPARATOR

Black Box

a(3 to 0)

b(3 to 0)

4bit

Comparator

x

y z

y z

z

b; e<= a and (not b); end dataflow; h) 4-BIT COMPARATOR Black Box a(3 to 0)
b; e<= a and (not b); end dataflow; h) 4-BIT COMPARATOR Black Box a(3 to 0)
b; e<= a and (not b); end dataflow; h) 4-BIT COMPARATOR Black Box a(3 to 0)

VHDL CODE

VERILOG CODE

 

entity compart4bit is Port ( a,b : in std_logic_vector(3 downto 0); aeqb,agtb,altb: out std_logic);

 

module comp(a,b,aeqb,agtb,altb); input [3:0] a,b; output aeqb,agtb,altb; reg aeqb,agtb,altb;

end compart4bit;

 

architecture

Behavioral

of

always @(a or b) begin

 

compart4bit is begin process (a,b) begin if a > b then aeqb<='1';agtb<=’0’;altb<=’0’; elsif a < b then agtb<='1';aeqb<=’0’;altb<=’0’; else altb<='1'; aeqb<=’0’; agtb<=’0’; end if ; end process; end Behavioral;

aeqb=0;

agtb=0;

altb=0;

if(a==b)

aeqb=1;

else if (a>b)

 

agtb=1;

else

altb=1;

end

endmodule

output Greater than Equal to Less than
output
Greater than
Equal to
Less than

RESULT: Combinational designs have been realized and simulated using H

Experiment No. 4

AIM: Write HDL code to describe the functions of a full Adder Using three modeling styles.

COMPONENTS REQUIRED: FPGA board, FRC’s, jumper and power supply.

DATA FLOW

Black box

Truth table

a

b

c

FULL

ADDER

FULL ADDER
FULL ADDER
FULL ADDER
FULL ADDER
DATA FLOW Black box Truth table a b c FULL ADDER Sum Cout INPUTS OUTPUTS a
DATA FLOW Black box Truth table a b c FULL ADDER Sum Cout INPUTS OUTPUTS a

Sum

Cout

Black box Truth table a b c FULL ADDER Sum Cout INPUTS OUTPUTS a B cin

INPUTS

OUTPUTS

a

B

cin

SUM

Cout

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

VHDL CODE

VERILOG CODE

 

entity fulladder is Port ( a,b,c : in std_logic; s,cout : out std_logic); end fulladr;

 

module fulladder ( a, b, c,s,cout) input a, b,c; output s, cout; assign s= a ^ b^c; assign cout= a & b & c; endmodule

architecture data of fulladr is begin sum<=a xor b xor cin; cout<= ( a and b) or ( b and cin) or ( cin and a); end data;

BEHAVIORAL STYLE

VHDL CODE

VERILOG CODE

entity fulladder beh is Port ( a,b,c : in std_logic; sum,carry : out std_logic); end fulladrbeh;

 

module fulladd(cin,x,y,s,co); input cin,x,y; output s,co; reg s,co; always@(cin or x or y) begin case ({cin,x,y})

3'b000:{co,s}='b00;

architecture Behavioral of fulladrbeh is begin process( a,b,c) begin

 
 

3'b001:{co,s}='b01;

if(a='0'

and

b='0'

and

c='0')

then

sum<='0';

3'b010:{co,s}='b01;

carry<='0';

3'b011:{co,s}='b10;

elsif(a='0' and b='0' and c='1') then sum<='1';

3'b100:{co,s}='b01;

carry<='0';

3'b101:{co,s}='b10;

elsif(a='0' and b='1' and c='0') thensum<='1';

3'b110:{co,s}='b10;

carry<='0';

3'b111:{co,s}='b11;

elsif(a='0'

and

b='1' and

c='1')

thensum<='0';

endcase

carry<='1';

end

elsif(a='1' and b='0' and c='0') thensum<='1';

endmodule

carry<='0';

elsif(a='1'

and

b='0' and

c='1')

thensum<='0';

carry<='1';

elsif(a='1'

and

b='1' and

c='0')

thensum<='0';

carry<='1';

else sum<='1'; carry<='1'; end if; end process; end Behavioral;

 

STRUCTURAL STYLE

VHDL CODE

VERILOG CODE

entity fullstru is Port ( a,b,cin : in std_logic; sum,carry : out std_logic); end fullstru;

module fa (x,y,z,cout,sum); input x,y,z; output cout,sum; wire P1,P2,P3;

architecture structural of fullstru is

HA HA1 (sum(P1),cout(P2),a(x), b(y)); HA HA2 (sum(sum),carry(P3),a(P1),b(Z)); OR1 ORG (P2,P3, Cout);

endmodule

signal c1,c2,c3:std_logic; component xor_3 port(x,y,z:in std_logic; u:out std_logic);

end component;

 

component and_2 port(l,m:in std_logic; n:out std_logic);

end component;

component or_3 port(p,q,r:in std_logic; s:out std_logic); end component;

begin X1: xor_3 port map ( a, b, cin,sum); A1: and_2 port map (a, b, c1); A2: and_2 port map (b,cin,c2); A3: and_2 port map (a,cin,c3); O1: or_3 port map (c1,c2,c3,carry);

end structural;

Supporting Component Gates for Stuctural Full Adder

//and gate// library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity and2 is

Port ( l,m : in std_logic;

n : out std_logic);

end and2; architecture dataf of and2 is begin n<=l and m; end dataf;

//or gate// library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity or3 is

Port ( p,q,r : in std_logic;

s : out std_logic);

end or3; architecture dat of or3 is begin s<= p or q or r; end dat;

//xor gate// library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity xor3 is

Port ( x,y,z : in std_logic;

u : out std_logic); end xor3;

architecture dat of xor3 is begin u<=x xor y xor z; end dat;

Full adder data flow i/o pins

NET "a" LOC = "P74"; NET "b" LOC = "P75"; NET "cin" LOC = "P76"; NET "cout" LOC = "P84"; NET "sum" LOC = "P85";

LOC = "P84"; NET "sum" LOC = "P85"; Sum output carry output RESULT: Three modeling styles

Sum output

carry output

RESULT: Three modeling styles of full adder have been realized and simulated using HDL. codes.

Experiment No. 5

AIM: Write a model for 32 bit ALU using the schematic diagram shown below.

COMPONENTS REQUIRED:FPGA/CPLD board, FRC’s, jumper and power supply.

 

OPCODE

ALU OPERATION

1

A+B

2

A-B

3

A

Complement

4

A*B

5

A and B

6

A or B

7

A nand B

8

A xor B

9

Right shift

10

Left Shift

11

Parallel load

Black box

 

Truth table

ALU

A1(3 to 0)

B1(3 to 0)

Black box   Truth table ALU A1(3 to 0) B1(3 to 0) opcode (2 to 0)
Black box   Truth table ALU A1(3 to 0) B1(3 to 0) opcode (2 to 0)
Black box   Truth table ALU A1(3 to 0) B1(3 to 0) opcode (2 to 0)

opcode (2 to 0)

  Truth table ALU A1(3 to 0) B1(3 to 0) opcode (2 to 0) Zout (7

Zout (7 downto 0)

Operation

Opcode

A

B

Zout

A+B

000

1111

0000

00001111

A-B

001

1110

0010

00001100

A or B

010

1111

1000

00001111

A and B

011

1001

1000

00001000

Not A

100

1111

0000

11110000

A1*B1

101

1111

1111

11100001

A nand B

110

1111

0010

11111101

A xor B

111

0000

0100

00000100

VHDL CODE

VERILOG CODE

entity alunew is Port( a1,b1:in std_logic_vector(3 downto 0); opcode : in std_logic_vector(2 downto 0); zout : out std_logic_vector(7 downto 0)); end alunew;

module ALU ( a, b, s, en, y ); input signal [3:0]a, b; input [3:0]s; input en; output signal [7:0]y; reg y; always@( a, b, s, en, y ); begin

architecture Behavioral of alunew is signal a: std_logic_vector( 7 downto 0);

if(en==1)

signal b: std_logic_vector( 7 downto 0); begin

a<= "0000" & a1; b<= "0000" & b1;

begin case 4’d0: y=a+b; 4’d1: y=a-b; 4’d2: y=a*b; 4’d3: y={4’ bww, ~a}; 4’d4: y={4’ d0, (a & b)}; 4’d5: y={4’ d0, (a | b)}; 4’d6: y={4’ d0, (a ^ b)}; 4’d7: y={4’ d0, ~(a & b)}; 4’d8: y={4’ d0, ~(a | b)}; 4’d9: y={4’ d0, ~(a ^ b)}; default: begin end end case end

zout<=

a+b

when opcode ="000" else when opcode ="001" else

a-b

a or b

when opcode ="010" else

a and b when opcode ="011" else

not a

when opcode ="100" else

a1 * b1 when opcode ="101" else

a

nand b when opcode ="110" else

a

xor b;

end Behavioral;

 

else

y=8’d0;

end

endmodule

  else y=8’d0; end endmodule RESULT: 32 bit ALU operations have been realized and

RESULT: 32 bit ALU operations have been realized and simulated using HDL codes.

Experiment No. 6

AIM: Develop the HDL code for the following flip flop: T, D, SR, JK.

COMPONENTS REQUIRED: FPGA board, FRC’s, jumper and power supply.

T FLIPFLOP

Black Box

t

t    
   

clk

clk

T ff

clk T ff q

q

rst

rst   qb
 
rst   qb

qb

VHDL CODE

VERILOG CODE

entity tff is Port ( t,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end tff;

module tff(t,clk,rst, q,qb); input t,clk,rst; output q,qb; reg q,qb; reg temp=0; always@(posedge clk,posedge rst)

begin

architecture Behavioral of tff is signal clkd:std_logic_vector(21 downto 0); begin process(clkd) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process (clk) variable temp:std_logic:='0'; begin if rising_edge(clk) then if (t='1') then temp:=not temp; else temp:=temp; end if; end if; q<=temp;qb<=not temp; end process; end Behavioral;

if (rst==0) begin if(t==1) begin temp=~ temp; end else temp=temp;

end

q=temp;qb=~temp;

end

endmodule

Truth table

Rst

T

Clk

q

1

0

1

q

1

1

1

qb

1

X

No +ve edge

Previous state

0

X

X

0

Rising edge Output
Rising edge
Output

D FLIP-FLOP

Black Box

d

   
 
 
 

D FF

  D FF

clk

clk
clk

q

qb

VHDL CODE

entity dff is Port ( d,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end dff; architecture Behavioral of dff is signal clkd:std_logic_vector(21 downto 0); begin process(clkd) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process (clk) variable temp: std_logic; begin if rising_edge(clk) then temp:=d; end if; q<=temp;qb<=not temp; end process; end Behavioral;

std_logic; begin if rising_edge(clk) then temp:=d; end if; q<=temp;qb<=not temp; end process; end Behavioral;
std_logic; begin if rising_edge(clk) then temp:=d; end if; q<=temp;qb<=not temp; end process; end Behavioral;

VERILOG CODE

module dff(d,clk,rst,q,qb); input d,clk,rst; output q,qb; reg q,qb; reg temp=0;

always@(posedge clk,posedge rst) begin if (rst==0) temp=d; else temp=temp; q=temp;

qb=~ temp ; end endmodule

Truth table

clk

D

Q

qb

X

1

1

0

1

1

1

0

1

0

0

1

Output at rising edge
Output at rising edge

NET "clk" LOC = "P18"; NET "d" LOC = "P74"; NET "q" LOC = "P84"; NET "qb" LOC = "P85";

SR FLIP FLOP

Black Box

clk

clk    
   

s

s q

q

q

r

r SR FF

SR FF

rst

rst   qb
 
rst   qb

qb

 

pr

pr  
 

Truth table

Rst

pr

Clk

s

r

q

qb

1

X

X

X

X

0

1

0

1

X

X

X

1

0

0

0

1

0

0

Qb

Qbprevious

0

0

1

0

1

0

1

0

0

1

1

0

1

0

0

0

1

1

1

1

1

VHDL CODE

VERILOG CODE

entity srff is Port ( s,r,rst,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end srff;

module srff(s,r,clk,rst, q,qb); input s,r,clk,rst; output q,qb; reg q,qb; reg [1:0]sr; always@(posedge clk,posedge rst) begin sr={s,r};

if(rst==0)

architecture Behavioral of srff is signal clkd:std_logic_vector(21 downto 0); begin process(clkd) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process;

begin case (sr)

2'd1:q=1'b0;

2'd2:q=1'b1;

2'd3:q=1'b1;

process(clk,rst) variable sr:std_logic_vector(1 downto 0); variable temp1,temp2:std_logic:='0'; begin sr:=s&r; if (rst ='0')then if rising_edge(clk) then case sr is when "01"=> temp1:='0'; temp2:='1';

default: begin end endcase end

else

begin

q=1'b0;

end

qb=~q;

end

when "10"=> temp1:='1'; temp2:='0'; when "11"=> temp1:='1'; temp2:='1'; when others=> null; end case; end if; else temp1:='0'; temp2:='1'; end if;

endmodule

q<=temp1;qb<=temp2;

end process;

end Behavioral;

S R
S
R

output

JK FLIPFLOP

Black Box

j

j    
   

k

k q

q

 
  JK FF  

JK FF

 

clk

 
clk   qb

qb

 
 
   
 

rst

rst

VHDL CODE

VERILOG

entity jkff is Port ( j,k,rst,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end jkff; architecture Behavioral of jkff is signal clkd:std_logic_vector(21 downto 0); begin process(clkd) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clk,rst) variable jk:std_logic_vector(1 downto 0); variable temp:std_logic:='0'; begin jk:=j&k; if (rst ='0')then if rising_edge(clk) then case jk is when "01"=> temp:='0';

 

module jkff(j,k,clk,rst, q,qb); input j,k,clk,rst; output q,qb; reg q,qb; reg [1:0]jk; always@(posedge clk,posedge rst) begin jk={j,k};

if(rst==0)

begin case (jk)

2'd1:q=1'b0;

2'd2:q=1'b1;

2'd3:q=~q;

default: begin end endcase end

else

q=1'b0;

qb=~q;

when "10"=> temp:='1'; when "11"=> temp:=not temp; when others=> null; end case; end if; else temp:='0'; end if; q<=temp; qb<=not temp; end process; end Behavioral;

 

end

endmodule

Truth table

Rst

Clk

J

K

Q

Qb

1

1

0

0

Previous

state

1

1

0

1

0

1

1

1

1

0

1

0

1

1

1

1

Qb

Q

1

No+ve egde

-

-

Previous

state

0

-

-

-

0

1

- - Previous state 0 - - - 0 1 Output (when input 00 and rising

Output (when input 00 and rising edge)

NET "clk" LOC = "p18"; NET "j" LOC = "p84"; NET "k" LOC = "p85"; NET "rst" LOC = "p86"; NET "q" LOC = "p112"; NET "qb" LOC = "p114";

RESULT: Flip-flop operations have been realized and simulated using HDL codes

Experiment No. 7

AIM: Design 4 bit Binary, BCD Counter (Synchronous reset and Asynchronous reset and any sequence counters.

COMPONENTS REQUIRED: FPGA board, FRC’s, jumper and power supply.

a) BCD COUNTER

Black Box

clk

rst

BCD

counter

power supply. a) BCD COUNTER Black Box clk rst BCD counter Truth table q(3 downto 0)
power supply. a) BCD COUNTER Black Box clk rst BCD counter Truth table q(3 downto 0)
power supply. a) BCD COUNTER Black Box clk rst BCD counter Truth table q(3 downto 0)

Truth table

q(3 downto 0)

Rst

Clk

Q

1

X

0000

0

1

0001

0

1

0010

0

1

0011

0

1

0100

0

1

0101

0

1

0110

0

1

0111

0

1

1000

0

1

1001

0011 0 1 0100 0 1 0101 0 1 0110 0 1 0111 0 1 1000

VHDL CODE

VERILOG CODE

entity bcd is Port ( clr,clk,dir : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0); tc : out STD_LOGIC); end bcd; architecture Behavioral of bcd is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clkd,clr) variable temp:std_logic_vector(3 downto 0); begin

if(clr='1')then

module bcd(clr,clk,dir, tc, q); input clr,clk,dir; output reg tc; output reg[3:0] q; always@(posedge clk,posedge clr) begin

if(clr==1)

q=4'd0;

else begin if (dir==1)

q=q+1;

else if(dir==0)

q=q-1;

if(dir==1 & q==4'd10) begin

q=4'd0;tc=1'b1;

end else if(dir==0 & q==4'd15) begin

temp:="0000";tc<='0';

elsif rising_edge(clkd(21)) then if (dir='1') then

q=1'd9;tc=1'b1;

end

temp:=temp+1;

else tc=1'b0;

elsif(dir='0') then

end

temp:=temp-1;

end

end if; if(dir='1' and temp="1010") then temp:="0000"; tc<='1'; elsif(dir='0' and temp="1111") then temp:="1001"; tc<='1'; else tc<='0'; end if; end if; q<=temp; end process;

endmodule

end Behavioral;

b) GRAY COUNTER

Black Box

   
 

clk

  clk 4 bit Binary to  

4 bit

Binary to

  clk 4 bit Binary to  
 

en

en q(3 downto 0)

q(3 downto 0)

rst

rst gray  

gray

 

VHDL CODE

VERILOG CODE

entity gray is Port ( clr,clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR (2 downto 0)); end gray; architecture Behavioral of gray is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clr,clkd) variable temp:std_logic_vector(2 downto 0); begin if(clr='0') then if rising_edge(clkd(21)) then case temp is when "000"=> temp:="001"; when "001"=> temp:="011"; when "011"=> temp:="010"; when "010"=> temp:="110"; when "110"=> temp:="111"; when "111"=> temp:="101"; when "101"=> temp:="100"; when "100"=> temp:="000"; when others => null; end case; end if; else temp:="000"; end if; q<=temp; end process; end Behavioral;

module gray(clr,clk, q); input clr,clk; output reg[2:0] q; reg temp=3'd0; always@(posedge clk,posedge clr) begin

 

if(clr==0)

begin

case(temp)

3'd0:q=3'd1;

3'd1:q=3'd3;

3'd2:q=3'd6;

3'd3:q=3'd2;

3'd6:q=3'd7;

3'd7:q=3'd5;

3'd5:q=3'd4;

3'd4:q=3'd0;

endcase

end

else q=3'd0;

end

endmodule

Truth table

Rst

Clk

En

B3

B2

B1

B0

G3

G2

G1

G0

1

X

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

1

0

0

0

1

0

1

1

0

0

1

0

0

0

1

1

0

1

1

0

0

1

1

0

0

1

0

0

1

1

0

1

0

0

0

1

1

0

0

1

1

0

1

0

1

0

1

1

1

0

1

1

0

1

1

0

0

1

0

1

0

1

1

0

1

1

1

0

1

0

0

0