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CICC 2009

Michael H. Perrott September 2009

Performance is important

- Phase noise can limit wireless transceiver performance - Jitter can be a problem for digital processors - Analog building blocks on a mostly digital chip pose design and verification challenges - The cost of implementation is becoming too high

Can digital phase-locked loops offer excellent performance with a lower cost of implementation?

M.H. Perrott

ref(t) out(t) e(t) v(t) ref(t) e(t) ref(t) out(t) e(t) v(t) out(t)

Phase Detect

VCO efficiently provides oscillating waveform with variable frequency PLL synchronizes VCO frequency to input reference frequency through feedback

M.H. Perrott 4

ref(t) div(t) e(t) v(t) Fout = N Fref ref(t) Phase Detect e(t) v(t) Analog Loop Filter VCO div(t) Divider N out(t)

M.H. Perrott

5

ref(t) div(t) e(t) v(t) e(t) v(t) Analog Loop Filter VCO div(t) Nsd[k] Modulator Divider N[k]

Fout = M.F Fref

ref(t)

Phase Detect

out(t)

M.F

M.H. Perrott 6

ref(t) div(t) e(t) v(t) Fout = M.F Fref ref(t) Phase Detect e(t) v(t) Analog Loop Filter VCO div(t) Nsd[k] Modulator Divider N[k] M.F out(t)

Quantization Noise

f

7

M.H. Perrott

1 D Q reset div(t) 1 D Q

Reg

phase error

ref(t)

error(t)

ref(t)

out(t)

M.H. Perrott

Pulse width is formed according to phase difference between two signals Average of pulsed waveform is applied to VCO input

Phase Detector Signals ref(t) div(t) error(t) Phase Detector Characteristic

Average of error(t)

Phase Detect div(t) Analog Loop Filter Divider

phase error

ref(t)

out(t)

VCO

M.H. Perrott

Benefit: average of pulsed output is a continuous, linear function of phase error Issue: analog loop filter implementation is undesirable

10

error(t)

Charge Pump

ref(t)

Phase Detect

out(t)

M.H. Perrott

Charge pump: output resistance, mismatch Filter caps: leakage current, large area

11

Going Digital

ref(t) Phase Detect Analog Loop Filter VCO Divider out(t)

ref(t)

Time -toDigital

out(t)

M.H. Perrott

12

Outline of Talk

Overview of Key Blocks (TDC and DCO) Modeling & CAD Tools High Performance TDC design Quantization Noise Cancellation DCO based on an efficient passive DAC structure Divider Design Loop Filter Design Prototype with measured Results

M.H. Perrott

13

div(t)

Delay Delay Delay Delay

div(t)

D Q Reg D Q Reg D Q Reg

e[k] ref(t)

1 1 1 0 0

e[k]

ref(t)

ref(t)

out(t)

M.H. Perrott

14

Delay varies due to mismatch

div(t)

1 1 1 0 0

e[k]

detector output

phase error out(t) DCO

ref(t)

ref(t)

Integer-N PLL

- Limit cycles due to limited resolution (unless high ref noise) - Fractional spurs due to non-linearity from delay mismatch

15

Fractional-N PLL

M.H. Perrott

Modeling of TDC

Phase Detector Characteristic quantization error tq[k] tdel time error phase error[k] T 2 TDC Gain 1 tdel e[k]

detector output

out(t)

Phase error converted to time error by scale factor: TDC introduces quantization error: tq[k] TDC gain set by average delay per step: tdel M.H. Perrott

T/2

16

Analog Control

Varactor

Varactor

DAC

ref(t)

out(t)

M.H. Perrott

- Allows the use of an existing VCO within a digital PLL - Can be applied across a broad range of IC processes

17

ref(t)

Varactor

Time -toDigital div(t)

Varactor

Digital Loop Filter DCO Divider

Digital Control

out(t)

M.H. Perrott

18

Binary Array 1x 2x 4x 2 nx

Coarse Control

Varactor

Varactor

Fine Control

- Binary array: efficient control, but may lack monotonicity - Unit element array: monotonic, but complex control

- Coarse control: active only during initial frequency tuning (leverage binary array) - Fine control: controlled by PLL feedback (leverage unit

element array to guarantee monotonicity)

19

M.H. Perrott

out(t)

Coarse Initial Control Frequency

T ref(t)

Varactor

Divide-by-K

T c=T/M

Varactor

Tuning

Fine Control

Digital Modulator

DCO

TDC out

Increase resolution by dithering of fine cap array Reduce noise from dithering by

- Using small unit caps in the fine cap array - Increasing the dithering frequency (defined as 1/T )

c

M.H. Perrott

20

Varactor

Varactor

Digital Control

Phase noise

- Same as for

Quantization Noise

Phase Noise

f M

f out(t)

- See Section 3

in[k]

of Supplemental Slides

M.H. Perrott

21

Modeling

TDC TDC-referred Noise S tq(e j2fT) f tq[k] ref[k] T 2 DCO DCO-referred Noise S n(f) f TDC Gain 1 tdel Loop Filter e[k] H(z) z=ej2fT div[k] Divider CT-DT 1 N 1 T T DT-CT n(t) 2Kv s s=j2f out(t)

-20 dB/dec

M.H. Perrott

TDC and DCO-referred noise influence overall phase noise according to associated transfer functions to output Calculations involve both discrete and continuous time

23

tq[k] ref[k] div[k] 1 N T 2 TDC Gain 1 tdel Loop Filter e[k] H(z) z=ej2fT CT-DT 1 T T DT-CT 2Kv s s=j2f n(t) out(t)

TDC-referred noise

DCO-referred noise

M.H. Perrott

24

tq[k] ref[k] div[k] 1 N T 2 TDC Gain 1 tdel Loop Filter e[k] H(z) z=ej2fT CT-DT 1 T T DT-CT 2Kv s s=j2f n(t) out(t)

M.H. Perrott

25

TDC-referred noise

DCO-referred noise

M.H. Perrott

26

Key Observations

tq[k] ref[k] div[k] 1 N T 2 TDC Gain 1 tdel Loop Filter e[k] H(z) z=ej2fT CT-DT 1 T T DT-CT 2Kv s s=j2f n(t) out(t)

TDC-referred noise

Lowpass with a DC gain of 2N

DCO-referred noise

Highpass with a high frequency gain of 1 How do we calculate the output phase noise?

M.H. Perrott

27

x(t) CT CT x[k] DT DT x[k] DT CT H(f) H(f) y[k] y(t)

H(ej2fT)

y(t)

M.H. Perrott

CT DT DT

CT DT CT

28

TDC-referred Noise S tq(e j2fT) f tq[k] fo 2N G(f) fo DCO-referred Noise S n(f) f n(t) 1-G(f)

TDC noise

-20 dB/dec

DCO noise

out(t)

2 1 2N G(f) S tq(e j2fT) T

29

fo

M.H. Perrott

S tq(e j2fT)

tdel 12 f tq[k]

S out(f)

tdc

fo

2N G(f)

2 2 tdel

1 2N G(f) T f

12

fo

M.H. Perrott

30

CAD Tools

Open-Loop Design Approach G(f) = A(f) 1+A(f)

A(f) =

G(f) 1-G(f)

- Indirectly design G(f) using bode plots of A(f) - Directly design G(f) by examining impact of its specifications on phase noise (and settling time) - Solve for A(f) that will achieve desired G(f)

Implemented in PLL Design Assistant Software

http://www.cppsim.com

32

M.H. Perrott

- G(f): 500 kHz BW, Type II, 2 order rolloff - TDC noise: -94.7 dBc/Hz - DCO noise: -153 dBc/Hz at 20 MHz offset (3.6 GHz carrier)

nd

M.H. Perrott

33

-60 -70 -80 -90

Detector Noise VCO Noise Total Noise

L(f) (dBc/Hz)

4

DCO Noise

10

10

10

TDC noise too high for GSM mask with 500 kHz PLL bandwidth

M.H. Perrott 34

- G(f): 100 kHz BW, Type = 2, 2 order rolloff - TDC noise: -94.7 dBc/Hz - DCO noise: -153 dBc/Hz at 20 MHz offset (3.6 GHz carrier)

nd

M.H. Perrott

35

-60 -70 -80 -90

Detector Noise VCO Noise Total Noise

L(f) (dBc/Hz)

-100 -110

DCO Noise

-120 -130 -140 -150 -160 3 10 10

4

10

10

10

M.H. Perrott 36

- Where:

M.H. Perrott

37

Assumptions

del

- Ref freq (1/T) = 50 MHz, Out freq = 3.6 GHz (so N = 72) - t = 20 ps, K = 12 kHz/unit cap - 100 kHz bandwidth, Type = 2 , 2 order rolloff

v nd

M.H. Perrott

38

1

D Q R

Schematic

- Hierarchical

R D Q

PFD

Charge Pump

Loop Filter

Code blocks

of module behavior using templated C++ code

- Specification

Divider Modulator

CppSim Module Description Name Inputs, Outputs Parameters Code

M.H. Perrott

39

http://www.cppsim.com

M.H. Perrott 40

Two Key Issues: TDC resolution Mismatch

Motivation

TDC-referred Noise S tq(e j2fT) f tq[k] fo 2N G(f) fo DCO-referred Noise S n(f) f n(t) 1-G(f)

-20 dB/dec

PLL bandwidth dramatically influences relative impact of TDC and VCO noise

Want high PLL bandwidth? Need low TDC Noise

DCO Noise

TDC Noise

dBc/Hz

TDC Noise

dBc/Hz f

DCO Noise

fo

M.H. Perrott

fo

f

42

div(t)

Delay Delay Delay Delay

div(t)

D Q Reg D Q Reg D Q Reg

e[k] ref(t)

Delay

1 1 1 0 0

e[k]

ref(t)

Vernier

div(t)

Delay Delay Delay

div(t)

D Q Reg

D Q Reg

D Q Reg

1 1 1 0 0

e[k]

ref(t)

ref(t)

Delay2

Delay2

Delay2

e[k]

Delay2

43

M.H. Perrott

Mismatch issues are more severe than the single delay chain TDC

Delay

Vernier

div(t)

Delay Delay Delay

div(t)

D Q Reg

D Q Reg

D Q Reg

1 1 1 0 0

e[k]

ref(t)

ref(t)

Delay2

Delay2

Delay2

e[k]

Delay2

44

M.H. Perrott

Single Delay Chain Vernier

Delay Delay Delay Delay Mux D Q Reg D Q Reg D Q Reg Delay2 Delay2 Delay2 D Q Reg D Q Reg D Q Reg Delay Delay

div(t)

Fine e[k]

Delay - Delay2

Single delay chain provides coarse resolution (Folded) Vernier provides fine resolution

Delay

M.H. Perrott

45

Single Delay Chain Single Delay Chain Time Amplifier

Delay Mux D Q Reg D Q Reg D Q Reg D Q Reg D Q Reg D Q Reg Delay Delay

div(t)

Delay

Delay

Delay

Delay Amplification of Time

Fine e[k]

Single delay chain provides coarse and fine resolution Time amplification is used to improve resolution

Delay

M.H. Perrott

46

in(t) ref(t) in(t) Time Amplifier out(t) ref(t) ref(t) in(t) out(t) tout tin

D Q Latch

out(t) tin

Simplified view of: Abas, et al., Electronic Letters, Nov 2002 (note that actual implementation uses SR latch)

Metastability leads to progressively slower output transitions as setup time on latch is encroached upon

M.H. Perrott

47

Tq

Delay Delay Delay

Start

1 1 1 1 Out

Start

Stop

Registers

Tstop

1 1 0

Out

Stop Tin

Interpolate between edges to achieve fine resolution Cyclic approach can also be used for large range

48

M.H. Perrott

An Oscillator-Based TDC

Phase Error[1] Vdd Ring Oscillator div(t) ref(t) Osc(t) Reset ref(t) Logic div(t) Counter Count[k] Register e[k] e[k] Count[k] Phase Error[2]

Output e[k] corresponds to the number of oscillator edges that occur during the measurement time window Advantages

M.H. Perrott

- Extremely large range can be achieved with compact area - Quantization noise is scrambled across measurements

49

Phase Error[1] Vdd Ring Oscillator div(t) ref(t) Osc(t) Reset ref(t) Logic div(t) Counter Count[k] Register e[k] Count[k] Quant. Error[k] -q[0] e[k] q[1] -q[2] q[3] Phase Error[2]

Quantization error occurs at beginning and end of each measurement interval As a rough approximation, assume error is uncorrelated between measurements

M.H. Perrott

50

Deterministic TDC do not provide inherent scrambling For oversampling benefit, TDC error must be scrambled! Some systems provide input scrambling ( fractional-N PLL), while some others do not (integer-N PLL)

51

M.H. Perrott

Phase Error[1] Ring Oscillator Enable ref(t) Osc(t) Reset ref(t) Logic div(t) Counter Count[k] Register e[k] Count[k] Quant. Error[k] -q[0] e[k] q[1] -q[1] q[2] div(t) Phase Error[2]

- Hold the state of the oscillator between measurements - e[k] = Phase Error[k] + q[k] q[k-1] - Averaging dramatically improves resolution!

53

M.H. Perrott

Phase Error[1] Ring Oscillator Enable ref(t) div(t) Phase Error[2]

Osc. Phases(t)

11

10

Raw resolution is set by inverter delay Effective resolution is dramatically improved by averaging M.H. Perrott

54

Enable

Measurement 1

Enable

Measurement 2

Enable

Measurement 3

Enable

Measurement 4

M.H. Perrott

55

Enabled Ring Oscillator Disabled Ring Oscillator

(a)

Enable

(b)

Delay Element

Enable

Gate the oscillator by switching the inverter cores to the power supply

Vo n-1 Vo 5 Vo 4 Vo 3 Vo 2 Vo n Vo 1

Enable

M4 M3

Vo i-1

M2 M1

Vo i

M.H. Perrott

56

GRO Prototype

enable 15 Stage Gated Ring Oscillator En Dis

S Q R

enable(t) enable

Straayer, Perrott

Logic

error[k]

M.H. Perrott

57

enable 15 Stage Gated Ring Oscillator Variable Delay

S Q R

enable(t) enable

40

30

20

Logic

error[k]

Amplitude (dB)

10

-10

-20

0.1

-30 0.01

M.H. Perrott

Frequency (MHz)

10

100

58

Deadzones were caused by errors in gating the oscillator GRO injection locked to an integer ratio of FS Behavior occurred for almost all integer boundaries, and some fractional values as well Noise shaping benefit was limited by this gating error

59

M.H. Perrott

Single Input Single Output

Use multiple inputs for each delay element instead of one Allow each stage to optimally begin its transition based on information from the entire GRO phase state Key design issue is to ensure primary mode of oscillation

60

M.H. Perrott

Lee, Kim, Lee JSSC 1997

M.H. Perrott

61

Oscillation frequency near 2GHz with 47 stages Reduces effective delay per stage by a factor of 5-6! Represents a factor of 2-3 improvement compared to previous multi-path oscillators

62

M.H. Perrott

N-Stage Gated Ring Oscillator Enable

2 counters per stage * 47 stages = 94 counters each at 2GHz Power consumption for these counters is unreasonable Need a more efficient way to measure the multi-path GRO

M.H. Perrott

63

M.H. Perrott

- A single counter for coarse phase information (keeps track of phase wrapping) - GRO phase state for fine count information

64

M.H. Perrott

Multi-path structure leads to ambiguity in edge position Partition into 7 cells to avoid such ambiguity Requires 7 counters rather than 1, but power still OK

65

Start Stop Timing Generation Enable 47-stage Gated Ring Oscillator Z1-47 State Register Start Stop Enable CLK 1 2 3 4 5 6 7 Measurement Cells Out

CLK

Adder

66

M.H. Perrott

65,536 pt. FFT

-40 -50 -60 -70 -80 -90

Noise of 80fsrms in 1MHz BW

Input of 1.2pspp

279.2

279.0

278.8

-100

1.2ps

278.6 0 40 80 120 160 200

104

105

106

107

Frequency (Hz)

Time (s)

(a)

(b)

Data collected at 50Msps More than 20dB of noise-shaping benefit 80fsrms integrated error from 2kHz-1MHz Floor primarily limited by 1/f noise (up to 0.5-1MHz)

67

M.H. Perrott

- 94, 188, 282, etc. - No deadzones for other even or odd integers, fractional output

68

M.H. Perrott

Ref PFD Div

N/N+1

Loop Filter

Out

Quantization Noise Spectrum

Frequency Selection

Fout

PLL dynamics

M.H. Perrott

70

M.H. Perrott

Phase error due to is predicted by accumulating quantization error Gain matching between PFD and D/A must be precise

71

Scale factor determined by simple digital correlation Analog non-idealities such as DC offset are completely eliminated

M.H. Perrott

72

10 us

See analog version of this technique in Swaminathan et.al., ISSCC 2007 M.H. Perrott

73

M.H. Perrott

Gated-ring-oscillator (GRO) TDC achieves low in-band noise All-digital quantization noise cancellation achieves low out-of-band noise Design goals:

- 3.6-GHz carrier, 500-kHz bandwidth - <-100dBc/Hz in-band, <-150 dBc/Hz at 20 MHz offset

74

M.H. Perrott 75

Dual-Port LC VCO

Frequency tuning:

M.H. Perrott

- Use a small 1X varactor to minimize noise sensitivity - Use another 16X varactor to provide moderate range - Use a four-bit capacitor array to achieve 3.3-4.1 GHz range

76

Goals of 10-bit DAC

1X varactor minimizes noise sensitivity 16X varactor provides moderate range A four-bit capacitor array covers 3.3-4.1GHz

M.H. Perrott

- Monotonic - Minimal active circuitry and no transistor bias currents - Full-supply output range

77

L DD H

- Resistor ladder forms V = M/32V and V = (M+1)/32V , where M ranges from 0 to 31 - N unit capacitors charged to V , and (32-N) unit capacitors

DD

M.H. Perrott

charged to VL

78

Connect Together

u load

M.H. Perrott

79

M.H. Perrott

Issues:

GRO range must span entire reference period during initial lock-in

80

M.H. Perrott

81

M.H. Perrott

82

Vc(t) varies Vf(t) is held at midpoint Vc(t) is frozen to take quantization noise away quantization noise cancellation is enabled

83

M.H. Perrott

M.H. Perrott

Set zero (62.5kHz) and first pole (1.1MHz) digitally Set second pole (3.1MHz) by capacitor ratio

84

Accumulator Gain K2 first-order IIR 1- 1-z-1 1 1-z-1 Gain K1

ref[k] div[k]

T 2

TDC Loop Gain Filter e[k] 1 H(z) tdel z=ej2fT divider 1 Nnom

DAC Gain V 2B

DT-CT T

out(t)

CT-DT 1 T

M.H. Perrott

85

DAC thermal noise impacts performance due to the higher coarse VCO gain

86

M.H. Perrott

Bypass to divider for feedforward path allows coarse DAC bandwidth to be dramatically reduced!

87

M.H. Perrott

ref[k] div[k] Kc 2 first-order TDC IIR Gain 1 e[k] 1- tdel 1-z-1 Accum. 4 1 1-z-1 1 64 Divider z-1 1-z-1 1 Nnom DAC Gain V 2B DT-CT T VCO 2Kvc s s=j2f CT-DT 1 T out(t)

T 2

Routing of signal path into Sigma-Delta controlling the divider yields a feedforward path

- Adds to accumulator path as both signals pass back through the divider - Allows reduction of coarse DAC bandwidth

Noise impact of coarse DAC on VCO is substantially lowered

M.H. Perrott

88

0.13-m CMOS Active area: 0.95 mm2 Chip area: 1.96 mm2 VDD: 1.5V Current:

GRO-TDC:

2.3mA 157X252 um2

M.H. Perrott

89

Divider

1.4mW (3%) 2.8mW Ref. Buffer (6%) 3.0mW (7%) 3.4mW GRO-TDC (7%)

DAC

VCO

21.0mW (46%)

Digital

M.H. Perrott

Notice GRO and digital quantization noise cancellation have only minor impact on power (and area)

90

Suppresses quantization noise by more than 15 dB Achieves 204 fs (0.27 degree) integrated noise (jitter) Reference spur: -65dBc

M.H. Perrott

91

40 VCO Noise Finepath Quantization Noise Finetune DAC Thermal Coarsetune DAC Thermal Divider Noise (1% left) GRO Noise Ref Noise Closeloop Noise

60

80

dBc/Hz

100

120

140

160

180 3 10

10

10

10 foffset

10

M.H. Perrott

92

-50

Spur (dBc) -60 -65 -70 -75 3.62 3.63 3.64 3.65 3.66 frequency (GHz) 3.67

16.2us

93

M.H. Perrott

Conclusions

TDC (or Ref) noise dominates at low frequency offsets DCO noise dominates at high frequency offsets

Behavioral simulation tools such as CppSim allow architectural investigation and validation of calculations TDC structures are an exciting research area

M.H. Perrott 94

Supplemental Slides

Section 1: Digital Fractional-N Frequency Synthesizers

5 N[k] 4 out(t) div(t) ref(t) e[k]

ref(t)

Time e[k] Digital -toLoop Filter Digital div(t) N[k] DCO Divider

out(t)

M.H. Perrott

96

out(t) div(t) ref(t) e[k] cnt[k] 5 4 e[k] Time Phase Reg -toUnwrap Digital Reg Re-time ref(t) signal cnt[k] div(t) Reg out(t)

ref(t)

Wrap e[k] by feeding delay chain in TDC with out(t) Counter provides information of when wrapping occurs

97

M.H. Perrott

Key Issues

ref(t) e[k] Time Phase Reg -toUnwrap Digital Reg Re-time ref(t) signal cnt[k] div(t) Reg Digital Loop Filter DCO count reset out(t)

Counter, re-timing register, and delay stages of TDC must operate at very high speeds

See Staszewski et. al, JSSC, Dec 2005

M.H. Perrott

98

5 N[k] 4 out(t) div(t) ref(t) e[k]

ref(t)

Time e[k] Digital -toLoop Filter Digital div(t) DCO Divider N[k]

out(t)

4.25

Accum

M.H. Perrott

99

Accumulator residue corresponds to an estimate of the instantaneous phase error of the PLL

- Fractional value (i.e., 0.25) yields the slope of the residue - Carry out signal accurately predicts when a VCO cycle

should be swallowed

ref(t) Time e[k] Digital -toLoop Filter Digital div(t) DCO Divider Carry Out Residue Carry Out out(t)

Carry out signal is asserted when the phase error deviation (i.e. residue) exceeds one VCO cycle

N.Frac = 4.25

Accum

Frac =0.25

M.H. Perrott

100

- Dramatic reduction of spurious noise - Noise shaping for improved in-band noise - Maintains bounded phase error signal

ref(t) Time e[k] Digital -toLoop Filter Digital div(t) DCO Divider N[k]

out(t)

Nsd[k]

Modulator

M.H. Perrott

101

TDC TDC-referred Noise S tq(e j2fT) f tq[k] ref[k] T 2 DCO DCO-referred Noise S n(f) f TDC Gain 1 tdel Loop Filter e[k] H(z) z=ej2fT div[k] Divider 1 Quantization Noise n[k] S q(e j2fT) f Nnom

-1 z 2 1-z-1 z=ej2fT

-20 dB/dec

DT-CT T

CT-DT 1 T

Divider model is expanded to include the impact of divide value variations M.H. Perrott

102

TDC-referred DCO-referred Noise Noise S n(f) S tq(e j2fT) -20 dB/dec Quantization Noise j2 fT S q(e ) fo f n[k]

-1 2 z 1-z-1

f tq[k] 2NnomG(f) fo

f n(t) 1-G(f)

- High PLL

T G(f) fo out(t)

z=ej2fT

M.H. Perrott

2

103

www.cppsim.com

104

M.H. Perrott

Supplemental Slides

Section 2: DCO Modeling

out(t)

Coarse Initial Control Frequency

T ref(t)

Varactor

Divide-by-K

T c=T/M

Varactor

Tuning

Fine Control

Digital Modulator

DCO

TDC out

Increase resolution by dithering of fine cap array Reduce noise from dithering by

- Using small unit caps in the fine cap array - Increasing the dithering frequency (defined as 1/T )

c

M.H. Perrott

106

Digital Upsampler Modulator inq[m] insd[m] in[k] M Zero-Order Hold

1 0 Tc

incap(t) t Kv

in[k]

insd[m]

inq[m]

incap(t)

m Tc

t Tc

- Clocked at 1/T (i.e., reference frequency) - Clocked at 1/T = M/T - Held at a given setting for duration T

c c

M.H. Perrott

- Units of K

107

Digital Upsampler Modulator insd[m] inq[m] in[k] M Zero-Order Hold

1 0 Tc

incap(t) t Kv

M 0 1/MTc

Zero-Order Hold

Tc

0 1/Tc

z=ej2fTc

Upsampler and zero-order hold correspond to discrete and continuous-time sinc functions, respectively has signal and noise transfer functions (Hstf(z), Hntf(z))

M.H. Perrott

- Note: var(q

raw[k])

108

M Digital qraw[k] Modulator Upsampler by M in[k]

M 0 1/MTc

Tc

Hntf(z)

Zero-Order Hold

Tc

Hstf(z)

0 1/Tc

z=ej2fTc

frequencies of interest Upsampler is approximated as a gain of M Zero-order hold is approximated as a gain of Tc

M.H. Perrott

Assume Hstf(z) = 1

109

Quantization Noise qraw[k] Hntf(z) f in[k] M Tc z=ej2fTc f 2Kv s s=j2f out(t) Phase Noise

q[k]

Proper design of DCO will yield quantization noise that is below that of the intrinsic phase noise (set by tank Q, etc.)

110

f out(t)

simplified model

DT-CT in[k] T

M.H. Perrott

Supplemental Slides

Section 3: Derivation of VCO Quantization Noise Due to Capacitor Dithering

Quantization Noise qraw[k] Hntf(z) f in[k] M Tc z=ej2fTc f 2Kv s s=j2f out(t) Phase Noise

q[k]

DT to CT spectral calculation:

-S -H

M.H. Perrott

qraw(f)

= 1/12 since qraw[k] uniformly distributed from 0 to 1 -1 -1 2 ntf(z) is often 1-z (first order) or (1-z ) (second order)

112

- Dithering frequency is 200 MHz (i.e., 1/T = 200e6) - has first order shaping (i.e., H (z) = 1 - z ) - Fine cap array yields 12 kHz/unit cap (i.e., K = 12e3)

c ntf -1 v

M.H. Perrott 113

Supplemental Slides

Section 4: Derivation of Discrete-Time Loop Filter Parameterization based on Continuous-Time Specifications

PLL Design Assistant assumes continuous-time open loop transfer function Acalc(s):

Above parameters are calculated based on the desired closed loop PLL bandwidth, type, and order of rolloff (which specify G(s)) For 100 kHz bandwidth, type = 2, 2nd order rolloff, we have:

10 p z

M.H. Perrott

115

tq[k] ref[k] div[k] 1 N T 2 TDC Gain 1 tdel Loop Filter e[k] H(z) z=esT T CT-DT 1 T DT-CT 2Kv s s=j2f n(t) out(t)

At low frequencies (i.e., |sT| << 1), we can use the first order term of a Taylor series expansion to approximate

M.H. Perrott

116

Given the continuous-time approximation of A(s), we then leverage the PLL Design Assistant calculation:

M.H. Perrott

117

- Where:

Note: Tdco= T/N

M.H. Perrott 118

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