Programmable Logic

! Regular logic
" Programmable Logic Arrays " Multiplexers/Decoders " ROMs
Random Logic Full Custom Design

! Field Programmable Gate Arrays

" Xilinx Vertex

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Regular Logic Structured Design

Programmable Logic Arrays (PLAs)

! Pre-fabricated building block of many AND/OR gates
" Actually NOR or NAND " Personalized" by making or breaking connections among gates " Programmable array block diagram for sum of products form
inputs

AND array

product terms

OR array

outputs
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Enabling Concept
! Shared product terms among outputs
example: F0 F1 F2 F3 = = = = A + A C' B' C' B' C B' C' + AB + AB + A input side: 1 = uncomplemented in term 0 = complemented in term = does not participate F2 1 0 0 1 0 F3 0 1 0 0 1 output side: 1 = term connected to output 0 = no connection to output reuse of terms

personality matrix product term AB B'C AC' B'C' A inputs A B 1 1 0 1 0 1 outputs F0 F1 0 1 0 0 0 1 1 0 1 0

C 1 0 0

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Before Programming
! All possible connections available before "programming"
" In reality, all AND and OR gates are NANDs

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After Programming
! Unwanted connections are "blown"
" Fuse (normally connected, break unwanted ones) " Anti-fuse (normally disconnected, make wanted connections)
A B C

AB B'C AC' B'C' A

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F0

F1

F2

F3

Alternate Representation for High Fan-in Structures

! Short-hand notation--don't have to draw all the wires
" Signifies a connection is present and perpendicular signal is an input to gate notation for implementing
F0 = A B + A' B' F1 = C D' + C' D A B C D AB A'B' CD' C'D

AB+A'B' CD'+C'D
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Programmable Logic Array Example

! Multiple functions of A, B, C
" F1 = A B C " F2 = A + B + C " F3 = A' B' C' " F4 = A' + B' + C' " F5 = A xor B xor C " F6 = (A xnor B xnor C)
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F1 0 0 0 0 0 0 0 1 F2 0 1 1 1 1 1 1 1 F3 1 0 0 0 0 0 0 0 F4 1 1 1 1 1 1 1 0 F5 0 1 1 0 1 0 0 1 F6 0 1 1 0 1 0 0 1 A B C full decoder as for memory address bits stored in memory A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC

F1 F2 F3 F4 F5 F6

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PLA Design Example

! BCD to Gray code converter
A 0 0 0 0 0 0 0 0 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 1 C 0 0 1 1 0 0 1 1 0 0 1 D 0 1 0 1 0 1 0 1 0 1 W 0 0 0 0 0 1 1 1 1 1 X 0 0 0 0 1 1 0 0 0 0 Y 0 0 1 1 1 1 1 1 0 0 Z 0 1 1 0 0 0 0 1 1 0
A 0 0 C 0 0 0 1 1 1 B X X X X 1 1 X X D 0 0 C 0 0 1 1 0 0 B X X X X A 0 0 X X D

K-map for W
A 0 0 C 1 1 1 1 1 1 B X X X X 0 0 X X D

K-map for X
A 0 1 C 0 1 0 0 1 0 B X X X X 1 0 X X D

minimized functions: W=A+BD+BC X = B C' Y=B+C Z = A'B'C'D + B C D + A D' + B' C D'

K-map for Y

K-map for Z

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PLA Design Example (contd)

! Code converter: programmed PLA
A B C D A BD BC BC' B C A'B'C'D BCD AD' BCD' W X Y Z

minimized functions: W=A+BD+BC X = B C' Y=B+C Z = A'B'C'D + B C D + A D' + B' C D' not a particularly good candidate for PLA implementation since no terms are shared among outputs however, much more compact and regular implementation when compared with discrete AND and OR gates

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PLA Design Example

! BCD to Gray code converter
A 0 0 0 0 0 0 0 0 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 1 C 0 0 1 1 0 0 1 1 0 0 1 D 0 1 0 1 0 1 0 1 0 1 W 0 0 0 0 0 1 1 1 1 1 X 0 0 0 0 1 1 0 0 0 0 Y 0 0 1 1 1 1 1 1 0 0 Z 0 1 1 0 0 0 0 1 1 0
A 0 0 C 0 0 0 1 1 1 B X X X X 1 1 X X D 0 0 C 0 0 1 1 0 0 B X X X X A 0 0 X X D

K-map for W
A 0 0 C 1 1 1 1 1 1 B X X X X 0 0 X X D

K-map for X
A 0 1 C 0 1 0 0 1 0 B X X X X 1 0 X X D

minimized functions: W= X= Y= Z=

K-map for Y
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K-map for Z

PLA Design Example #1

! BCD to Gray code converter
A 0 0 0 0 0 0 0 0 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 1 C 0 0 1 1 0 0 1 1 0 0 1 D 0 1 0 1 0 1 0 1 0 1 W 0 0 0 0 0 1 1 1 1 1 X 0 0 0 0 1 1 0 0 0 0 Y 0 0 1 1 1 1 1 1 0 0 Z 0 1 1 0 0 0 0 1 1 0
A 0 0 C 0 0 0 1 1 1 B X X X X 1 1 X X D 0 0 C 0 0 1 1 0 0 B X X X X A 0 0 X X D

K-map for W
A 0 0 C 1 1 1 1 1 1 B X X X X 0 0 X X D

BC

K-map for X
A 0 1 0 0 1 0 B X X X X 1 0 X X D

minimized functions: W= X= Y= Z=

C 0 1

K-map for Y
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K-map for Z

PLA Design Example #2

! Magnitude comparator
A 1 0 C 0 0 0 1 0 0 B 0 0 1 0 0 0 0 1 D 0 1 C 1 1 1 0 1 1 B 1 1 0 1 A 1 1 1 0 D

A B

C D A'B'C'D' A'BC'D ABCD AB'CD' AC' A'C B'D BD'

K-map for EQ
A 0 1 C 1 1 0 0 1 1 B 0 0 0 0 0 0 1 0 D

K-map for NE
A 0 0 C 0 0 1 0 0 0 B 1 1 0 1 1 1 0 0 D

A'B'D B'CD ABC BC'D'

K-map for LT

K-map for GT
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EQ NE LT GT

Multiplexer/Demultiplexer: Making Connections

! Direct point-to-point connections between gates ! Multiplexer: route one of many inputs to a single output ! Demultiplexer: route single input to one of many outputs
control control

multiplexer

demultiplexer

4x4 switch

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Multiplexers/Selectors
! Multiplexers/Selectors: general concept
" 2n data inputs, n control inputs (called "selects"), 1 output " Used to connect 2n points to a single point " Control signal pattern forms binary index of input connected to output I I A Z
Z = A' I 0 + A I 1 A 0 1 Z I0 I1 0 0 0 0 1 1 1 1
1

functional form logical form two alternative forms for a 2:1 Mux truth table
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0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 1 0 0 1 1 1

Multiplexers/Selectors (cont'd)
! 2:1 mux: ! 4:1 mux: ! 8:1 mux: Z = A' I0 + A I1 Z = A' B' I0 + A' B I1 + A B' I2 + A B I3 Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 + AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7
2 n -1 k=0

! In general, Z = !

(mkIk)
I0 I1 I2 I3 I4 I5 I6 I7

" in minterm shorthand form for a 2n:1 Mux

I0 I1

2:1 mux A

I0 I1 I2 I3

4:1 mux A B

8:1 mux

A B C

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Cascading Multiplexers
! Large multiplexers implemented by cascading smaller ones
I0 I1 I2 I3 I4 I5 I6 I7 4:1 mux 8:1 mux 2:1 mux 4:1 mux Z I0 I1 I2 I3 A I4 I5 I6 I7 alternative implementation 2:1 mux 2:1 mux 2:1 mux 2:1 mux C A B 8:1 mux

B C

4:1 mux

control signals B and C simultaneously choose one of I0, I1, I2, I3 and one of I4, I5, I6, I7 control signal A chooses which of the upper or lower mux's output to gate to Z

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Multiplexers as Lookup Tables (LUTs)

! 2n:1 multiplexer implements any function of n variables
" With the variables used as control inputs and " Data inputs tied to 0 or 1 " In essence, a lookup table

! Example:
" F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB'(0) + AB(1)
1 0 1 0 0 0 1 1 0 1 2 3 4 8:1 MUX 5 6 7 S2 S1 S0 A B C

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Multiplexers as LUTs (contd)

! 2n-1:1 mux can implement any function of n variables ! Example:
" With n-1 variables used as control inputs and " Data inputs tied to the last variable or its complement " F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB'(0) + AB(1)
1 0 1 0 0 0 1 1 0 1 2 3 4 8:1 MUX 5 6 7 S2 S1 S0 A B C A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 1 0 1 0 0 0 1 1 C' C' 0 1 C' C' 0 1 0 1 4:1 MUX 2 3 S1 S0 A B

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Multiplexers as LUTs (contd)

! Generalization
I0 n-1 mux control variables single mux data variable . . I1 . . . . . In-1 In . . . . 0 1 0 0 0 0 1 In F 1 0 In' 1 1 1 four possible configurations of truth table rows can be expressed as a function of I n

! Example: F(A,B,C,D) implemented by an 8:1 MUX

A
1 1 1 0 0 0 1 1 1 0 0 1 1 0 1 0
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choose A,B,C as control variables D multiplexer implementation

1 D 0 1 D D D D

0 1 2 3 4 8:1 MUX 5 6 7 S2 S1 S0 A B C

Announcements
! We took everyone on the wait list into the class
" Result is that Tu labs are very crowded! " Th night lab is very light -- think of switching to get more TA face time! " Send email to pokai@berkeley.edu to request a lab change

! First HW due Friday at 2 PM just before Lab Lecture

" CS 150 hand-in box outside and just to the right of 125 Cory doors

! Second HW on class web site ! Use ucb.class.cs150 newsgroup for lab, hw, course questions!

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Demultiplexers/Decoders
! Decoders/demultiplexers: general concept
" Single data input, n control inputs, 2n outputs " Control inputs (called selects (S)) represent binary index of output to which the input is connected " Data input usually called enable (G)
1:2 Decoder: O0 = G S O1 = G S O0 O1 O2 O3 2:4 Decoder: = G S1 = G S1 = G S1 = G S1 S0 S0 S0 S0 O0 O1 O2 O3 O4 O5 O6 O7 = = = = = = = = 3:8 Decoder: G S2 S1 S0 G S2 S1 S0 G S2 S1 S0 G S2 S1 S0 G S2 S1 S0 G S2 S1 S0 G S2 S1 S0 G S2 S1 S0

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Demultiplexers as General-Purpose Logic

! n:2n decoder implements any function of n variables
" With the variables used as control inputs " Enable inputs tied to 1 and " Appropriate minterms summed to form the function
0 1 2 3 3:8 DEC 4 5 6 7 S2 S1 S0 A B C
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A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC

demultiplexer generates appropriate minterm based on control signals (it "decodes" control signals)

Demultiplexers as General-Purpose Logic (contd)

! F1 = A' B C' D + A' B' C D + A B C D ! F2 = A B C' D + A B C ! F3 = (A' + B' + C' + D')
4:16 DEC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A'B'C'D' A'B'C'D A'B'CD' A'B'CD A'BC'D' A'BC'D A'BCD' A'BCD AB'C'D' AB'C'D AB'CD' AB'CD ABC'D' ABC'D ABCD' ABCD F1

Enable

F2

F3

A B C D
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Cascading Decoders
! 5:32 decoder
" 1x2:4 decoder " 4x3:8 decoders
0 2:4 DEC 1 2 S1 S0 3 A B 0 1 2 3:8 DEC 3 4 5 6 7 S2 S1 S0 A'B'C'D'E' 0 1 2 3:8 DEC 3 4 5 6 7 S2 S1 S0

A'BC'DE'

0 1 2 3:8 DEC 3 4 5 6 7 S2 S1 S0 C D E

ABCDE

0 1 2 3:8 DEC 3 4 5 6 7 S2 S1 S0 C D E

AB'C'D'E'

AB'CDE

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Read-only Memories
! Two dimensional array of 1s and 0s
" Entry (row) is called a "word" " Width of row = word-size " Index is called an "address" " Address is input " Selected word is output
n 2 -1 i decoder j 0 internal organization 0 n-1 Address bit lines (normally pulled to 1 through resistor !selectively connected to 0 by word line controlled switches) word[i] = 0011 word[j] = 1010 1 1 1 1 word lines (only one is active !decoder is just right for this)

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ROMs and Combinational Logic

! Combinational logic implementation (two-level canonical form) using a ROM
F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C' A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F0 0 1 0 0 1 1 0 0 F1 0 1 1 0 0 0 0 1 F2 1 1 0 0 1 0 0 0 F3 0 0 0 1 1 0 1 0 ROM 8 words x 4 bits/word

A B C F0F1F2F3 address outputs block diagram

truth table

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ROM Structure
! Similar to a PLA structure but with a fully decoded AND array
" Completely flexible OR array (unlike PAL)
n address lines inputs

decoder

2n word lines

memory array (2n words by m bits)

outputs m data lines

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ROM vs. PLA

! ROM
" " " " " " " " " " " " " " Design time is short (no need to minimize output functions) Most input combinations are needed (e.g., code converters) Little sharing of product terms among output functions Size doubles for each additional input Can't exploit don't cares Cheap (high-volume component) Can implement any function of n inputs Medium speed Design tools are available for multi-output minimization There are relatively few unique minterm combinations Many minterms are shared among the output functions Most complex in design, need more sophisticated tools Can implement any function up to a product term limit Slow (two programmable planes)
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! PLA

Field-Programmable Gate Arrays

! PLAs: 100s of gate equivalents ! FPGAs: 1000-10000s gates ! Logic blocks ! Interconnect ! I/O blocks
" Implement combinational and sequential logic

" Wires to connect inputs and outputs to logic blocks " Special logic blocks at periphery of device for external connections " How to make logic blocks programmable? " How to connect the wires? " After the chip has been fabbed
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! Key questions:

Tradeoffs in FPGAs
! Logic block - how are functions implemented: fixed functions (manipulate inputs) or programmable?
" Support complex functions, need fewer blocks, but they are bigger so less of them on chip " Support simple functions, need more blocks, but they are smaller so more of them on chip

! Interconnect
" How are logic blocks arranged? " How many wires will be needed between them? " Are wires evenly distributed across chip? " Programmability slows wires down !are some wires specialized to long distances? " How many inputs/outputs must be routed to/from each logic block? " What utilization are we willing to accept? 50%? 20%? 90%?
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Xilinx 4000 Series Programmable Gate Arrays

! CLB - Configurable Logic Block
" 5-input, 1 output function " or 2 4-input, 1 output functions " optional register on outputs
IOB IOB IOB IOB

! Built-in fast carry logic ! Can be used as memory ! Three types of routing
" direct " general-purpose " long lines of various lengths

IOB

IOB

CLB

CLB

Wiring Channels
IOB

" can be reconfigured

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The Xilinx 4000 CLB

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IOB

! RAM-programmable

CLB

CLB

Two 4-Input Functions, Registered Output

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5-Input Function, Combinational Output

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CLB Used as RAM

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Xilinx 4000 Interconnect

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Xilinx FPGA Combinational Logic Examples

! Key: General functions are limited to 5 inputs
" (4 even better - 1/2 CLB) " No limitation on function complexity

! Example
" 2-bit comparator: A B = C D and A B > C D implemented with 1 CLB (GT) F = A C' + A B D' + B C' D' (EQ) G = A'B'C'D'+ A'B C'D + A B'C D'+ A B C D

! Can implement some functions of > 5 input

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Xilinx FPGA Combinational Logic

! Examples
" N-input majority function: 1 whenever n/2 or more inputs are 1 " N-input parity functions: 5 input/1 CLB; 2 levels yield 25 inputs!
5-input Majority Circuit CLB 9 Input Parity Logic

CLB 7-input Majority Circuit CLB CLB CLB

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CLB

Xilinx FPGA Adder Example

! Example
" 2-bit binary adder - inputs: A1, A0, B1, B0, CIN outputs: S0, S1, Cout
A2 B2 A1 B1 A0 B0 Cin

A3 B3

CLB

CLB

CLB

CLB

Full Adder, 4 CLB delays to final carry out

S0

Cout

S3

C2

S2

C1

S1

C0

A3 B3 A2 B2

A1 B1 A0 B0 Cin

CLB S3 Cout

S2

CLB S1 C2

S0

2 x Two-bit Adders (3 CLBs each) yields 2 CLBs to final carry out

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Combinational Logic Implementation Summary

! Regular Logic Structures
" Programmable Logic Arrays
# Programmable connections: AND-OR (NOR-NOR) Arrays

" Multiplexers/decoders
# Multipoint connections for signal routing # Lookup Tables

" ROMs
# Truth table in hardware

" Field Programmable Gate Arrays (FPGAs)

# Programmable logic (LUTs, Truth Tables) and connections

" Advantages/disadvantages of each

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