Department of Computer Science & Engineering )acu!

t% Name :Ch* Satish +umar ,e''% Name of the Subject: MP&I Branch: III CSE I Semester Lecture Duration : 4 Min Lesson P!an Suggeste' "opics as per #N"$ s%!!abus "eaching L*No* "opics to be co&ere' Page No BooMetho's $nit I L1 Architecture of 8085, Registers R4 2.2 BB L2 Pin diagram, nterru!ts, Addressing "odes R4 2.2 BB nstruction sets L# An overview of 8085 R4 2.25 BB L4 Architecture of 808$ %1 4 BB L5 Architecture of 808$ "icro!rocessor "emor& segmentation, '(ag register %1 $ BB /!ecia( functions of 1enera( Pur!ose 1enera( data registers, segment registers, L$ %1 2 BB registers Pointers 808$ '(ag register and function of L) %1 ) BB 808$ f(ags nde* registers ,+escri!tion of ,ach f(ag -its mmediate, +irect, Register, Register ndirect, L8 %1 41 BB nde*ed, Register Re(ative Based nde*ed Re(ative -ased nde*ed Addressing modes of 808$ +ata co&2transfer nstructions, Arithmetic and L. %1 4$ BB Logica( nstructions, Branch nstructions, machine 0ontro( L10 %1 $. BB nstructions, '(ag "ani!u(ation nstructions nstruction set of 808$, Assem-(er /hift and Rotate nstructions and string L11 %1 $$, )4 BB +irectives instructions, +efining each with e*am!(e L12 /am!(e !rograms %1 10# BB %echni3ues to !ass in!ut data to !rocedures, L1# /am!(e !rograms, !rocedures and R4 4.5. BB +efining a "A0R4,Passing !arameter to a "acros "A0R4 $nit II L14 ALP for (ogica( instructions %1, R4 10#, 4.8) BB L15 ,*am!(es %1, R4 10#, 4.8) BB Assem-(& (anguage !rograms L1$ ALP for Branch and 0a(( instructions %1, R4 10#, 4.8) BB L1) invo(ving (ogica(, Branch 5 0a(( ,*am!(es %1, R4 10#, 4.8) BB instructions, sorting, eva(uation of L18 arithmetic e*!ressions, string ALP for sorting and arithmetic instructions %1, R4 10#, 4.8) BB L1. mani!u(ation ,*am!(es %1, R4 10#, 4.8) BB L20 ALP for /tring nstructions %1, R4 10#, 4.8) BB L21 ,*am!(es %1, R4 10#, 4.8) BB $nit III /igna( +escri!tions of 808$,"inimum "ode L22 Pin diagram of 808$6"inimum mode %1 8,21,2# BB 808$ s&stem and timings and ma*imum mode of o!eration, "a*imum "ode 808$ s&stem and timings, L2# %iming diagram %1 25 BB 74L+ res!onse se3uence. "emor& interfacing to 808$ 8/tatic L24 /tatic RA" nterfacing %1, R4 158, 4.80 BB RA" 5 ,PR4"9 L25 +&namic RA" nterfacing %1, R4 1$), 4.80 BB nterna( Architecture of 825), Register L2$ %1 2.4 BB 4rgani;ation :eed for +"A. +"A data transfer L2) "ethod, nterfacing with 82#)2825) /igna( descri!tions, +"A transfer o!erations %1 2.8 BB L28 nterfacing 825) with 808$ %1 #0# BB $nit I( L2. nterna( Architecture,Pin +iagram, %1 184 BB 8255 PP < various modes of o!eration and interfacing to 808$

8255 PP < various modes of o!eration "odes of 4!eration of 8255, nterfacing 8255 L#0 and interfacing to 808$ !orts with 808$ L#1 nterfacing @e&-oard, nterfacing with 808$ L#2 +is!(a&s f(ow chart for ALP L## 82). /te!!er "otor and actuators nterfacing with 808$ L#4 nterfacing A+008082080. +2A and A2+ converter interfacing L#5 nterfacing +A00800 $nit ( nterru!t structure of 808$,Aector L#$ nterru!t 0&c(e of 808$28088 interru!t ta-(e, nterru!t service :on "asBa-(e nterru!t and "asBa-(e nterru!t L#) routines ntroduction to +4/ and B 4/ L#8 4verview interru!ts L#. Architecture and signa( descri!tions of 825. 825. P 0 Architecture and interfacing nterru!t se3uence and 0ommand words of 825. L40 cascading of interru!t contro((er and L41 its im!ortance o!eration modes of 825. L42 nterfacing and !rogramming 825. $nit (I /eria( data transfers,As&nchronous and L42 "ethods of +ata 0ommunication /&nchronous data transfer schemes L4# 8251 =/AR% architecture and Architecture and /igna( +escri!tions of 8251 L44 interfacing 8251 4!eration modes L45 %%L to R/ 2#20 and R/2#20 to %%L nterfacing 8251 with 808$ conversion,/am!(e !rogram of seria( ,*am!(e Programme L4$ data transfer L4) ,,, 488 1P B $nit (II L48 Architecture 4verview of 8051 "icro 0ontro((er L4. 24 Ports,"emor& 4rgani;ation L50 Adressing modes L51 nstruction set of 8051, Register ,+irect and ndirect Addressing modes B&te (eve( (ogica( o!erations,Bit (eva( (ogica( o!erations,Rotate and /wa! 4!erations,Arithmetic 4!erations

%1 %1 %1 %1 %1 %1 %2 %2 %2 %2 %2 %2 %2 %1 %1 %1 %1 %1

18) 1.0, 1.$ 1.# 228 212 224 1#8 141 24. 24. 252 25$ 25. 2)8 2)8 282 28) 28)

BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB

%2 %2 %2 %2 %2

1$ 28 #$ 15# 1$.

L52 /im!(e Programs $nit (III L5# %imer20ounter o!eration in 8051 L54 /eria( 0ommunication contro( in 8051 nterru!t structure of 8051 "emor& and 24 interfacing of 8051 %imer20ounter modes /eria( 0ommunication,"u(ti!rocessor 0ommunication

%2 %2

)0 ))

BB BB BB

L55

nterru!ts, nterru!t Priorities

%2

$$

BB

L5$ "emor& Addressing %2 #2 BB %2 215 L5) "emor& and 24 interfacing of 8051 ,*terna( 24 nterfacing BB "E." B//+S %1. Advanced micro!rocessor and Peri!hera(s 6 A.@.Ra& and @.".Bhurchandi, %"7, 2000 %2. "icro 0ontro((ers < +eshmuBh, %ata "c1raw 7i(( ,dition. ,E)E,ENCES R1. "icro Processors 5 nterfacing < +oug(as =. 7a((, 200). R2. %he 8088 and 808$ "icro Processors < P7 , 4th ,dition, 200#. R#. "icro 0om!uter /&stem 808$28088 'ami(& Architecture, Programming and +esign 6 B& Liu and 1A 1i-son, P7 , 2nd ,d. R4. 8085, 808$ "icro!rocessors and 8051 "icrocontro((ers 7ardware, A!!(ications and nterfacing 6 R.Latha, /. /aBthive( 8 :ote>? P? indicates Page :um-er9