Submicron Project, SoC 2005

3-BIT COMPARATOR DESIGN

Ding Chengwei 820116-A190 chengwei@kth.se Niu Yuechao yuechao@kth.se
Abstract-The objective of this project is to build a 3-bit comparator, which compares two numbers each represented in 3 bits. The circuit produces 2 bits out: Q1 is active when A>B, Q1 is not active when A<B or A=B. Q2 is active when A=B, otherwise not active. Our approach is first to build up 1-bit comparator as one component and then connect three such kind of 1-bit comparator together. By applying the knowledge of CMOS and analyzing the logic behavior of the function, we can get the design with CMOS technology and run the simulation to check if it is correct.

I.

INTRODUCTION

omparing two binary words for equality is a commonly used operation in computer systems and device interfaces. A circuit that compares two binary words and indicates whether they are equal is called a comparator. Here we need to design such kind of a comparator which compares the value of two 3-bit numbers and gives the output Q1 to 1 when the first number A is larger than the second number B, output Q2 to 1 when the two numbers are equal. Our method is to extend the 1-bit comparator to a 3-bit comparator by combine the logic relation between the 1-bit comparator outputs. Here we use Microwind to draw the layout of the CMOS circuit. Then we extract the spice file in Microwind and run under PSPICE to get the simulation result to verify if it works. This paper describe how to and the process of doing basic CMOS circuit design by applying the knowledge of K-Map optimization, CMOS circuit structure.

II.

1-BIT COMPARATOR

F S

Irst of all we need to design an 1 bit comparator. We can easily make such a component, 2 bits for input A and B, and 2 bits for output Q1 and Q2. Q1 is one when A is larger than B which means only when A is one and B is zero will set Q1 to one. And for the Q2, only when A and B both become one and zero will it be set. Here we can define Q1 as Q1 = A B , Q2 as

Q2 = A B + A B

Econd we draw the Karnaugh-map of 1-bit comparator and find the relationship between the input and the output.

Q1 = A B (when A>B)

Q2 = A B + A B (when A=B)

Submicron Project, SoC 2005

hen we can get the circuit structure and here is the logic diagram for the one bit comparator which is composed of two inverters, three two-input AND gates and one two-input or gate.

This is the one bit comparators layout in Microwind.

The simulation result of 1-bit comparator in PSPICE

Submicron Project, SoC 2005

He three bit comparator is easy to be implemented by combine three one-bit comparator together. Here is the structure of the circuit in our design. We use three one-bit comparator components, one two-input AND gate, two three-input AND gate and one three-input OR gate.

III.

3-BIT COMPARATOR

Hat we have done is to use one AND gate to combine all the 1-bit comparators Q2 together. It could be easily understood only when all the bits of the three bit numbers are equal means that this two numbers have the same value. For the Q1 output, lets consider there are two three-bit numbers, A3 A2 A1 and B3 B2 B1 . There are three cases represent A is larger than B. First, A3 is larger than B3 . Second, A3 equals B3 , but A2 is larger than B2 . The last one is when

A3 equals B3 and A2 equals B2 , but A1 is larger than B1 . Anyone of these three relations has been
satisfied will set Q1 to one, so we use an OR gate here. The layout of this circuit in Microwind is given like this.

Submicron Project, SoC 2005

The simulation result in PSPICE verified this design and we put in here.

Propagation delay for Q2 (A=B) from Microwind (step=1ps) A3 A2 A1 B3 B2 B1 Average 256ps 225ps 205ps 1176ps 260ps 500ps 176ps 167ps 164ps 225ps 480ps 360ps 216.67ps 225ps 200ps 1201ps 177ps 100ps 180ps

Propagation delay for Q1 (A>B) from Microwind (step=1ps) A3 A2 A1 B3 B2 B1 Average 116ps 154ps 162ps 150ps 170ps 290ps 150ps 170ps 159ps 154ps 157ps 1160ps 169.0ps 154ps 1106ps 1076ps 150ps 149ps 250ps

The propagation delay of this circuit is about 216.67ps for Q2 (A=B) and 169.0ps for Q1 (A>B).

Submicron Project, SoC 2005

IV. Conclusion His paper has described how the COMS circuit can be used to construct the comparator by using the logic relation between different input and output nodes. We can use Karnaugh maps to minimize the representation of the functions. After that, we can use the logic units which composed with CMOS transistors to help us constructing the circuit. The PSPICE simulation results show our design has satisfied all the requirements. And also the propagation delay of this design is also within the consideration. By adding more 1-bit components into the circuit, we can easily make a larger size comparator. Of course, comparing with parallel inputs in our design, one way to save input pins is to do it in serious input with only two inputs which is beyond the scope of this paper.

Reference
[1] [2] [3] P. E. Allen , D.R. Holberg , CMOS ANALOG Circuit Design (Second Edition), chapter6,8 , Oxford Univ Pr,2002 William J. Dally and John W. Poulton: Digital Systems Engineering, Cambridge University Press 1998, pp519-521, 1998. John F. Wakerly, Digital Design Principles and Practices(Second Edition), Chapter3,4,7