Layout Techniques For Symmetry and Matching

Layout
Techniques
Symmetry and Matching
E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005
1
Matching
Matching: When engineering circuits, you want partnered
devices to react exactly the same way, this is called matching.
All of the devices in an integrated circuit occupy the same piece of
silicon, so they all experience the similar manufacturing conditions.
If one components value increases by 10%, then all similar devices
experience similar increases. Devices specifically constructed to
obtain a known constant ratio are called matched devices.
The ration between two similar components on the same
integrated circuit can be controlled to better than +/- 1%.
Analog Integrate Circuits usually depend on matching to obtain
much of their precision and performance.
Digital Integrated Circuits depend on matching to obtain compactness.
2
Mismatch
Mismatch: a deviation of the measured device ratio from the
intended device ratio is called mismatch.
1
) / (
) / ( ) / (
1 2
2 1
1 2
1 2 1 2
=
=
x X
x X
X X
X X x x
Mismatch for a specific pair

of devices.
X
1
and X
2
are the intended values,
x
1
and x
2
are the measured values.
The same measurements performed on a second pair of devices will
yield a different mismatch . Measurements of a large number of
device pairs will produce a random distribution
1
,
2
,
3
, ..
Standard
deviation of
mismatch
=
N
i
i
m
N N
s
1
2
) (
1
1 1

=
=
N
i
i
N
m
1
1
The average
mismatch
3
Examples of mismatch in passive devices
4
Examples:
Consider the case of two matched Poly resistors having widths of 2um
and 4um respectively. Suppose that Poly etching introduces a process
variations of 0.1um. Then the resulting mismatch is: {[(2 + 0.1)/(4 + 0.1)
0.5 ]/0.5}= 2.4%.
Consider a couple of matched resistors one having 20um long and the
other 40um long. Suppose that contacts of resistors have a process
variations of 0.2um. This introduces a mismatch of about {[(20.2)/(40.2)
0.5]/0.5}= 0.5%
Suppose a pair of poly-poly capacitors, one measuring 10x10um and
the other 10x20um, both experience a poly etch variation of 0.1um, then
the systematic mismatch is {[(102.1/203.1) 0.5]/0.5}= 0.6%.
Causes of Mismatch
Random mismatches stem from
microscopic fluctuations in
dimensions, dopings, oxide
thickness, etch rate,
photolithography, and other
parameters that influence
component values.
5
Approaches to reduce Mismatch
Random statistical fluctuations in deposited layers
Aspect of deposited
Poly layer
Peripheral
fluctuations
areal
fluctuations
Designed mask of
Poly layer
For capacitors, the contribution of peripheral fluctuations term
decreases as the capacitance increases and the areal
fluctuations term dominates.
For resistors, the effect of process variations can be sharply
reduced by making both two resistors the same width.
6
Etch rate variations
Faster
etch
rate
Slower
etch
rate
Larger openings grant more access
to the etchant and thus clear more
quickly than small openings.
Consequently, sidewall erosion
occurs to a greater degree around
the edges of a large opening than
around the edges of a small one.
Effect of etch rate variations on matched resistors
Drawn
size
(outline)
Final
size
(shaded)
Dummy
or etch
guards
7
Matched resistors array
employing connected
dummies for reducing
etch rate variations
Matched capacitors array
employing grounded dummies
real
capacitors
Dummy
capacitor
Poly1 plate
contacts
Dummy resistor
Dummy resistor
Matched resistor
Matched resistor
Matched resistor
8
Effect of diffusion interactions
The resistors occupying the ends
of the array will have slightly
different values of diffusion
interactions than the resistors
occupying the middle of the array.
End array resistor
Middle array resistor
End array resistor
Matched array of
diffused resistors
including grounded
dummies for
reducing diffusion
interactions
Matched resistor
Matched resistor
Dummy resistor
Dummy resistor
Tank
NBL
Tank
contact
9
The same width for matching resistors
As an example, if you want four resistors to match each
other, then do not select one of those resistors as 5um
wide, another 10um wide, another 2um wide and a fourth
one as 20um wide. They all need to match each other , so
choose one universal width that is sensible and have all
the same width. Vary only the lengths.
10
Improved serpentine
resistor layout
Poor serpentine
resistor layout
11
Mismatch in CMOS transistors
Device orientation
M1
M1
M2
M2
Bad matched transistors,
transistors have different kp
Good matched transistors
variations in kp are cancelled
Effect of photolithographic misalignment when device is mirrored
12
M2 is a
mirror of M1
M1
M2
M1
L1 >>, L2 <<
L1 >>, L2 >>
Deep diffusions can affect the matching of nearby
MOS transistors. The tails of these diffusions extend a
considerable distance beyond their junctions and the
excess dopants they introduce can shift Vth and alter
the transconductance of nearby transistors
PMOS
NMOS
13
Poly etch rate variations
M1 M2 M3
Dummy
gate
Gate array for reducing Poly etch rate variations
M1 M2 M3
Interdigited transistor
14
NMOS transistors usually match more precisely
than PMOS transistors.
Several authors have reported that PMOS
transistors exhibit 30 to 50% more
transconductance mismatch than comparable
NMOS transistors
(Ref. Lakshmikumar et al., Characterization and Modeling of Mismatch
in MOS Transistors for precision Analog Design, pp 1060.)
15
16
Compact layout
Easy to tile
Difficult to tile
Matched devices
should reside as
close as possible
to minimize the
influence of stress
between them.
Symmetry
Circuit A
Circuit B
Circuit C
Circuit A
Circuit B Circuit C
Line of
symmetry
Imaginary line of symmetry
helps components match
Rearranging placement
of circuits
Poor matching
Keep everything in symmetry,
particularly in high frequency, if you
want to match parasitics, you have
to layout blocks across a line of
symmetry.
17
Common-centroid
Axis of symmetry
Centroid
Location the centroid
Centroid
Axis of symmetry
Placing devices around a common central
point is known as common-centroid.
18
Common-centroid Layout
Axis of
symmetry
Axis of symmetry
of device A
Axis of symmetry
of device B
Common axis of
symmetry
19
A A B B
A A B B A A B
One-dimension interdigitatated arrays
Examples of common-centroid in interdigitated arrays
Cross coupled pair
A
B
B
A
A
B
B
A
B
A
A
B
Two-dimension interdigitated patterns
or cross-coupled pair patterns
These arrays are adequate to lay out capacitors, diodes, and
transistors
20
Construction of Interdigitated Arrays
Procedure:
1.- Identify all the components comprising the array.
2.- Divide components in segments and see if all the
values have a greatest common factor.
3.- In case where a large common factor does not
exist, try using the value of the smallest device as
the value of a segment, then determine the number
of segments in the other devices.
4.- Once the segment has been found make sure
that it is not so small that it precludes reasonable
matching (no less than 5um wide for resistors and
100um2 for capacitors).
5.- Finally, choose the best interdigitation pattern.
21
Common-centroid in MOS transistors
Example of Interdigitated MOS transistor
A B B A
D S
Gate
S D D
22
Common-centroid in MOS transistors
A
A
B
B
D
D S
G
Example of cross-coupled MOS transistor
23
24
Rules for device matching
Construct matched resistors from a single material
Make matched resistors the same width
Make matched resistors sufficiently wide (minimum width ~ 5um)
Where practical, use identical geometries for resistors
Orient matched resistors in the same direction
Place matched resistors in close proximity
Interdigite arrayed resistors
Place dummies on either end of a resistors array
MATCHED RESISTORS
Segmented resistors are superior to serpentines
25
MATCHED RESISTORS (CONT.)
Use Poly resistors in preference to diffused ones
Place deposited resistors over field oxide
If leads cross resistors, they should cross all resistor segments in
the same manner
Place matched resistors well away from power devices
Avoid short resistor segments (Poly resistors must have a total
length no less than 50um to minimize nonlinearities)
Avoid excessive power dissipation in matched resistors
26
MATCHED CAPACITORS
Use identical geometries for matched capacitors
Use square geometries for precisely matched capacitors
Make matched capacitors as large as practical
Place matched capacitors adjacent to another
Place matched capacitors over field oxide
Connect the upper electrode of a matched capacitor to the higher-
impedance node
Place dummy capacitors around the outer edge of the array
Cross-couple arrayed capacitors
Consider the capacitance of leads connecting the capacitor
27
MATCHED CAPACITORS (Cont.)
Do not run leads over matched capacitors unless they are
electrostatically shielded
Use thick oxide dielectrics in preference to thin oxide or composite
dielectrics
Place matched capacitors well away from power devices.
28
MATCHED TRANSISTORS
Use identical finger geometries
Use large active areas
For voltage matching, keep V
gs
small
For current matching keep V
gs
large
Orient transistors in the same direction
Place transistors in close proximity
Keep the layout of the matched transistors as compact as possible
Where practical use common-centroid layouts
Place dummy segments on the ends of arrayed transistors
29
MATCHED TRANSISTORS (Cont.)
Place transistors well away from power devices
Do not place contacts on top of active gate area
Do not route metal across the active gate region
Keep all junctions of deep diffusions far away from active gate area
Connect gate fingers using metal straps
Use thin oxide devices in preference to thick oxide devices
Consider using NMOS transistors rather than PMOS transistors

Layout Techniques For Symmetry and Matching

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