Low-Power and Area-Efficient Carry Select Adder

AIM: The main aim of the project is to design and implement Low-Power and Area-Efficient Carry Select Adder. ABSTRACT: Carry Select Adder (CSLA) is one of the fastest adders use in many dataprocessing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and po er consumption in the CSLA. This or! uses a simple and efficient gate-le"el modification to significantly reduce the area and po er of the CSLA. #ased on this modification $-, %&-, '(-, and &)-* s+uare-root, CSLA (S-.T CSLA) architecture ha"e *een de"eloped and compared S-.T CSLA ith the regular S-.T CSLA architecture. ith the regular or! e"aluates the The proposed design has reduced area and po er as compared ith only a slight increase in the delay. This

performance of the proposed designs in terms of delay, area, po er, and their products *y hand ith logical effort and through custom design and layout in /.%$m C01S process technology. The results analysis sho s that the proposed CSLA structure is *etter than the regular S-.T CSLA. Propo ed !et"od 2n this paper e can increase the *it si3e. hile implementing the adder e need

4or gate . actually it re+uires %) transistor5s to implement . e can implement this

V.Mallikarjuna (Project manager)

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4or gate

ith ' transistors . in this

ay

e reduce the area, delay, po er

consumption

BL#C$ %IA&RAM:

Fig6 .egular %&-* S-.T CSLA.

T##LS: hspice_vA- !!".!#$ t-spice APPLICATI#' A%(A'TA&ES: This project is used to reduce the area and po er of S-.T CSLA architecture. The reduced num*er of gates of this or! offers the great ad"antage in the

reduction of area and also the total po er.

V.Mallikarjuna (Project manager)

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 The po er-delay product and also the area-delay product of the proposed design sho a decrease for %&-, '(-, and &)-* si3es hich indicates the success of the method and not a mere tradeoff of delay for po er and area.

RE)ERE'CES: 1. 7. #edrij, 8Carry-select adder,9 IRE Trans. Electron. Comput., pp. ')/: ')). #. .am!umar, ;.0. <ittur, and =. 0. <annan, 8AS2C implementation of modified faster carry sa"e adder,9 Eur. J. Sci. Res., "ol. )(, no. %, pp. >':>$. T. ?. Ceiang and 0. 7. ;siao, 8Carry-select adder using single ripple carry adder,9 Electron. Lett., "ol. '), no. ((, pp. (%/%:(%/'. ?. <im and L.-S. <im, 8&)-*it carry-select adder Electron. Lett., "ol. '@, no. %/, pp. &%):&%>. 7. 0. .a*aey, Digtal Integrated CircuitsA Design Perspective . Apper Saddle .i"er, B76 =rentice-;all. ith reduced area,9

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &