Multi operand Redundant Adders on FPGAs

AIM: The main aim of the project is to design and develop Multi operand Redundant Adders on FPGAs. ABSTRACT: Although redundant addition is widely used to design parallel multioperand adders for ASIC implementations, the use of redundant adders on Field Programmable ate Arrays !FP As" has generally been avoided# The main reasons are the efficient implementation of carry propagate adders !CPAs" on these devices !due to their speciali$ed carry%chain resources" as well as the area overhead of the redundant adders when they are implemented on FP As# This paper presents different approaches to the efficient implementation of generic carry%save compressor trees on FP As# They present a fast critical path, independent of bit width, with practically no area overhead compared to CPA trees# Along with the classic carry%save compressor tree, we present a novel linear array structure, which efficiently uses the fast carry%chain resources# This approach is defined in a parameteri$able &'( code based on CPAs, which ma)es it compatible with any FP A family or vendor# A detailed study is provided for a wide range of bit widths and large number of operands# Compared to binary and ternary CPA trees, speedups of up to *#*+ and *#,- are achieved for ,.%bit width and up to /#0, and /#,, for .-%bit width#

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

BLOCK IAGRAM:

Fig1 Transformation of a 2%bit width 31* linear array compressor tree into a CPA array#

Tools: 4ilin5 +#*i IS6, 7odelsim .#-c# Appli!ation Ad"anta#es: 6fficiently implementing CS compressor trees on FP A, in terms of area and speed, is made possible by using the speciali$ed carry%chains of these devices in a novel way# The proposed high%level definition of CSA arrays based on CPAs facilitates ease%of%use and portability, even in relation to future FP A architectures, because CPAs will probably remain a )ey element in the ne5t generations of FP A# Re$eren!es:

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

 8# Cope, P# Cheung, 9# (u), and (# &owes, :Performance Comparison of raphics Processors to ;econfigurable (ogic1 A Case Study,< I666 Trans# Computers, vol# 3+, no# -, pp# -//%--0# S# 'i)mese, A# =ava), =# =ucu), S# Sahin, A# Tangel, and &# 'incer, :'igital Signal Processor against Field Programmable ate Array Implementations of Space%Code Correlator 8eamformer for Smart Antennas,< I6T 7icrowaves, Antennas Propagation, vol# -, no# 3, pp# 3+/% 3++# S# ;oy and P# 8anerjee, :An Algorithm for Trading off >uanti$ation 6rror with &ardware ;esources for 7AT(A8%based FP A 'esign,< I666 Trans# Computers, vol# 3-, no# ?, pp# 00.%0+.# F# Schneider, A# Agarwal, @#7# @oo, T# Fu)uo)a, and @# =im, :A Fully Programmable Computing Architecture for 7edical Altrasound 7achines,< I666 Trans# Information Technology in 8iomedicine, vol# ,-, no# *, pp# 3/0%3-B# C# &ill, :The Soft%Core 'iscrete%Time Signal Processor Peripheral DApplications CornerE,< I666 Signal Processing 7aga$ine, vol# *., no# *, pp# ,,*%,,3#

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &