Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications

AIM The main aim of the project is to design !Efficient Majority Logic Fault Detection "ith Difference-Set Codes for Memory Applications#$ A%S&'AC& Nowadays, single event upsets (SEUs) altering digital circuits are becoming a bigger concern for memory applications This paper presents an error!detection method for difference!set cyclic codes with majority logic decoding "ajority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors #owever, they re$uire a large decoding time that impacts memory performance The proposed fault!detection method significantly reduces memory access time when there is no error in the data read The techni$ue uses the majority logic decoder itself to detect failures, which ma%es the area overhead minimal and %eeps the e&tra power consumption low

K.Aravind Reddy (Director) 9652926926, 9640648

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'ig( Schematic of an ") decoder *) cyclic shift register **) +,- matri& ***) "ajority gate *.)+,- for correction

&((LS +ilin& *SE / 0 * and "odelSim 1 2c

A++LICA&I(, AD-A,&A*ES The proposed techni$ue is able to detect any pattern of up to five bit!flips in the first three cycles of the decoding process This improves the performance of the design with respect to the traditional ")3 approach The ")33 error detector module has been designed in a way that is independent of the code si4e This ma%es its area overhead $uite reduced
K.Aravind Reddy (Director) 9652926926, 9640648 Cell No:

compared with other traditional approaches such as the syndrome calculation (S'3) 5 theoretical proof of the proposed ")33 scheme for the case of double errors has also been presented 'EFE'E,CES 6 7 Slayman, 86ache and memory error detection, correction, and reduction techni$ues for terrestrial servers and wor%stations,9 *EEE Trans 3evice "ater -eliabil , vol :, no ;, pp ;/<=2>2 - 6 ?aumann, 8-adiation!induced soft errors in advanced semiconductor technologies,9*EEE Trans 3evice "ater -eliabil , vol :, no ;, pp ;>@= ;@1 A von Neumann, 8Brobabilistic logics and synthesis of reliable organisms from unreliable components,95utomata Studies, pp 2;=/C " 5 ?ajuraet al , 8"odels and algorithmic limits for an E66!based approach to hardening sub!@>>!nm S-5"s,9*EEE Trans Nucl Sci , vol :2, no 2, pp /;:=/2: - Naseer and A 3raper, 83E6 E66 design to improve memory reliability in sub!@>> nm technologies,9 inBroc *EEE *6E6S, 0>>C, pp :C1=:C/

K.Aravind Reddy (Director) 9652926926, 9640648

Cell No: