CMOS Devices Process Integration

Navakanta Bhat
Professor
Centre for Nano Science and Engineering (CeNSE) Dept. of Electrical Communication Engineering, Indian Institute of Science, Bangalore
Navakanta Bhat

Outline
CMOS Technology and Design Objectives Isolation Wells Gate Stack Junctions Interconnects
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The Integrated Circuit Food Chain

System Architecture Digital Architecture

Application Domain

Circuit Design Computational State Variable Device Physics

Boolean Logic Charge CMOS Silicon

Technology Domain
Process Technology

CAD and Modeling Optimization across all the domains is necessary

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What is in a IC Chip ?
A large ensemble of transistors connected appropriately through multilevel metal interconnection lines

INTEL Every thing should be made as simple as possible, but no simpler! Albert Einstein

IBM

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CMOS : NMOS + PMOS

Drain Gate Source

schematic cross section

n G oxide n

lay out
G oxide

switch model ID
p

p-well

n-well

Silicon

Silicon

NMOSFET CMOS

PMOSFET

Vth

Vth V G CMOS

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Performance Metrics in CMOS

INVERTER Vdd Ids IN Ids OUT CL Gate Capacitance Junction Capacitance Interconnect Capacitance

CAPACITANCE IS INERTIA

D= CL*Vdd /Ids

P=CL*Vdd2*f

CL , total capacitance at the switching node Vdd , supply voltage f , switching frequency Ids , charging or discharging current
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Vt-Vdd design plane

Normalized delay

Delay Vt Pac Psb

0.4 Vt/Vdd

Vdd

Delay increases significantly for Vt/Vdd > 0.4 Pactive (Pac) = CVdd2f Pstandby (Psb) = WVddIoff Delay and Power are the only trade-off points for digital design
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Transistor Design Metrics

Ioff

DC Metric
C BETTER DESIGN

AC Metric
BETTER DESIGN

Ion

Ion
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Transistor design methodology for Digital CMOS

Circuit characteristics: Delay (Vt/Vdd) Active power (Vdd) Standby power (Vt)

Hot carrier reliability Vdd, L, N

System compatibility Vdd

Gate oxide reliability Vdd, Tox

Design parameters: L, Vdd, Tox, N, Xj S/D engineering Channel engineering Choice of materials and processes
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Constant Electric Field Scaling

Technology scaling Scaling factor K > 1 Primary scaling factors: Tox, L, W, Xj (all linear dimensions) Na, Nd (doping concentration) Vdd (supply voltage) Derived scaling behavior of transistor: Electric field Ids Capacitance Derived scaling behavior of circuit: Delay (CV/I) Power (VI) Power-delay product Circuit density ( 1/A)

1/K K 1/K 1 1/K 1/K 1/K 1/K2 1/K3 K2

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Technology Life cycle

Source : ITRS 2007

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Worldwide Wafer Production across Technologies

Source : ITRS 2007

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Microelectronics to Nanoelectronics
Gate tunneling Channel quantization Quasi ballistic transport

SCALiNG

Silicon CMOS
1960

New Materials and Device structures

2010 45nm 2020 15nm

Nano-scale building blocks and Giga-scale Integration!

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ITRS Projections
2007 Year of Production Technology Node (nm) Printed Gate Length (nm) Physical Gate Length (nm) Wafer diameter (inch) Number of masks required for fabrication of Microprocessor Number of Transistors in Microprocessor (billion) Number of interconnect wiring levels in the Microprocessor Number pins for packaged Microprocessor chip Operating voltage (V) Microprocessor frequency, GHz Chip power dissipation (Watts) 65 42 25 12 33 1.1 15 1088 1.1 9.3 189 45 30 18 12 35 2.2 16 1450 1.0 15.1 198 32 21 13 18 37 4.4 17 1930 0.9 23 198 22 15 9 18 37 8.8 17 2568 0.8 39.7 198 16 11 6.3 18 39 17.7 18 3418 0.7 62.4 198 11 7.5 4.5 18 39 17.7 18 3760 0.7 73.1 198 2010 2013 2016 2019 2022

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ISOLATION MODULE
SiO2 is used isolate two transistors LOCal Oxidation of Silicon (LOCOS) Shallow Trench Isolation

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LOCOS Isolation
~10nm Pad SiO2 Dry oxide ~15nm Si3N4 LPCVD Active Litho, Dry etch

Si

Si

Si
Scalability is an issue due to Birds beak

~500nm Field SiO2 Wet oxide

Strip nitride, oxide Wet etch

Si

Si Comment on Wafer Type

Si
Not suitable for < 250nm
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Shallow Trench Isolation

~10nm Pad SiO2 Dry oxide ~15nm Si3N4 LPCVD

Active Litho, Dry etch ~350nm depth

Si Liner oxide (~10nm) HDPECVD trench fill TEOS chemistry

Si

Si

Chemical Mechanical Polishing, HF dip, Nitride strip

Si

Si
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Well Module
What are the requirements for Nano MOSFET Design ?

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Nano MOSFET : Design Issues

G S D S G D

Leakage current Vt Vt roll-off

SHORT CHANNEL EFFECTS

~1m L (m) Drain Induced Barrier Lowering (DIBL)

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How do you minimize SCE?

Screen the electric field Increase Substrate Doping Concentration Increased impurity scattering Degradation of sub-threshold slope Increased junction capacitance Minimize coupling volume Decrease source/drain depth Increased source/drain resistance Junction spiking

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Transistor Structure Requirement

Na

spacer n+ source p-well X

gate
oxide

Pocket halo Y drain

Na

n+

L Y

Deep S/D and Shallow Extension

Super steep retrograde channel

Short channel effects are controlled by shallow extensions, pocket halos and super steep retrograde channel
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Other Requirements
Adjust Vt Prevent Deep Punch Through

Si Account for high fields at trench corner USE CHAIN OF IMPLANTS

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Well Implant Chain

P-Well
Boron ~ 200 KeV, 1012 1013 /cm2 Boron ~100 KeV, 1012 1013 /cm2 Boron ~50 KeV, 1012 1013 /cm2 Boron ~ 15 KeV, 1012 1013 /cm2 Indium ~ 120 KeV, 1012 1013 /cm2

N-Well
Phosphorus ~ 600 KeV, 1012 1013 /cm2 Phosphorus ~300 KeV, 1012 1013 /cm2 Phosphorus ~ 50 KeV, 1012 1013 /cm2 Phosphorus ~ 15 KeV, 1012 1013 /cm2 Antimony ~ 150 KeV, 1012 1013 /cm2

Multiple Vt Technology
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Gate Stack Module

SiO2, Dual Polysilicon Gate High-K, Metal Gate

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Polysilicon Gate stack

RCA Clean Dry, 800C, O2+N2 Nitridation i-PolySilicon LPCVD

Si

Si

Si

Phase Shift Litho Resist Trim

Poly Etch

NBTI Reappears! Si Si Comment on Dual Gate technology

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Why High-K and Metal Gate

Direct Tunneling current

Increasing gate resistance for short channel device Activation of poly-Si

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High-K Metal Gate Gate stack

DISPOSABLE GATE PROCESS i-PolySilicon PVD HfO2 LPCVD RCA Clean

Si

Si

Si

Phase Shift Litho Resist Trim

Poly Etch

Dispose -off polySi after ILD0 and fill the gate trench with dual metal gate materials Ensures Self Aligned transistor
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Si

Si

Junction Module

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NMOS Halo and Extension

NMOS S/D Litho Boron, 45o tilt, ~1012, 15KeV

Si Arsenic, 0o tilt, ~1014, 5KeV

Si

Si

STORY #1: Shadow

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PMOS Halo and Extension

PMOS S/D Litho Phosphorus, 45o tilt, ~1012, 35KeV

Si BF2, 0o tilt, ~1014, 3 KeV

Si

STORY #2 Si
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Spacer Formation
Deposit 10nm Oxide, 40nm nitride

Si

Anisotropic nitride etch

STORY #2: Cgd

Si

What about Oxide spacers ?? Boron segregation degrades PMOS Comment on offset spacers for extension
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Deep S/D Implant and Anneal

NMOS S/D Litho Arsenic, 15 KeV, ~1015 PMOS S/D Litho Boron, 5 KeV, ~1015

Si RTA

Si

Si

Trade off between poly depletion, versus Junction depth & Boron Penetration

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Silicide Formation
G S D

Parasitic Channel Resistance PVD Metal RTA ETCH METAL

Si
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Interconnect Module

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ILD0 , Contact and Metal1

ILD0 CVD Contact Litho & Etch W CVD and CMP Aluminum PVD Metal Litho & Etch Forming gas anneal STORY #3: Yield

Si Same process continues for Via1, Metal2, Via2, Metal3

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Interconnect delay in Nano CMOS

Intrinsic gate delay

Delay

Interconnect delay

0.18

0.25

0.35

0.5

Technology node (m)

Gate delay decreases due to decrease in gate capacitance Interconnect delay increases due to decreasing metal line width and increasing intra-metal coupling capacitance Interconnects are no longer afterthought in Nano CMOS
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Copper Interconnects
Dual Damascene Process ILD CVD (thickness for via and metal) Litho Via holes and etch via hole Litho Metal trenches and etch metal trench Copper Electroplating and CMP

Si
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Beyond Bulk Silicon CMOS

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SOI CMOS ?
SOI Si film (10-100nm) Insulator
500m

Bulk

Si wafer

Si wafer

Devices are built on thin Si film (~100nm) on insulator Handle Si wafer may be underneath the insulator (VLSI) Insulator itself may form the rest of the substrate (Displays) Partially Depleted SOI (PDSOI) versus Fully Depleted SOI (FDSOI)
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Components of node capacitance

CL=Cg + Cj + Ci Cg = gate oxide capacitance Cj = junction capacitance Ci = interconnect capacitance

s , permittivity of Si
A , cross section area Wd , depletion width
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Cj= sA/Wd

Other SOI specific effects

Drain current overshoot Lower body effect Better sub-threshold slope Fewer processing steps Better isolation resulting in dense circuits Absence of latch-up problem Threshold voltage (Vt) instability due to DC floating body effect

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SOI device delay

IBM data

IBM data

SOI results in at least 30% lower delay compared to bulk The improvement is more pronounced at lower voltages SOI results in about 70% lower power for the same speed
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SOI Power dissipation

IBM data SOI results in about 70% lower power for the same speed
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Need for Multigate FETs

SiO2

n+

n+

Increase in P type doping with decreasing L results in n+-p+ tunnel junction

Intels data

Alternate structures required for better gate control over the channe - Double Gate, FinFET, Surround Gate
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Fin FET

H.S.P Wong, IBM Technical Journal

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CMOS with new materials ?

Germanium / GaAs / GaN ? Graphene ?

Planar Technologies are Circuit designer friendly as opposed CNT and other vertical transistors
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Germanium Schottky Barrier MOSFETs

*
Spacer Gate
oxide

R Doped S/D

Silicid e
scd

R
dp

R
ext

ov

Metal

Advantages Reduced series resistance Reduced short channel effects Low thermal budget process Easy for Metal gate Reduced process variability *
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S-D Kim et al., Advanced Model and analysis of series resistance for CMOS scaling , IEEE TED, Vol. 49, No. 3, March

What about NMOS Schottky Junction Transistors on Ge (or Si)

Technologically hard problem Fermi level pinning in the bottom half of the band gap
For Si : Eg/3 above valence band edge For Ge : Close to valance band edge

Ec Ei Ev

Schottky junctions on n-type Ge/Si are possible Schottky junctions on p-type Ge/Si have never been very efficient
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Is it possible to passivate the interface and De-pin the Fermi level?

Literature on Sulphur passivation of III-V semiconductors exists

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Current State-of-the-art
Sulphur implantation: results in ohmic contacts to both substrate types. Not possible to produce Schottky Source/Drain. Passivation studies for Ge High-k interface done only for p-channel devices. N-channel devices have proved very difficult to passivate. No studies exist on the effect of passivation on Schottky Interface.
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Sulphur Passivation of Ge surface

Ge cleaned in HCl-HBr mixture to remove native oxide. Subsequently treated in Aqueous Ammonium Sulphide ((NH4)2S ) solution Passivation treatment carried out close to boiling point.
Al, Zr, Ta (Low work function) W, Ni, Pt (High work function)
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XPS studies
Intensity (Arbitrary Units)

S-pass. Ge 3d 5/2 HCl-HBr Bare Ge

25

Intensity (Arbitrary Units)

S 2p

GeO2

30 35 Binding Energy (eV)

160 165 170 Binding Energy (eV)

Intensity (Arbitrary Units)

Native oxide peak disappears after cleaning and sulphur passivation

Ge 2p3/2 Ge-S

Sulphur peak is evident on Sulphur treated Wafers Ge-S peak also apperas indicating that sulphur Is chemically active on the surface 1230
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1210

1215 1220 1225 Binding Energy (eV)

Schottky contact on p-Ge

Modification of behavior on p-Ge
60 40 Al pass. Zr pass. Zr Un-pass. Al Un-pass.

J (A/cm )

20 0 -20 -40 -60 -1

EC
Eg

EV

-0.5

Voltage(V)

0.5

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Schottky contact on n-Ge

Modification of behavior on n-Ge
60 40 Al Un-pass. Zr Un-pass. Al pass. Zr pass.

J (A/cm )

20 0 -20 -40 -60 -1

-0.5

Voltage(V)

0.5

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Barrier height trend after passivation

Electron Barrier (Bn)
0.66 0.6 0.5 0.4 0.3 0.2Al 0.1 0
Zr Zr Ta Ta W Ni Pt Al

Ideal Theory
Un - passivated. S - passivated 4.5

4.05

mvac

5.5

Sulphur passivation results in almost ideal Schottky behaviour

Arun & Bhat APL, 2010

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Summary
CMOS Process Integration Isolation module Well module Gate stack module Junction module Interconnect module CMOS Process Complexity continues to increase with technology scaling

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Thank You

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