Lecture 8

iD vs. vDS
The current in the triode region is: The current in the saturation region is theoretically constant, equal to the value of the current at the upper edge of the Triode region: In the semiconductor fabrication process, the combination of the surface mobility and oxide capacitance is know as the process transconductance parameter. We can also see that the current through a device is dependent on the aspect ratio of the width to the channel length.
The values of W and L can be selected by the circuit designer. However every fabrication process has a limit on how small L can be. This measure is used to describe the fab. process, say 0.09m technology (currently used)
W iD = ( nCox ) L 1 2 (vGS Vt )vDS vDS 2

iD =

1 W 2 ( nCox ) (vGS Vt ) 2 L

= nCox kn
W iD = k n L 1 2 (vGS Vt )vDS vDS 2

iD =

1 W (vGS Vt )2 kn 2 L

Small = fast
The gate oxide thickness also scales with the channel length. Currently oxides are 2nm thick! Why do we care about short channels?
If we want a faster transistor, it needs to handle more current. The way to think about that is the speed of a transistor is fundamentally limited to how long it takes an electron to cross the channel. Faster crossing times means higher speed, or shorter distances. If we try for higher speed, then that means higher current (i=q X velocity)

So both ways of looking at it demand a shorter channel if we want our computers to keep getting faster

Example
Consider a MOSFET with W/L=8m/0.8 m, tox=8 nm, n=450 cm2/Vs, and Vt=0.7V. What values of VGS and VDSmin are needed to operate in saturation with a DC current ID=100A? First we need to find Cox and kn: Using the equation for the drain current in saturation: Solve for vGS: We can then find the minimum VDS to ensure the MOSFET is in saturation:
Cox =

ox
tox

3.45 10 11 = 8 10 9

= 4.32f F/m 2
= nCox kn

= 450 cm 2 / V s 4.32 f F/m 2

= 194 A/V 2
iD = 1 W (vGS Vt )2 kn 2 L

vGS = Vt +

2iD L W kn

vGS = 1.02V
VDS min = VGS Vt

Clouds on the Horizon

The MOSFET has been the poster child for Moores Law since practically the beginning. As the channel length shrinks, the number of components that can be fit onto a chip increases. But as we can see, there is a fundamental limit:
Our gate oxides are already just 2 nm thick (this is only about 20 atoms!) As we go smaller, we need to make this thinner. But if we go thinner, the gate oxide will leak due to quantum effects. Variations in thickness become a problem too.

But Moores law has been declared dead many times in the past 20 years and we keep on plugging away. What next then? Replace the oxide with a low-k dielectric (allows you to get thicker layers but still keep the gate capacitance as you want it. Other tricks? For processors, add more real estate to the chip. Intel is shifting to Multi-core processors because they wont get their transistors much faster due to size limits. Thus gain speed by doing things in parallel. But thats outside the scope of this course!

This is a Transmission Electron Micrograph of a standard MOSFET channel and gate. The Oxide, highlighted in blue, is only 2 nm thick! This is what is produced commercially today. Note you can see the individual silicon atoms here!

p-Channel and CMOS

We have covered Enhancement mode n-channel MOSFETs so far. As you might imagine, we can also make p-channel MOSFETs just as easily. Why would we want to?
For one thing, they will operate with the opposite polarity of gate bias, which can be useful Second, they can be combined with the n-channel to create a very useful design architecture:

Complimentary MOS circuits use both the n-channel and p-channel MOSFETs in them. You might imagine that there is some usefulness to this because application of a gate voltage will make one conduct and the other not or vice versa. That is handy in logic gates and surprisingly enough also in analog applications. There is a challenge in making them though. You need to create a well of n-type silicon in the ptype substrate in order to get a p-channel. But this is not so hard to do. CMOS is the most utilized technology in device design these days.

MOSFET Symbol
The symbol for the MOSFET shows the four terminals of the device. In many cases it is easier to designate the source and drain figuratively, rather than write S and D next to the terminals.
In that case, an arrow is drawn on the source. The direction of the arrow indicates the normal flow of current through the device and thus the polarity of the device (in this case n-channel) Another way to visualize the direction of the arrow is to consider that the arrow represents the diode formed between the source and channel In practice the source and drain are established according to the polarity of the applied voltages (the drain is always positive relative to the source in an nchannel FET). Otherwise the two are physically interchangeable.

Often the body terminal is connected to the source.

iD-vDS
A schematic representation of the application of a n-channel MOSFET is shown. The iD vs. vDS curve should have the same shape for all applied gate voltages. The only difference being the magnitude of current flowing through the channel. We can see that there are three regions of operation of the MOSFET:
Triode: Used when the MOSFET is to be configured as switch. Saturation: In this region the MOSFET is used as an amplifier. Cutoff: Also used for switch applications

For cutoff operation, we need: To operate in the Triode region:

We need to induce a channel first: vGS < Vt Then maintain a continuous channel

This can be summed up as:

vGS Vt
vGD > Vt

vDS < vGS Vt

iD-vDS (Triode)
W 1 2 In the triode region, the iD-vDS are iD = k n (vGS Vt )vDS vDS 2 L described as: If vDS is sufficiently small, we can W 2 (vGS Vt )vDS i k ignore the vDS term, and obtain a D n L linear equation near the origin: W In this region, the FET is acting like r v = k (V V ) i L a variable resistor with a value of: We can express this resistance in V V V terms of the gate to source W overdrive voltage VOV rDS = 1 k n L The linear approximation that this formula is based on assumes that: vDS << 2VOV
DS D DS v DS small vGS =VGS n GS t

OV

GS

iD-vDS (Saturation)
To operate in the saturation region:
A channel must be established And it must then be pinched off at the drain

vGS Vt
vGD Vt

vDS vGS Vt

The n-channel enhancement MOSFET operates in the saturation region when vGS is greater than Vt and the drain voltage does not fall below the gate voltage by more than Vt volts. The boundary between the Triode and Saturation region is: The drain current provided is independent of the applied voltage and is determined by the gate voltage following a square law relationship. The relationship between the saturation drain current and the drain source voltage at the onset of saturation is:

vDS = vGS Vt

iD =

1 W 2 vDS kn 2 L