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Nov 14, 2013

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Digital Laboratory Department of Electrical Engineering Faculty of Engineering Universitas Indonesia 2013

Table of Contents Module 1: Basic Combinational Logic ........................................... 4 Module 2: Combinational Circuit................................................... 7 Module 3: Arithmetic Functions ..................................................... 11 Module 4: Flip-flop ........................................................................... 19 Module 5: Counter ........................................................................... 26

Compiled, edited and translated by: Prima Dewi Purnamasari M. Anugerah Gunawan Boma Anantasatya Adhi 2013

1| OVERVIEW

Objectives a. Validating Boolean algebra equation with logic circuits. b. Validating K-map as a tool for simplifying complex Boolean algebra equation.

Boolean algebra and Logic Gates In designing a combinational logic circuit, one should understand how to simplify a logic equation. This becomes necessary since logic equation is hardly ever found in its simplest form. Therefore, a method to simplify such equation is required. There are 2 commonly used methods to simplify a logic equation: Boolean algebra and Karnaugh Map (K-map). Basic principles of Boolean algebra: 1. A 0 = 0 2. A 1 = A 3. A A = A 4. A A = 0 5. A + 0 = A 6. A + 1 = 1 7. A + A = A 8. A + A = 1 9. (A) = A 10. A B = B A 11. A + B = B + A 12. (A B) C = A (B C) 13. (A + B) + C = A + (B + C) 14. A (B + C) = (A B) + (A C) 15. A + B C = A + B A + C 16. A + A B = A 17. A + A B = A + B 18. (A + B) = AB 19. (AB) = A + B *explanation about K-map can be found in appendix

3| Procedures

Equipments: a. Boolean Algebra and Logic Gates i. Power Supply PS-445

ii. Advance Logic Trainer LT345 MK2 b. K-Map i. Power Supply PS-445 ii. Advance Logic Trainer LT345 MK2 Experiment Procedure: a. Boolean Algebra and Logic Gates i. Connect 5V line and Gnd line provided by the power supply with logic tutor LT345 Mk2 module. ii. Built several circuits to prove some basic principles of Boolean algebra. iii. Generate a truth table from the result. b. K-Map i. Connect 5V line and Gnd line provided by the power supply with logic tutor LT345 Mk2 module. ii. Built several circuits as noted by lab assistant. iii. Generate a truth table from the experiment result. iv. Simplify the circuit using K-map and validate the result. v. Generate a truth table from the K-map result.

4| Potential Hazards

Risk of electric shock due to high voltage appears on power supply.

Draw the circuit of each experiment! Make an analysis for each experiment! Explain the result of the circuit done in the experiment! Explain the comparison between the process using Kmap and using boolean algebra!

Explain what binary logic is! Explain what logic gate is! Explain the 3 functions of basic logic gate, draw the truth table and the symbols! Explain the function of each primitive logic gate (other tha explained above), draw the truth table and the symbols! Explain the function of each complex logic gate (other tha explained above), draw the truth table and the symbols! What is combinational circuit? Give an example of it! Explain about boolean algebra! What is it used for? Mention the equations! Explain about K-map and give an example of how to use it!

1|

OVERVIEW

a. Objectives a. Understanding principles of Decoder and Encoder. b. Understanding principles of Multiplexer and Demultiplexer.

Decoder and Encoder a. Decoder Decoder is combinational logic circuits which convert binary number from one numeral system to other numeral system, e.g. from Excess-3 to BCD. In general, decoder has n input and m output, which m = 2n. For each arbitrary input (any combination of 0 and 1) always sets only 1 output active (the rests are inactive).

Figure 2.1 General form of a decoder b. Encoder Encoder is the opposite of decoder. It has m input and n output, which m = 2n. Only one bit input is significant and the output is arbitrary. Multiplexer and Demultiplexer a. Multiplexer Multiplexer has n input terminals, m selector (m = 2n) and only one output terminal. This circuit will pass selected input to the output terminal.

Gambar 2.2 Mechanical data selector. To understand basic principle of multiplexer, we can observe a mechanical selector principle. There are 4 input terminals on figure 2.2 numbered 0 to 3. Selectors position on figure 2.2 is on input 3. Therefore any data on input 3 will be passed to output. Such mechanical selector can be implemented in digital logic as in figure 2.3. A to D is the input. S0 and S1 will select which output will be passed to F (output). This behavior can be verified by checking the truth table.

Figure 2.3 Multiplexer with 4 input b. Demultiplexer Demultiplexer the inverse of a multiplexer. Demultiplexer has 1 input, m selectors and n outputs (which m = 2n). A demultiplexer will pass any input to selected output for each A and B combination (figure 2.4).

Equipment a. Decoder and Encoder i. Power Supply PS-445 ii. Advance Logic Trainer CK-341 b. Multiplexer and Demultiplexer i. Power Supply PS-445 ii. Advance Logic Trainer CK-341 iii. IC 74(LS)153 2 pcs. iv. IC 74(LS)155 1 pc. v. IC 74(LS)157 1 pc. Experiment Procedure a. Decoder and Encoder i. Use built-in BCD to 7-segment decoder in Advance Logic Trainer CK-341. ii. Set input A0, A1, A2 and A3 on built-in decoder according to table A. iii. Make note for each activated segment as in figure 2.5 according to table A. b. Multiplexer and Demultiplexer i. Connect 5V line and Gnd line provided by the power supply with Advance Logic Trainer CK-341. ii. Use IC 74(LS)153 to build a multiplexer circuit. iii. Record the output! iv. Redo for IC 74(LS)155 as 1 to 4 and 1 to 8 decoder. v. Record the output!

3| Potential Hazards

Risk of electric shock due to high voltage appears on power supply.

Make an analysis for each experiment! Make a circuit diagram for each experiment! In coder experiment, what kind of 7segment is used? What needs to be done to the circuit if we want to use the other kind of 7 segment? Why the pin 1C-(2C), and (1G)-(2G) is connected in 1-8 demultiplexer experiment?

Explain about decoder and encoder and their differences! Explain the difference between 2 kinds of seven segment indicators and sketch the diagram! Explain about multiplexer and demultiplexer and their differences! How to simplify the equation of multiplexers output? Why do decoder, encoder, multiplexer and demultiplexer are included in rudimentary logic function? Explain

1|

OVERVIEW

Objectives: 1. Understand the basics of addition and subtraction using adder and subtractor circuit 2. Understand the concept of Half and Full Adder and Subtractor 3. Understand the concept of ripple adder and subtractor 4. Understand how to implement digital circuit on SPICE simulator (Xilinx/Proteus/Multisim)

1|BASIC THEORY

Half Adder, Full Adder, Half Subtractor, dan Full Subtractor In Digital Arithmetics, addition,subtraction, multiplication and division are based from binary operation.

Half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The carry signal represents an overflow into the next digit of a multi-digit addition. The value of the sum is 2C + S. The simplest half-adder design is like in picture 3.1, incorporates an XOR gate for S and an AND gate for C.

Picture 3.1 Half Adder Table 3.1 shows the result of addition of two 1bit-binary shown as A and B, where C show the value of Carry. Table 3.1 Half Adder Truth Table INPUTS A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 OUTPUTS C 0 0 0 1

Take a note that when A = B = 1 will make S = 0 and Carry = 1. From the table above the logic function of S is A XOR B, and for C is AB. These functions can be implemented in digital circuit as shown in picture 3.1, a half adder. A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A,B, and Cin; A and B are the operands, and Cin is a bit carried in from the adder circuit before or default value from user setting. The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. of binary numbers. The circuit produces a two-bit output, output carry and sum typically represented by the signals C as Carry and S for Sum. The truth table of full adder can be seen from table 3.2 below.

Table 3.2 Full Adder Truth Table INPUTS OUTPUTS A B Cin S 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 In Full adder circuit, if A, B and Cin have values of 1, then S and the C adalah is AB+Cin(A XOR B). Full adder circuit areshown in picture 3.2. C 0 0 0 1 0 1 1 1 1.

The logic function of S is A XOR B XOR Cin. For C, or carry out(Cout), the function

The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). The truth table is shown on the table 3.3 below.

From the tablel 3.3, the function of D can be written as Di=A B. Where in Bo the function is Bo=AB. The digital circuit from those two function which create half subtractor are shown below in picture 3.3.

Picture 3.3 Half Subtractor Like the Full Adder circuit, full-subtractor is a combinational circuit which is used to perform subtraction of three bits. It has three inputs, X and Y as subtraction variable and Z (Bin) as the borrow value from subtractor circuit before or user value. The two outputs are D (difference) and B (borrow). The Digital Circuit and Trut Table of full subtractor are shown below.

Table 3.4 Full Subtractor Truth Table A 0 0 0 0 1 1 1 1 INPUTS B 0 0 1 1 0 0 1 1 Bin 0 1 0 1 0 1 0 1 Di 0 1 1 0 1 0 0 1 OUTPUTS Bout 0 0 0 1 0 1 1 1

It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is called a ripple-carry adder, since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder. The layout of a ripple-carry adder is simple, which allows for fast design time; however, the ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. The ripple carry adder circuit are shown below in picture 3.5.

Picture 3.5 Ripple Carry adder The ripple carry subtractor is similar to ripple carry adder, the difference is the connected node is Bout (Borrow Out) to Bin (Borrow In) Instead of C to Cin. The rest of the concept is similar too.

2|

PROCEDURE

Datasheet of TTL Ripple Carry Adder Datasheet of TTL Ripple Carry Subtractor

a. Create new workspace! b. Create half adder and half subtractor in different design sheet! c. Create full adder and full subtractor developed from step 3 in different design sheet! d. Create ripple carry adder and ripple carry subtractor developef from step 4 in different design sheet. e. Complete the design by connecting all VCC and GND nodes and implement switch function as input for each design. f. Fill the data by performing simulation through the built desing

3|

Potential Hazards

Always make sure the VCC and GND is correctly connected and the VCC is 5V Make sure the saved design location design is known

4|

Give your analysis of the experiment on Table A (Ripple Carry Adder)! Give your analysis of the experiment on Table B (Ripple subtractor)! Give the overall conclusions of this experiment! Write in points form!

5|

TABLE A. RIPPLE CARRY ADDER

1. What adder and subtractor circuit are? Give the complete description about them! 2. Draw every type of adder and subtractor circuit! Give description on each of them

3. Describe why there is an inverter on Ripple Subtractor circuit whereas in Ripple

Adder there are none of them exists! 4. Give example of implementation of adder and subtractor on real life device (At least 1 for each of them)! Give complete description on how they work and write the source of the information (Journal preferable)

Objectives:

1. 2.

To understand the work principle of sequential circuit To understand the difference in work principles between sequential circuit and combinational circuit

3. To understand the work principle of flip flop as the base of sequential circuit and memory circuit

1|BASIC THEORY

The work principle of sequential circuit is different from combinational circuit. In sequential circuit, the output is determined from both last inputs given and the previous output. It is because the previous output works as feedback signal to its own circuit. In sequential circuit, the output is also determined by the order of inputs given to the circuit. The output can be different for the same value of inputs if the order of inputs given is also different. Based on its clock, there are two types of sequential circuit: synchronous sequential circuit and asynchronous sequential circuit. In synchronous sequential circuit, the circuit operation is controlled together with the same external clock signal. While in asynchronous sequential circuit, the circuit operation is not controlled together with the same external clock signal, but with the output of the previous circuit. The simplest sequential circuit is flip flop, or, in other words, bistable. In this experiment it will be shown the characteristic of flip flop so that it is used as the base element of memory. There are two common characteristics that all kinds of flip flop have: 1. Flip-flop is a bistable component, which means there are only two fixed condition, 0 and 1.Flip flop can hold or remember a binary bit information. If a signal input is given and the output becomes 1, then this 1 condition will be remembered until there is new signal that is able to change it into 0 or vice versa. 2. Flip flop has two outputs, which one of them is the complement of the other output. There are types of flip flop that dont need clock input such as RS Latch and D latch, but there are also some types that need clock input such as RS flip flop, D flip flop and JK flip flop. Clock is a periodic signal which is used to control the the work

order or synchronization in digital circuit. Usually, the clock used for digital circuit has the square-wave form like the figure below.

Below is the logic diagram of RS Latch using NOR gates and the logic diagram of RS flip flop.

Figure 4.3 RS Flip-flop The difference between those two figures is that the flip flop has clock signal input while the latch doesnt. The clock input in flip flop is only as synchronization to the circuit but the output remains the same. Table 4.1. PS/NS RS Flip-flop table q (present state) S R Q(next state) Q(next state) 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 0 1 1 x X 1 0 0 1 0 1 1 0 1 0 1 1 1 x X Characteristic equation of RS flip-flop: Q = S + Rq

D Latch is RS flip-flop, but the S and R input is complement to each other and create a new data (D) input, and there is another new inputk, Enable (Gate).

Q q 0 1

D flip flop is different from D latch, it has clock input so that the output will change on clock transition. There are two transition of clock, positive edge triggering, or the clock transition from L (low) to H (high) and negative edge triggering, or the clock transition from H (high) to L (low).

Figure 4.5 D Flip-flop Table 4.3 PS/NS D Flip-Flop table q (Present D Q (Next state) Q (Next state) state) 0 0 0 1 0 1 1 0 1 0 0 1 1 1 1 0 Characteristic equation of D Flip-Flop : Q = D

f. JK Flip Flop

Just like D flop flop, JK flip flop also needs clock pulse as one of its inputs. This clokc input causes the output to change with the transition of the clock pulse. JK flip flop has special characteristic, which is when both J and K inputs are all have the value 1, then the output will alternate between 0 and 1 for each clock transition. In other words, this condition is called TOGGLE.

Figure 4.6 JK Flip-flop Table 4.4 PS/NS JK Flip-Flop Table q (Present J K Q (Next state) state) 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0 Characteristic equation of JK Flip-Flop : Q = Jq + Kq

2 | PROCEDURE

Materials: 1 Power Supply 1 Advance Logic Trainer Module 1 IC 74LG279 (RS Latch) 1 IC 74LS75 (D Latch) 1 IC 74LS74A (D Flip-flop) 1 IC 74LS76A (JK Flip-flop) 1 IC 74LS73A (JK Flip-flop) 1 IC NE555 (Timer) 20 Cables

a. b.

c.

Connect the power supply (5V) to the Advance Logic Trainer. Put IC 74LG279 (RS Latch) to the Advance Logic Trainer and connect each IC pin with switch module for inputs and LED module for outputs from the Advance Logic Trainer. Check the characteristic of IC 74LG279 (RS Latch) tersebut by giving inputs corresponding to table A.

d.

e.

Repeat step 2 and 3 for IC 74LS75 (D Latch), IC 74LS74A (D flip-flop), IC 74LS76A (JK flip-flop) andIC 74LS73A (JK flip-flop) by giving inputs corresponding to table B, C, D, and E. For flip flops which uses clock signal, connect the corresponding IC pin with clock signal from IC NE555 module from Advance Logic Trainer.

B. Potential Hazards Check if the power supply connect correctly to the Advance Logic Trainer and to the IC. Dont be confused between VCC and ground. Each must be connected correctly, not get swapped and not connect to each other. Put the IC correctly, dont get inverted when putting the IC to the socket.

1. Give the analysis of RS Latch Experiment! 2. Give the analysis of D latch experiment! 3. Give the analysis of D flip-flop experiment! 4. Give the analysis of JK flip-flop (IC 74LS76A) experiment! 5. Give the analysis of JK flip-flop (IC 74LS73A) experiment! Give the Conclusion of these experiments by using mutiple points

S 0 1 1 1 0 0 1 0 Table A. RS Latch (IC 74LG279) R Q 1 1 0 1 1 0 0 0 Table B. D Latch (IC 74LS75) G Q 0 0 1 0 Q

D 0 1 0 0

1 1

1 0 Table C. D Flip-Flop (IC 74LS74A) INPUTS CLEAR CLOCK D 1 X X 0 X X 0 X X 1 1 1 0 1 0 X Table D. JK Flip-Flop (IC 74LS76A) INPUTS CLEAR CLOCK J K 1 X X X 0 X X X 0 X X X 1 0 0 1 1 0 1 0 1 1 1 1 1 1 X X Table E. JK Flip-Flop (IC 74LS73A) INPUTS CLOCK J K X X X 0 0 1 0 0 1 1 1 1 X X

OUTPUTS Q Q

PRESET 0 1 0 1 1 1

PRESET 0 1 0 1 1 1 1 1

OUTPUTS Q Q

OUTPUTS Q Q

CLEAR 0 1 1 1 1 1

b. c. d. e. f.

Explain about sequential circuit and give an example! Explain the difference between sequential circuit and combinational circuit! Explain about flip flop, the types of flip flop and the figures of the circuits! Explain about Toggle in JK flip flop! Explain about state diagram and timing diagram!

Module 5: Counter

Objectives:

1. Understanding the principle of flip-flop in counter. 2. Students understand the difference of synchronous and asynchronous counter.

1|BASIC THEORY

A counter is a sequential logic circuit that goes through a prescribed sequence of states upon the application of input pulses. The prescribed sequence can be a binary sequence or any other sequence. A counter that goes through 2N (N is the number of flip-flops in the series) states is called a binary counter. The modulus of a counter is the number of different states it is allowed to have. Counter modulus is normally 2N unless controlled by a feedback circuit which limits the number of possible states (an example being the decimal counter). Counters are very widely used in almost all computers and other digital electronic systems. There are two major categories of counters: asynchronous counters and synchronous counters.

g. ASYNCHRONOUS COUNTER

Counters arranged so that the output of one flip-flop generates the clock input of the next higher stage are generally called asynchronous counters (or ripple counter). In other words, in asynchronous counters, the CLK inputs of all flip-flops (except the first one) are triggered not by the incoming pulses but rather by the transition that occurs in other flip-flops. Therefore, the change of state of a particular flip-flop is dependent upon the present state of other flip-flops. Figure 1

h. SYNCHRONOUS COUNTER

Synchronous counters eliminate the cumulative flip-flop delay seen in ripple counter. Each flip-flop is clocked by the same clock signal. Each gate selectively controls when each more significant bit flip-flop is to change state (toggle) on the next clock transition. Such control (enable) can be realized by setting, for example, the J and K inputs of a J-K flip-flop. Because of this control, the addition of a common clock will synchronize data transfer and all flip-flops will change state simultaneously. The important feature of a synchronous counter is that the transitions of the individual flip-flops are synchronized to a master clock signal.

i. TIMING DIAGRAM

Because this 4-bit synchronous counter counts sequentially on every clock pulse the resulting outputs count upwards from 0 (0000) to 15 (1111). Therefore, this type of counter is also known as a 4-bit synchronous up counter. But, in many applications require the counter which count 0-9. Therefore, we use decade

counter. Figure 4. Asynchronous decade counter This type of asynchronous counter counts upwards on each leading edge of the input clock signal starting from 0000 until it reaches an output 1010 (decimal 10). Both outputs Q1 and Q2 are now equal to logic 1 and the output from the NAND gate changes state from logic 1 to a logic 0 level and whose output is also connected to the CLEAR (CLR) inputs of all the J-K Flip-flops. This signal causes all of the Q outputs to be reset back to binary 0000 on the count of 10. Once Q1 and Q3 are both equal to logic 0 the output of the NAND gate returns back to a logic level 1 and the counter restarts again from 0000. We now have a decade or Modulo-10 counter.

2 | PROCEDURE

Materials Power Supply Advances Logic Trainer IC 74LS93 (4-bit binary asynchronous counter) IC 74LS90 (4-bit decade asynchronous counter) IC 74LS163 (4-bit binary synchronous counter) IC 74LS162 (4-bit decade synchronous counter) Wires

h. Mount IC 74LS93 (4-bit binary asynchronous counter) on the board and make the connections as shown in datasheet. (SWITCH as input and LED as output)! i. Now connect CLOCK to a pulse and start counting by pushing the pulse button! j. Continue the process and look at the output. How the influence of the clock signal on the output? Record the output of each transition in a table A! k. Repeat the same procedure (b, c, and d) and record the output of each transition in table B, C, and D for each of IC!

a. Analysis 1) Make an analysis of 1st experiment! 2) Make an analysis of 2nd experiment! 3) Make an analysis of 3rd experiment! 4) Make an analysis of 4th experiment!

c. Basic Theory 1) What is counter in digital system? Give an example and make a diagram block!

d. Data Form

Table A. 4-bit binary asynchronous counter IC 74LS193 Count 0 1 2 3 4 5 6 7 Qa Qb Qc Qd Count 8 9 10 11 12 13 14 15 Note: R0(1) = 0 ; R0(2) = 0 Qa Qb Qc Qd

Table B. 4-bit decade asynchronous counter IC 74LS90 Count 0 1 2 3 4 Qa Qb Qc Qd Count 5 6 7 8 9 Note: R0(1) = 0 ; R0(2) = 0 ; Rg(1) = 0 ; Rg(2) = 0 Qa Qb Qc Qd

Note: CLEAR = 1 ; LOAD = 1 ; DATA INPUT A,B,C,D = 0 ; ENABLE P,T = 1 Warning the ripple carry output when count 15 or 1111 in binary!

Note: CLEAR = 1 ; LOAD = 1 ; DATA INPUT A,B,C,D = 0 ; ENABLE P,T = 1 Warning the ripple carry output when count 9 or 1001 in binary!

g. h. i. j.

Explain about register! Explain about shift register! Explain about counter, give an example and also the block diagram! Explain the difference between asynchronous counter and synchronous counter!

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