LIC & Applications

UNIT I
IC FABRICATION
PART A
1. What are the advantages of Integrated circuits?
1. Miniature size and hence increases equipment density
2. Cost reduction due to batch processing
3. Increased system reliability due to the elimination of soldered joints.
4. Reduction in power consumption
5. Increasing operation speed
6. Improved functional performance.
2. Classify the types of ICs.
Integrated Circuits can be classified based on
(i) Based on Mode of operation
(a) Digital I.C.
(b) Analog I.C. (Linear IC)
(ii) Based on fabrication
(a) Monolithic I.C.
(b) Hybrid I.C.
(iii) Based on Integration level
(a) SSI Small Scale I.C.
(b) MSI Medium Scale I.C.
(c) LSI Large Scale I.C.
(d) VLSI Very Large Scale I.C.
3. What is meant by monolithic technology?
Monolithic technology all the active and passive elements along with their interconnections
are manufactured on a single chip of Silicon. It is a highest order of reliability. Hence they are
preferred only in low power applications.
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4. Name the different types of IC packages (May-06)
1. Metal can package
2. Ceramic flat package
3. Dual in line package.
5. What is meant by Epitaxy?
The word epitaxy is derived from Greek word epi meaning upon and the past tense of
the word tension meaning arranged. So, one could describe epitaxy as arranging atoms in single
crystal fashion upon a single crystal substrate; so that the resulting layer is an extension of the
substrate crystal structure.
6. Distinguish between monolithic integrated circuits and hybrid integrated circuits.
Monolithic Integrated Circuits Hybrid Integrated Circuits
In Monolithic circuits, all circuit components both
active and passive elements and their
interconnections are manufactured into or on top
of a single chip of silicon.
Hybrid Integrated circuits separated component
parts are attached to a ceramic substrate and
interconnected by means of either metallization
pattern or wire boards.
It is used for more applications in Linear and
digital IC
It is used for adopt less applications
Cost wise is less. Cost wise is slightly higher compared to monolithic
ICs.
They are preferred only in low power
applications.
They are preferred for high power applications.
7. What is meant by thermal Oxidation?
The process of oxidation is called Thermal Oxidation because high temperature is used to
grow the oxide layer. The thickness of the film is governed by time, temperature and the moisture
content. The thickness of oxide layer is usually in the order 0.02 to 2 m.
8. What are the important purpose of SiO2?
SiO2 has the property of preventing the diffusion of almost all impurities through it.
1. SiO2 is extremely hard protective coating and is unaffected by almost all reagents except
hydrofluoric acid. Thus it stands against any contamination.
2. By Selective etching of SiO2, diffusion of impurities through carefully defined windows in
the SiO2 can be accomplished to fabricate various components.
9. List the disadvantage of ICs.
(a) Inductors cannot be fabricated.
(b) IC functions at fairly low voltage.
(c) They can handle only limited amount of power. Cannot with stand rough handling and
excessive heat.
10. What are reasons for Aluminiumis mostly used for metallization of ICs?
1. It is relatively a good conductor
2. It is easy to deposit aluminium films using vacuum deposition.
3. Aluminium makes good mechanical bands with silicon.
4. Aluminium forms low resistance, non rectifying contact with p type silicon and the
heavily doped n type silicon.
PART B
1. Explain how the silicon wafer prepared and Epitaxial Growth?
silicon wafer preparation:
The following steps are used in preparation of Si wafers.
1. Crystal growth and doping
2. Ingot trimming and grinding.
3. ingot slicing
4. wafer polishing and etching
5. wafer cleaning.
The starting material for crystal growth is highly purified (99.99999) polycrystalline silicon.
The Czochralski crystal growth process is the most often used for producing single crystal silicon
ingots. The poly crystalline silicon with an appropriate amount of do pant is put in a quartz
crucible and is then placed in a furnace. The material is then hated to a temperature in excess of
the silicon melting point of 1420C. A small single crystal rod of silicon called a seed crystal is then
dipped in to the silicon melt and slowly pulled out as shown in fig. As the seed crystal is pulled
out of the melt, it brings with it solidified mass of silicon with the same crystalline structure as
that of seed crystal. During the crystal pulling process, the seed crystal and the crucible are rotated
in opposite directions in order to produce ingots of circular cross- section. The diameter of the
ingot is controlled by the pulling rate and the melt temperature. Ingot diameter of about 10 to 15
cm is common and ingot length is generally of the order of 100cm.
Next the top and bottom portions of the ingot are cut off and the ingot surface to produce
an exact diameter (D = 10, 12.5, 15 cm). The ingot is also ground flat slightly along the length to get
a reference plane. The ingot is then sliced using a stainless steel saw blade with industrial
diamonds embedded in to the inner diameter cutting edge. This produce circular wafers or slices
as shown in fig. the orientation flat portion serves as a useful reference place for the various
processes described later. The silicon wafer so obtained have very rough surface due to slicing
operation.
These wager undergo a number of polishing steps to produce a flat surface. Then one side
of the wafer is given a final mirror smooth highly polished finish, whereas the other side is
simply lapped on an abrasive lapping machine to obtain an acceptable degree of flatness. Finally,
the wafer are toughly rinsed and dried. A raw cut slice the thickness 23 40 mils produces wafers
of 16 -32 mils thickness after all the polishing steps.
These silicon wafers will contain several hundred rectangular chips, each one containing a
complete integrated circuit. After all the IC fabrication processes are complete, these wafer are
sawed into 100 to 8000 rectangular chips having side of 10 to 1mm. each chip is a single IC and
may contain hundreds of components. The wafer thickness therefore is so chosen that is possible
to separate chips without breaking and at the same time. It gives sufficient mechanical strength to
Rotation
Pull
Seed crystal
Silicon ingel
Quartz
crucible
Silicon melt
T> 1420 C
D
D = 10, 12, 5,
15 cm
Orientation
flat
the IC chip.
Epitaxial Growth :
The word epitaxy is derived from Greek word epi meaning Upon and the past tense of
the word tension meaning arranged. So, one could describe epitaxy as, arranging atoms in
single crystal fashion upon a single crystal substrate, so that the resulting layer is an extension of
the substrate crystal structure. The basic chemical reaction used for the epitaxial growth of pure
silicon is the hydrogen reduction of silicon tetrachloride.
1200C
SiC4 +2H2 Si + 4HCI
Mostly, epitaxial films with specific impurity concentration are required. This is
accomplished by introducing phosphine (PH3) for the n type and bi borane (B2 H6) for p type
doping into the silicon tetrachloride hydrogen gas stream.
The process is carried out in a reaction chamber consisting of a long cylindrical quartz tube
encircled by a RF induction coil. Fig shows the diagrammatic representation of the system used.
The silicon wafers are placed on a rectangular graphite rod called a boat. This boat is then placed
in the reaction chamber where the graphite is heated inductively to a temperature 1200C. The
various gasses required for the growth of desired epitaxial layers are introduces into the system
through a control console.
Fig. A diagrammatic representation of a system for growing silicon epitaxial fill
the IC chip.
Epitaxial Growth :
1200C
SiC4 +2H2 Si + 4HCI
the IC chip.
Epitaxial Growth :
1200C
SiC4 +2H2 Si + 4HCI
Fig. Oxidation apparatus
2. Explain the Oxidation and Photolithography process?
SiO2 has the property of preventing the diffusion of almost all impurities through it. it
serves two very important purposes.
1. SiO2 is an extremely hard protective coating and is unaffected by almost all reagents except
2. By selective etching SiO2 diffusion of impurities through carefully defined windows in the
SiO2 can be accomplished to fabricate various components.
The silicon wafers are stacked up in a quartz boat and then inserted into quartz furnace tube.
The Si wafers are raised to a high temperature in the range of 950 to 1115C and at the same
time, exposed to a gas containing O2 or H2O or both. The chemical reaction is
Si + 2H2O SiO2 + 2H2
This oxidation process is called thermal oxidation because high temperature is used to
content. The thickness of oxide layer is usually in the order of 0.02 to 2 m.
Photolithography:
With the help of photolithography, it has become to produce microscopically small circuit
and device patterns on Si wafers. As many as 10,000 transistors can be fabricated on 1 cm 1cm
chip. The conventional photolithographic process used ultraviolet light exposure and device
dimension or line width as small as 2 m can be obtained. However, with the advent of latest
technology using X ray or electron beam lithographic technique, it has become possible to
produce device dimension down to submicron range (<1 m).
Photolithography involves two process, namely; Making of a photographic mask.
Photo etching:
The making of a photographic mask involves the following sequence of operations first the
preparation of initial artwork and secondly, its reduction. The initial layout or artwork of an IC is
normally done at a scale several hundred times larger than the final dimensions of the finished
monolithic circuit. This is because, for a tiny chip, larger the artwork, more accurate is the final
mask. For example it is often required to make an opening of width about 1 mil (25 m).
Obviously this cannot be managed by any draftsman even with his thinnest of sketch pens. So the
drawings are made magnified and often by a factor of 500. With the magnifications, it is easy to
see that a width of one mil is magnified to a width of 500 mils. That is, about 1.2 cm. Therefore, for
a finished monolithic chip area 50 mil 50 mil, the art work will be made on area of about 60 cm
60 cm.
This initial layout is then decomposed into several mask layers, each corresponding to a
proceeds step in the fabrication schedule. E.g. a mask for base diffusion, another for collector
diffusion, another for metallization and so on. For photographic purpose, artwork should not
contain any line drawing but must be of alternate clear and opaque regions. This is accomplished
by the use of clear Mylar coated with a sheet of red photographically opaque Mylar (trade name
Rubylith). The red layer can be easily peeled off this exposing clear with a knife edge from the
regions where impurities have to be diffused. The artwork is usually produced on a precision
drafting machine, known as co-ordinatograph. The coordinatograph has a cutting heat that can be
positioned accurately and moved along two perpendicular axes. The coordinatograph outlines the
pattern cutting through the red Mylar without damaging the clear layer underneath.
This rubylith pattern of individual mask is photograph and then reduced in steps by a
factor of 5 or 10 several times to finally obtain the exact image size. The final image also must be
repeated many times in a matrix array, so that many ICs will be produced in one process. The
photo repeating is done with a step and repeat camera. This is an imaging device with a
photographic plate on a movable platform. Between exposure, the plate is moved in equal steps so
that successive images form in an array. When the exposed plate is developed it becomes a master
mask. The masks, actually used in IC processing are made by contact printing from the master.
These working masks wear out with use and are replaced as required. Images form in an array.
Photo etching is used for the removal of SiO2 from desired regions so that the desired
impurities can be diffused. The water is coated with a film of photosensitive emulsion (Kodak
Photo resist KPR). The thickness of the film is in the range of 5000 10000 A as shown fig (a) The
mask (negative of the desired pattern) as prepared by steps described earlier is placed over the
photo resist coated wafer as shown in fig. (b) This is now exposed to ultraviolet light, so that KPR
becomes polymerized beneath the transparent region of the mask. The mask is then removed and
the wafer is developed using a chemical (trichloroethylene) which dissolves the unexposed / un-
polymerized regions on the photo resist and leaves the pattern as shown in fig. the polymerized
photoresist is next fixed or cured, so that it becomes immune to certain chemicals called enchants
used in subsequent processing steps. The chip is immersed in the etching solution of hydrofluoric
acid, which removes the SiO2 from the areas which are not protected by KPR as shown in fig, after
diffusion of imurities; the photo resist is removed with a chemical solvent (hot H2SO4) and
mechanical abrasion.
The etching process described is a wet etching process and the chemical reagents used are in
liquid form. A new process used these days is a dry etching process called plasma etching. A
major advantage of the dry etching process is that it is possible to achieve smaller line opening (s 1
m) compared to wet process is beyond the scope of this book.
X ray and Electron Beam Lithography:
With conventional ultraviolet (UV) photolithography process in which the UV wavelengths
used are in the range 0.3 to 0.4 m, the minimum device dimensions or line widths are limited by
diffraction effects to around five wavelengths or about 2 m. This is what puts an upper limit on
the IC device density using UV photolithography.
With the advent of X ray and electron beam lithography technique, it has become possible
to produce device dimensions down to submicron range (< 1 m). This is due to much shorter
wavelength involved. With these techniques MOSFET with gate length as small as 0.25 m have
been made. The cost of X ray or electron beam equipment is very high and the exposure times
very much longer than with UV photolithography. So this becomes a very expensive process and
is used only when very small device dimension (s 1 m) are needed.
3. Explain about diffusion, ion implantation and Isolation?
Diffusion:
Another important process in the fabrication of monolithic ICs is the diffusion of impurities
in the silicon chip. This uses a high temperature furnace having a flat temperature profile over a
useful length (about 20 length). A quartz boat containing about 20 cleaned wafers is pushed into
hot zone with temperature maintained about a 1000C. Impurities to be diffused are rarely used in
their elemented forms. Normally, compounds such as B2O3 (Boron oxide), BCI3 (Boron chloride)
are used for Boron and P2O5 (phosphorous pentaoxide) and POCI3 (phosphorous oxychloride) are
used as sources of Phosphorous. A carrier gas, such as dry oxygen or nitrogen us normally used
for sweeping the impurity to the high temperature zone. The depth of diffusion depends upon the
time of diffusion depends upon the time of diffusion which normally extends to 2 hours.
The diffusion of impurities normally takes places both laterally as well as vertically.
Therefore, the actual junction profiles will be curved as shown in fig. However for the sake of
simplicity, lateral diffusion will be omitted in all the drawings.
Diffusion:
Diffusion:
ION IMPLANTATION:
On implantation is the other technique used to introduce impurities into a silicon wafer. In
this process, silicon wafer are placed in a vacuum chamber and are scanned by a beam of high
energy doping ions (borons for p type and phosphorus for n type) as shown fig. these ions are
accelerated by energies between 20 kV to 25 kV. As the ions strike the silicon wafers, they
penetrate some small distance into the wafer. The depth of penetration of any particular type of
ion increases with increasing accelerating voltage. Ion implantation technique has two important
advantages:
1. It is performed at low temperature. Therefore, previously diffused regions have lesser
tendency for lateral spreading.
2. In diffusion process, temperature has to be controlled over a large area inside the oven,
whereas in ion implantation techniques, accelerating potential and the beam current are
electrically controlled from outside.
Fig. Ion implantation system
ISOLATION TECHNIQUES:
Since a number of components are fabrication on the same IC chip, it becomes necessary to
provide electrical isolation between different components and interconnection. Various types of
isolation technique have been developed. However, we shall discuss here only two commonly
used techniques namely.
ION IMPLANTATION:
advantages:
ION IMPLANTATION:
advantages:
p n junction isolation:
In this isolation technique p* - type impurities are selectively diffused into the n type
epitaxial later so as to reach p type substrate as shown fig (a) This produces islands surrounded
by p type moats. It can be seen that these regions are separated by two back to back p n
junction diodes. If the p type substrate material is held at the most negative potential in the
circuit, the diodes will be reverse biased providing electric isolation islands. The concentration of
the acceptor atoms in the regions between isolation islands is usually kept much higher (p*) than
the p type substrate. This prevents the depletions region of the reverse biased diode from
penetrating more into p* region and possibly connecting the isolation islands.
There is, however, one undesirable by produce of this isolation process. It is the presence
of a transition capacitance at the isolating p n junctions, resulting in an inevitable capacitor
coupling between the components and the substrate; these parasitic capacitances limit the
performance of the circuit a high frequencies. But being economical, this technique is commonly
used for general purpose ICs.
Dielectric Isolation:
Here a layer of solid dielectric such as silicon diode or ruby completely surrounds each
component, thereby producing isolation, both electrical and capacitance is neglible. Also, it is
possible to fabricate both p n- p and n p n transistor within the same silicon substrate. Since
this method requires additional fabrication steps, it becomes more expansive. This technique is
mostly used for fabricating professional grade ICs required grade ICs required for specialized
applications viz, fig (b) shows such a structure.
Fig. (b) Dielectric isolation
4. Explain about metallization and packaging?
METALLIZATION:
The purpose of this process is to produce at thin metal film layer that will serve to make
interconnections of the various components on the chip. Aluminium is usually used for the
metallization of most ICs as it offers several advantages.
2. It is easy to deposit aluminum films using vacuum deposition.
3. Aluminium makes goods mechanical bonds with silicon.
4. Aluminium forms low resistance, non rectifying (i.e. ohmic) contact with p type silicon
and the heavily doped n type silicon.
The film thickness of about 1 m and conduction width of about 2 to 25 m are commonly
used. The process takes place in a vacuum evaporation chamber as shown fig. the pressure in the
chamber is reduced to the range of about 10 6 to 10 7 tar ( 1 atmosphere = 760 torr = 760 mm
Hg). The tungsten coil or basket. A very high power density electron beam is focused at the
surface of the material to be evaporated. This vapours travel in straight line paths. The evaporated
molecules hit the substrate and condense there to form a thin film coating.
After the thin film metallization is done, the film is patterned to produce the required
interconnections and bonding pad configuration. This is done by photolithographic process and
aluminium is etched away form unwanted places by using etchans like phosphoric acid (H3PO4).
METALLIZATION:
METALLIZATION:
Assembly Processing And Packaging
Each of the water processed contains several hindered chips, each being a complete circuit.
So these chips must be separated and individually packaged. A common method called scribing
and cleaving used for separation make use of a diamond tipped tool to cut lines into the surface of
the water along the rectangular gird separating grid separating the individual; chips. Then the
wafer is fractured along the scribe lines and the individual chips are physically separated. Each
chip is then mounted on a ceramic wafer and attached to a suitable package.
There are three different package configurations available.
1. TO - 5 glass metal package
3. Dual in line (ceramic or plastic type)
TO 5 packages are available in 8, 10 or 12 leads, whereas the flat or dual in line package is
commonly available 8, 4 or 16 leads, but even 24 or 36 or 42 leads are also available for special
circuits. Ceramic packager, whether of flat type or dual in line are costly due to fabrication
process, but have the advantage or best hermetic sealing. Most of the general purpose ICs are dual
in line plastic packages due to economy.
5. For the Logic show in fig describe in detail the various processes for the fabrication in
monolithic form?
Fabrication of a Typical circuit:
We shall here since various steps utilized in converting the circuit into the monolithic IC of Fig.
Step 1: Wafer Preparation:
3
A
N 1.4 atoms/ cm
p type substrate
ohms cmresistivity
=
c
400
monolithic form?
3
A
N 1.4 atoms/ cm
p type substrate
ohms cmresistivity
=
c
400
monolithic form?
3
A
N 1.4 atoms/ cm
p type substrate
ohms cmresistivity
=
c
400
Refer fig starting material called the substrate is a p type silky wafer prepared as
discussed in Sec 1.5.1. The wafer are usually of 10 cm diameter and 0.4 m ( - 400 ,m) thickness.
The receptivity is approximately 10 O - cm corresponding to concentration of acceptor atom, NA =
1.4 10
15
atoms / cm
15
atoms / cm
3.
Step 2: Epitaxial Growth:
An n type eptixial film ( 5 25 m) is grown on the p type substrate as shown in Fig.
This ultimately becomes the collector region of the transistor, or an element of the diode and
diffused capacitor associated with the circuit. So in general it can be said that all active and passive
components are fabricated within this layer. The receptivity of n epitaxial layer is of the order of
0.1 to 0.5 O - cm.
Step 3: Oxidation:
A SiO2 layer of thickness of the order of 0.02 to 2 m is grown on the n epitaxial layer.
Step 4 : Isolation Diffusion:
In the circuit of Fig four components have to be fabricated, so we required for islands which
are isolated. For this SiO2 is removed from five different places using photolithographic technique.
Refer fig (d). The wafer is next subjected to heavy p type diffusion for a long time interval so that
p type.
n-epi layer 0.1 0.5 O -cm
p-type substrate 10 O -cm
5 25 m
n-epi layer
p-type substrate
0.02 2 m
SiO
2
1.4 10
15
atoms / cm
15
atoms / cm
3.
0.1 to 0.5 O - cm.
Step 3: Oxidation:
p type.
5 25 m
n-epi layer
p-type substrate
0.02 2 m
SiO
2
1.4 10
15
atoms / cm
15
atoms / cm
3.
0.1 to 0.5 O - cm.
Step 3: Oxidation:
p type.
5 25 m
n-epi layer
p-type substrate
0.02 2 m
SiO
2
Steps in the fabrication of the circuit shown in fig impurities penetrate the n type epitaxial
layer and reach this p type substrate. The area under the SiO2 are n type island that are
completely surrounded by p type moats. As long as the p n junctions between the isolation
islands are held at a negative potential with respect to the n type isolation islands, these regions
are electrically isolated from each other by two back to back diodes, providing the desired
isolation.
The concentration of acceptor atoms (NA = 5 10
20
cm
-3
) in the region between isolation
islands is generally kept higher than p type substrate for which Na = 1.4 10
15
atoms / cm
3
. This
ensure that the depletion region of the reverse biased diode will not extend into p* region to the
extend of electrically connecting the two isolation islands. There will, however, be as significant
amount of barrier of transition capacitance present as a by product of the isolation diffusion. The
top view of the isolation islands is depicted in fig.
Step 5: Base Diffusion:
Refer to fig A layer of SiO2 is grown over the entire wafer and a new pattern of openings is
formed using photolithographic technique. Now, p type impurities, such as boron, are diffused
through the openings into the islands of n type epitaxial silicon. The depth of this diffusion must
be controlled so that it does not penetrate through n layer into the substrate. This diffusion is
utilized to form base region, of the transistor, resistor, the anode of the diode and junction
capacitor.
isolation.
20
cm
-3
15
atoms / cm
3
. This
capacitor.
isolation.
20
cm
-3
15
atoms / cm
3
. This
capacitor.
Step 6: Emitter Diffusion:
Refer to fig (g) A new layer of SiO2 is again grown over the entire wafer and selectively
etched to open a new set of windows and n type impurity.
6. Explain about Resistors Fabrications?
Integrated Resistors:
The basic technique for obtaining a resistor in integrated circuit is by utilizing the bulk
resistance of a defined volume of semiconductor region. Four different methods are available for
fabricating integrated resistors, namely:
Diffused Resistor
Epitaxial Resistor
Pinched Resistor
Thin Film Resistor
Diffused Resistor:
In this method, resistor is formed in one of the isolated regions of epitaxial layer during
base or emitter diffusions common to bipolar transistor fabrication. A no extra fabricating steps
Diffused Resistor
Epitaxial Resistor
Pinched Resistor
Thin Film Resistor
Diffused Resistor:
Diffused Resistor
Epitaxial Resistor
Pinched Resistor
Thin Film Resistor
Diffused Resistor:
are required this type of resistor is very economical. However, a server limitation is the small
range of resistance possible.
The value of the resistance depends upon the surface geometry. That is length, width and
upon the diffused impurity profile. In this context, a very useful quantity sheet resistance is
defined as diffused layers are very thin.
Sheet Resistance Rs:
Consider the square L L of a material of resistively p, thickness t, and cross sectional
area A = L t shown in Fig (a), the resistance of this sheet of material can be written as
, )
pL p
Rs ohms per square
L t t
= =
The quantity Rs is independent of the size of the square and mainly depends upon the
diffusion characteristic of the material. Now consider Fig. (b, c) which shows a base resistor and
the emitter resistor. The resistance for these resistors can be expressed in terms of the sheet
resistance Rs and the surface dimensions L and W.
Now R = pL / W t
Or, R = Rs L / W
Where the ratio L/W is called the aspect ratio of the surface geometry and is, therefore, the
effective number of square contained in the resistor. The base resistor in the range of 20 O to 300
kO can be easily fabricated due to medium resistivity ( 200O / square) p type base region.
However, the sheet resistance of the emitter diffusion is of the order the 5 O / sq. only. So emitter
resistors are usually in the range of 10 to 1 kO.
Example:
, )
pL p
Rs ohms per square
L t t
= =
Now R = pL / W t
Or, R = Rs L / W
Example:
, )
pL p
Rs ohms per square
L t t
= =
Now R = pL / W t
Or, R = Rs L / W
Example:
Design a 4 O diffused resistor.
The sheet resistance of p type diffusion I s200 ohm / sq.
3
L 4Kt10 20
Then
W 200 1
= =
So a 4 kO resistor can be fabricated by 1 m wide a shown by the top view in fig (d).
Epitaxial Resistor:
Large value of resistance than possible by base or emitter resistor can be achieved by using
n epitaxial collector region as shown in Fig 1.23 (a). Sheet resistance of epitaxial layer in the
order 1 to 10 kO / square can be obtained.
Pinched Resistor:
The sheet resistivity of a semiconductor region can be increased by reducing its effective
cross sectional area. In a pinched resistor, this technique is used to achieve a high value of sheet
resistance from the ordinary base diffused resistor.
3
L 4Kt10 20
Then
W 200 1
= =
Epitaxial Resistor:
Pinched Resistor:
3
L 4Kt10 20
Then
W 200 1
= =
Epitaxial Resistor:
Pinched Resistor:
A pinched base diffused resistor is shown in Fig(b). It can give resistances of the order of
mega-ohm in a reasonably small area. In this structure, no current can flow through the n type
material (dark region ) due to the diode at contact 2 in the reverse direction. Only a small reverse
saturation current can flow through n material. So, by creating these n type regions the
effective cross sectional area of the conduction path has been reduced and thus resistance
between 1 and 2 increases.
Thin Film Resistor:
Vapour thin film deposition techniques as discussed in Sec. 1.5.8 can also be used for the
fabrication of IC resistors. In this, a very thin metallic film usually of Nichrome (NiCr) of thickness
less 1 m is vapour deposited on the SiO2 layer. Using masked etching, desired geometry of this
thin film is achieved to obtain suitable values of resistors. The ohmic contacts are made using A1
metallization and usual masked etching techniques. Nichrome resistors are available with typical
sheet resistance values of 40 to 400 O / square depending upon film thickness, so that resistance in
the range of 20 to 50 kO can be easily obtained. Fig (c) shows the cross sectional view of such a
resistor. These thin film resistors have three distinct advantages over the diffused resistors.
a. The film resistors have lesser and smaller parasitic components and hence their high
frequency behaviour is better.
b. The values of thin film resistors can be easily adjusted even after fabrication by
cutting a part of the resistors with a laser beam (Laser trimming).
c. Thin film resistors have low temperature co efficient, thereby making them more
stale.
Higher values of thin film resistors have been obtained by depositing Tantalum over SiO2
layer. The main disadvantages of thin film resistors is the additional process steps required in
their fabrication.
(c) Cross-section of a thin film resistor
Thin Film Resistor:
stale.
their fabrication.
Thin Film Resistor:
stale.
their fabrication.
UNIT II
CHARACTERISTICS OF OPAMP
PART A
1. What is an Op amp?
An operational Amplifier is a direct-coupled high-gain amplifier consisting of one or more
differential amplifiers and usually followed by a level translator and an output stage.
It is a versatile device that can be used to amplify dc as well as ac input signals.
2. Draw block diagram of a typical OP-Amp.
3. Design an amplifier with a gain of -10 and Input resistance equal to 10 K.
Given the gain of the amplifier is ve so inverting amplifier has to be mode.
o f
in 1
V R
V R
= f
Choose
R1 = 10 KO
Rf = - ACL R1
+
-
O/p terminal
Non INV /IP
INV/IP
Output Input
Stage
Inter-
mediate Stage
Level
Shifting Stage
O/P
Stage
Non inverting
Input
Inverting
Input
Dual - input
balanced
output
differential Amp
Dual - input
Unbalanced
output
differential
Amplifier
Emitter
Follower using
Constant Current
source
Complementary
Symmetry
Push-pull amplifier
= - (-10) (10KO)
f
R 100K = O
4. Describe the word voltage follower and draw its circuit?
The output voltage is equal to I/P voltage both in magnitude and phase. In other words we
can also say that the o/p voltage follows the I/P voltage exactly.
Vo = Vin
For this circuit voltage gain is unity.
5. Give the circuit diagram of differentiation?
o in
d
V CR V (t)
dt
=
6. What are the characteristics of Ideal OP-Amp?
1. Infinite Voltage gain A.
2. Infinite input Impedance.
3. Zero Output Impedance.
= - (-10) (10KO)
f
R 100K = O
Vo = Vin
o in
d
V CR V (t)
dt
=
= - (-10) (10KO)
f
R 100K = O
Vo = Vin
o in
d
V CR V (t)
dt
=
4. Zero Output Voltage
5. Infinite Bandwidth.
6. Infinite Common-mode Rejection ratio.
7. Infinite slew rate.
7. What are the Basic op amp applications?
1. Scale changer inverter
2. Summing amplifier
3. Inverting summing amplifier
4. Non inverting summing amplifier
5. sub tractor
6. Adder subtractor
8. Write the equation of voltage gain in non inverting amplifier?
= = +
0 f
1 1
V R
ACL 1
V R
9. What is common mode rejection ratio.
The relative sensitivity of an op amp to a difference signal as compared to a common
mode signal is called common mode rejection ratio.
d
c
A
P expressed in dB
A
=
10. What are the methods to improve slew rate?
(i) Slew rate can be improved with higher closed-loop gain and dc supply voltage. Slew rate
decreases with increases in temperature.
(ii) Another method for improving slew rate is, the rate at which voltage across the capacitor
increases is give by
c
dV I
dt C
=
for higher the slew rate, OP-Amp should have either a higher current or a small value of a
capacitor.
PART B
1. Explain the following DC characteristics?
b. Input bias current
c. Input offset current
DC Characteristics:-
An ideal op amp draws no current from the source and its response is also independent of
temperature. However, a real op amp does not work this way. Current is taken form the source
into the op amp inputs. Also the two inputs respond differently to current and voltage due to
mismatch in transistors. A real op amp also shifts its operation with temperature. These non
ideal dc characteristics that add error components to the dc output voltage are:
Input bias current
Input offset current
Input offset voltage
Thermal drift
Input Bias Current:
The op amps input is a differential amplifier, which may be made BJT or FET. In either
case, the input transistors must be biased into their linear region by supplying current into the
bases by the external circuit. In an ideal op amp, we assumed that no current is drawn form the
input terminals. However, practically, input terminals do conduct a small value of dc currents
entering into the inverting and non inverting terminals are shown as IB and IB respectively in
figure (a). Even through both the transistors are identical, IB are not exactly equal due to internal
imbalances between the two inputs. Manufactures specify input bias current IB as the average
value of the base currents entering into the terminals of an op amp.
So,
B B
B
I I
I
2
+
+
=
For 741, a bipolar op amp, the bias current is 500 nA or less. The FET input op amp will
have bias current as low as 50 pA at room temperature.
Consider the basic inverting amplifier of figure (b). If input voltage V1 is set to zero volts.
Instead, we find that the output voltage is offset by,
V0 = (IB) Rf
For a 741 op amp, with a 1 MO feedback resistor
V0 = 500 nA x 1 MO = 500 mV
The output is driven to 500 mV with zero input because of the bias currents. In application
where signal levels are measured in mill volts, this is totally unacceptable. This effect can be
compensated for as shown in figure (C) where a compensation resistor room has been added
between the no inverting input terminal and ground. Current I + B flowing through the
compensating resistor room develop a voltage Vi across it. Then, by KVL we get
-V1 + 0 + V2 V0 = 0
V0 = V2 V1
V0 = (IB) Rf
V0 = 500 nA x 1 MO = 500 mV
-V1 + 0 + V2 V0 = 0
V0 = V2 V1
V0 = (IB) Rf
V0 = 500 nA x 1 MO = 500 mV
-V1 + 0 + V2 V0 = 0
V0 = V2 V1
(C) Bias Current compensation
By selecting proper value of Rcomp, V2 can be cancelled with V1 and the output V0 will be
zero. The value of Rcomp is derived as
1 B comp
+ 1
B
comp
V I R
or
V
I
R
+
=
=
The node a is at voltage (-V1), because the voltage at the no inverting input terminal is (-V1). So,
with Vi = 0 we get
I1 = V1/R1
Also,
I2 = V2/Rf
For compensation, V0 should be zero for V1 = 0, that is, from equation V2=V1
So that, I2 = V1/Rf
KCL at node a gives
, )
'
1 f
1 1
B 2 1 1
f 1 1 f
R R
V V
I I I V
R R R R
+
= + = + =
Assuming, I B = I + B and using equation and we get,
1 B comp
+ 1
B
comp
V I R
or
V
I
R
+
=
=
with Vi = 0 we get
I1 = V1/R1
Also,
I2 = V2/Rf
So that, I2 = V1/Rf
KCL at node a gives
, )
'
1 f
1 1
B 2 1 1
f 1 1 f
R R
V V
I I I V
R R R R
+
= + = + =
1 B comp
+ 1
B
comp
V I R
or
V
I
R
+
=
=
with Vi = 0 we get
I1 = V1/R1
Also,
I2 = V2/Rf
So that, I2 = V1/Rf
KCL at node a gives
, )
'
1 f
1 1
B 2 1 1
f 1 1 f
R R
V V
I I I V
R R R R
+
= + = + =
, )
1 f
1
1
1 f comp
1 f
comp 1 f
1 f
R R
V
V
R R R
RR
R R || R
R R
+
=
+
= =
+
That is to compensate for bias currents, the compensating resistor Rcomp should be equal to
the parallel combination resistors tied to the inverting input terminal.
Input Offset Current:
Bias current compensation will work if both bias currents IB
+
and IB are equal. Since the
input transistors cannot be made identical, there will always be some small difference between IB
+
and IB. This difference is called the offset current IOS and can be written as
B B
ISO I I
+
=
The absolute value sign indicates that there is no way to predict which of the bias currents
will be larger.
Offset current IOS for BJT op amp is 200 nA and that for FET op amp is 10 pA. Even with
bias current compensation, offset current will produce an output voltage when the input voltage
V1 is zero. Referring to figure (c).
, )
t B comp
1
1
1
comp 1
2 B 1 B B
1
0 2 1 1
2 f B comp
comp
B B f B comp
1
V I R
V
and I
R
KCL at node 'a' gives
R
I I I I I
R
Again
V I R V
I R I R
R
I I R I R
R
+
+
+
+
=
=
| |
= =
|
\ .
=
=
=
Substituting equation and after algebraic manipulation
V0 = Rf[IB
IB
+
]
So,
V0 = RfIos
So even with bias current compensation and with the feedback resistor of 1 MO,, a 741 BJT
op amp has an output offset voltage
V0 = 1MO x 200 nA = 200 mV
With a zero input voltage. It can be seen from equation that the effect of offset current can
be minimized by keeping feedback resistance small. Unfortunately to obtain high input
impedance, R1 must be kept large. With R1 large, the feedback resistor Rf must also be high so as
to obtain reasonable gain.
The f feedback network in figure (d) is a good solution. This will allow large feedback
resistance while keeping the resistance to ground (seen by the inverting input) low as shown in
the dotted network. The T network provides a feedback signal as if the network were a single
feedback resistor. By To t conversion
2
t 1 s
f
s
R 2RR
R
R
+
=
To design a T network, first pick
Rt << Rf/2
Then calculate
2
t
s
f t
R
R
R 2R
=
So,
V0 = RfIos
V0 = 1MO x 200 nA = 200 mV
2
t 1 s
f
s
R 2RR
R
R
+
=
Rt << Rf/2
Then calculate
2
t
s
f t
R
R
R 2R
=
So,
V0 = RfIos
V0 = 1MO x 200 nA = 200 mV
2
t 1 s
f
s
R 2RR
R
R
+
=
Rt << Rf/2
Then calculate
2
t
s
f t
R
R
R 2R
=
3. Explain about the following applications?
1. Differentiator
2. Integrator
Differentiator:
One of the simplest of the op amp circuits that contain capacitor is the differentiating
amplifier, or differentiator. As the name suggests, the circuit performs the mathematical
operations of differentiation, that is, the output waveform is the derivative of input waveform. A
differentiator circuit is shown in figure (a).
Analysis:
The node N is at virtual ground potential i.e., uN = 0. The current Ic through the capacitor is,
Ic = C1 d/dt (u1-uN) = C1 dvi/dt
The current if through the feedback resistor is u0/ Rf and there is no current into the op
amp. Therefore the nodal equation at node N is
C1 dvi/dt +u0/Rf = 0
From which we have
u0 = R1C1 d u/dt
Differentiator
Thus, the output voltage u0 is a constant (Rf C1) times the derivate of the input voltage u1
and the circuit is a differentiator. The minus sign indicates a 180 phase shift of the output
waveform u0 with respect to the input signal.
1. Differentiator
2. Integrator
Differentiator:
Analysis:
From which we have
u0 = R1C1 d u/dt
Differentiator
1. Differentiator
2. Integrator
Differentiator:
Analysis:
From which we have
u0 = R1C1 d u/dt
Differentiator
The phasor equivalent of equation is, V0(s) = - R1C1 s Vi(s) where V0 and Vi is the phasor
representation of u0 and ui. In steady state put s = jw. We may now write the magnitude of gain A
of the differentiator as,
0
f 1 f 1
1
V
A j R C R C
V
= = c = c
From equation one can draw the frequency response of the op amp differentiator.
Equation may be rewritten as
a
f
A s
f
=
Where
a
f 1
1
f
2 R C
=
t
At t = fa |A| = 1, i.e. 0 dB, and the gain increases at a rate of +20 dB/decade. Thus at high
frequency, a differentiator may become unstable and break into oscillation. There is one more
problem in the differentiator of figure (a). The input impedance (i.e. 1/cC1) decreases with
increases in frequency, thereby making the circuit sensitive to high frequency noise.
Integrator:
If we interchange the resistor and capacitor of the differentiator of figure (a), we have the
circuit of figure (a) which as we will see, is an integrator. The nodal equation at node N is
u1/R1 + (Cf d u0/dt =0
Or
d V0/dt = -1/R1 Cf ui
0 i
1 f
1
V Vdt
R C
=
}
0
f 1 f 1
1
V
A j R C R C
V
= = c = c
a
f
A s
f
=
Where
a
f 1
1
f
2 R C
=
t
Integrator:
u1/R1 + (Cf d u0/dt =0
Or
0 i
1 f
1
V Vdt
R C
=
}
0
f 1 f 1
1
V
A j R C R C
V
= = c = c
a
f
A s
f
=
Where
a
f 1
1
f
2 R C
=
t
Integrator:
u1/R1 + (Cf d u0/dt =0
Or
0 i
1 f
1
V Vdt
R C
=
}
Integrating both sides, we get
, ) , ) , )
1 1
i
1 f
0 0
1
i
1 f
0
d dt
R C
1
t d t 0
R C
0 0
1
u0 = u
u = u + u
} }
}
Where u0, (0) is the initial output voltage.
The circuit, thus provides an output voltage which is proportional to the time integral of
the input and R1CF is the time constant of the integrator. If may be noted that there is a negative
sign in the output voltage, and therefore, this integrator is also known, as an inverting integrator.
A resistance, Rcomp = R1 is usually connected to the (+) input terminals to minimize the effect of
input bias current.
A simple low pass RC circuit can also work as an integrator when time constant is very
large. This requires very large values of R and C. The components R and C cannot be made
infinitely large because of practical limitations. However, in the op amp integrator of figure a,
by millers theorem, the effective input capacitance becomes Cf (1-A), where AV is the gain of the
op amp. The gain AV is infinite for an ideal op amp, so the effective time constant of the op
amp integrator becomes very large which results in perfect integration.
The operation of the integrator can also be studied in the frequency domain. In phasor
notation, equation can be written as
, ) , )
0 1
1 f
1
V S V s
sR C
=
In steady state, put s = jc and we get
, ) , )
0 1
1 f
1
V j V j
j R C
c = c
c
So, the magnitude of the gain or integrator transfer function is
, )
, )
0
1 1 f 1 f
V j
1 1
A
V j j R C R C
c
= = =
c c c
The frequency response (or Bode plot of this basic integrator is shown in figure (b). The
bode plot is a straight line of slop 6B / octave (or) equivalently 20 dB/decade). The frequency fb
in figure (b) is the frequency at which the gain of the integrator is 0 dB and is given by
1 f
1
b
2 R C
} =
t
It can further be seen from equation that at c = 0 the magnitude of the integrator transfer
function is infinite. At dc, the capacitor Cf behaves as an open circuit and there is no negative
feedback. The op amp thus operates in open loop, resulting in an infinite gain. In practice, of
course, output never becomes infinite, rather the output of the amplifier power supply depending
on the polarity of the input dc signal
As the gain of the integrator decreases with increasing frequency, the integrator circuit does
not have any frequency problem as faced in a differentiator. However, at low frequency such as at
dc (c = 0), the gain becomes infinite (or saturates). The solution to the problem is discussed in the
following.
3. In Figure R1 = 10 K, Rf = 100 K, Vi = 1V. A wad of 25 K is connected to the output
terminal. Calculate
i. I,
ii. V0,
iii. IL and
iv. Total current Io into the output pin
1
11
1
v
x i
R
=
Given that
V1 = 1V
following.
terminal. Calculate
i. I,
ii. V0,
iii. IL and
1
11
1
v
x i
R
=
Given that
V1 = 1V
following.
terminal. Calculate
i. I,
ii. V0,
iii. IL and
1
11
1
v
x i
R
=
Given that
V1 = 1V
R1 = 10 KO
1
1
1
1
V 1V
i 0.1mA
R 10K
i 0.1mA
= = =
O
=
fig.
(ii)
0 f
0 1
1
f
1
1
f
0 1
1
0
R
V V
R
Given that
R 100K
R 10K
V 1V
R 100K
V V 1V 10V
R 10K
V 10V
=
= O
= O
=
O
= = =
O
=
(iii)
0
1
L
0
1
0
L
i
L
V
i
R
Given that
V 10V
R 25K
V 10V
i 0.4mA
R 25K
i 0.4mA
=
=
= O
= = =
O
=
(iv)
I is calculated about is 0.1 mA
Therefore,
Total current i0 = i1 + iL
=0.1mA + 0.4 mA
=0.5mA
In an inverting amplifier for a +ve input output will be ve, therefore the direction of io is as
shown in the above figure.
4. a. In the following circuit for the non inventing amplifier R1 = 1 K and Rf = 10K.
Calculate the maximum output offset voltage due to Vos and IB. The op amp is LM 307 quirt
Vos = 10 mv and IB=300nA, Ios = 50 nA.
b) Calculate the value of Rcomp needed to reduce the effect of IB.
c) Calculate the maximum output voltage if Rcomp as calculated in (b) is connected in the circuit.
Solution:
f
OT OS f B
1
R
V 1 V R I
R
| |
= + +
|
\ .
Given that
, ) , ) , )
f 1
OS
B
OT
OT
R 10K ,R 1K
V 10mA
I 300nA
10K
V 1 10mV 10K 300nA
1K
110mV 3mV
113mV
V 113mV
= O = O
=
=
O | |
= + + O
|
O
\ .
= +
=
=
=0.5mA
Solution:
f
OT OS f B
1
R
V 1 V R I
R
| |
= + +
|
\ .
Given that
, ) , ) , )
f 1
OS
B
OT
OT
R 10K ,R 1K
V 10mA
I 300nA
10K
V 1 10mV 10K 300nA
1K
110mV 3mV
113mV
V 113mV
= O = O
=
=
O | |
= + + O
|
O
\ .
= +
=
=
=0.5mA
Solution:
f
OT OS f B
1
R
V 1 V R I
R
| |
= + +
|
\ .
Given that
, ) , ) , )
f 1
OS
B
OT
OT
R 10K ,R 1K
V 10mA
I 300nA
10K
V 1 10mV 10K 300nA
1K
110mV 3mV
113mV
V 113mV
= O = O
=
=
O | |
= + + O
|
O
\ .
= +
=
=
(b)
The value of Rcomp needed is
comp 1 f
1
f
comp
comp
R R 11R
Given that
R 1K
R 10K
R 1K || 10K
R 990
=
= O
= O
= O O
= O
(c)
With Rcomp in the circuit
, ) , ) , )
f
OT OS f OS
1
OS
OT
R
V 1 V R I
R
Given that I 50nA
10K
1 10mV 10K 50nA
1K
110mV 0.5mV
110.5mV
V 110.5mV
| |
= + +
|
\ .
=
O | |
= + + O
|
O
\ .
= +
=
=
(ii) A non inventing amplifier with a gain of 100 is mulled at 25C. What will happen to the
output voltage if the temperature rises to 50C for an offset voltage drift of 0.15 mV/C
Solution:-
Input offset voltage due to temperature rise = 0.15 mV/
0
C x (50C - 25C) = 3.75 mV. Since
this is an input change, the output voltage will change by
0 OS CL
0
V V bA
3.75mV 100
375mV
V 375mV
=
=
=
=
This could represent a very major shift in the output voltage.
5. Explain about the AC characteristics?
AC Characteristics
We have discussed so far the dc characteristics such as bias current; offset current, offset
voltage and thermal drift. These will affect the steady state (dc) response of the op amp only.
For small signal sinusoidal (ac) applications, one has to know the ac characteristics such as
frequency response and slew rate which will be discussed in this section.
FREQUENCY RESPONSE
Ideally, an op amp should have an infinite bandwidth. This means that, if its open loop
gain is 90 dB with dc signal its gain should remain the same 90 dB through audio and on to high
radio frequencies. The practical op amp gain, however, decreases (rolls off) at higher
frequencies.
Fig. a. Positive Peak Detector
High frequency mod of an OP-amp with single corner frequency
What causes the gain of the op amp to roll off after a certain frequency is reached?
Obviously, there must be a capacitive component in the equivalent circuit of the op amp. This
capacitance is due to the physical characteristics of the device (BJT or FET) used and the internal
construction of op amp. For an op amp with only one break (corner) frequency, all the
capacitor effects can be represented by a single capacitor C as shown in figure (a). This figure
represents the high frequency model of the op amp with a single corner frequency. It may be
observed that the high frequency model of figure (a) is a modified version of the low frequency
model with a capacitor C at the output. There is one pole due to RoC and obviously one 20
dB/decade roll off comes into effect.
The open loop voltage gain of an op amp with only one corner frequency is obtained from
figure (a) as
AC Characteristics
FREQUENCY RESPONSE
frequencies.
figure (a) as
AC Characteristics
FREQUENCY RESPONSE
frequencies.
figure (a) as
, )
, )
, )
, )
c
o OL d
o c
o OL
4 0
OL
1
1
0
jX
V A V 1
R jX
V A
or, A=
V 1 j2 fR C
A
or, A= 2
1+j f/f
1
where f 3
2 R C
=
+ t
=
t
Is the corner frequency of the op amp. The magnitude and the phase angle of the open loop
voltage gain are function of frequency and can be written as
, )
, )
OL
2
1
1
1
A
A 4
f
1
f
f
tan 5
f
=
| |
+
|
\ .
| |
=
|
\ .
The magnitude and phase characteristics from equation (4) and (5) are shown in figure (b,
c). It can be seen that
(i) For frequency f << fb the magnitude of the gain is 20 log AOL in dB.
(ii) At frequency f = fb the gain is 3 dB down from the dc value of AOL in dB. This frequency
f1 is called corner frequency.
(iii) For f>>fb the gain rolls off at the rate of 20 dB / decade or 6 dB/octave.
It can further be seen from the phase characteristics that the phase angle is zero at frequency f =
0. At corner frequency f1 the phase angle is 45 (lagging) and at infinite frequency the phase
angle is 90. This shows that a maximum of 90 phase change can occur in an op amp with a
single capacitor. It may be mentioned here, that zero frequency does not occur in log scale. From
all practical purposes, zero frequency is taken as one decade below the corner frequency and
infinite frequency is one decade above the corner frequency. The voltage transfer function in s
domain can be written as
, ) , )
OL OL
1
OL OL 1
A A
A
1 j f / f 1 j
A . A .
j s
1
1
1 1
= =
+ + c/c
c c
= =
c+ c + c
b) aper loop Magnitude Characteristics
Phase characteristics for ar op-amp
A practical op amp, however, has number of stages and each stage produces a capacitive
component. Thus due to a number of RC pole pairs, there will be a number of different break
frequencies. The transfer function of an op amp with three break frequencies can be assumed as.
6. (a) For the non inverting amplifier of figure (b), R1 = 1 K and Rf = 10 K. Calculate the
maximum output offset voltage due to VOS and IB. The op amp is LM 307 with VOS = 10 mV
and IB = 300 nA, IOS = 50 nA.
(b) Calculate the value of Rcomp= needed to reduce the effect of IB.
(c) Calculate the maximum output offset voltage if Rcomp as calculated in (b) is connected in the
circuit.
Solution:
circuit.
Solution:
circuit.
Solution:
(a)
, ) , ) , )
f
OT OS t B
1
R
V 1 V RI
R
10K
1 10mV 10K 300nA
1K
110mV 3mV 113mV
| |
= + +
|
\ .
O | |
= + + O
|
O
\ .
= + =
(b) The value of Rcomp needed is,
Rcomp = 1 KO||10KO = 990 O
(c) With Rcomp in the circuit,
f
OT OS t OS
1
R
V 1 V RI
R
110mV 0.5mV 110.5mV
| |
= + +
|
\ .
= + =
It can be seen from this example that it is the input offset voltage which is more responsible
for producing an output offset voltage compared to input bias current IB or the input offset current
IOS.
(a)
, ) , ) , )
f
OT OS t B
1
R
V 1 V RI
R
10K
1 10mV 10K 300nA
1K
110mV 3mV 113mV
| |
= + +
|
\ .
O | |
= + + O
|
O
\ .
= + =
Rcomp = 1 KO||10KO = 990 O
f
OT OS t OS
1
R
V 1 V RI
R
110mV 0.5mV 110.5mV
| |
= + +
|
\ .
= + =
IOS.
(a)
, ) , ) , )
f
OT OS t B
1
R
V 1 V RI
R
10K
1 10mV 10K 300nA
1K
110mV 3mV 113mV
| |
= + +
|
\ .
O | |
= + + O
|
O
\ .
= + =
Rcomp = 1 KO||10KO = 990 O
f
OT OS t OS
1
R
V 1 V RI
R
110mV 0.5mV 110.5mV
| |
= + +
|
\ .
= + =
IOS.
UNIT III
APPLICATIONS OF OPAMP
PART A
1. Name the important features of an Instrumentation amplifier?
1. High gain Accuracy
2. High CMRR
3. High gain stability
4. Low dc offset
5. Low O/P impedance
6. Low power loss
7. High output Impedance
2. List the applications of Instrumentation Amplifier?
(a) Temperature Indicator
(b) Temperature controller
(c) water flow meter
(d) Thermal conductivity meter
(e) Analog weight scale.
3. What is meant by comparator?
It is a circuit which compares a signal voltage on one input of an op-amp with a known
voltage called the reference voltage on the other input.
4. The basic step of a9 bit DAC is 10.3mV. If 000000000 represented by oV, what is produced if
file I/P produced if the I/P is 101101110?
The I/P voltage is =10.3MV (1X28+0x2
7
+ 1X2
6
+1X2
5
+0X2
4
+1X2
3
+1X2
2
+1X2
1
+X2
0
) = 3.76V.
5. Calculate the value of LSB, MSB and full scale output for an a bit DAC for the 0 to 15 range?
1 1 1
2 2 52
15V
15V range LSB = 29 .2
51L
1
scale
2
1
= 15 7 .5
2
n a
L S B
f o r
M S B f u l l
V
= = =
=
=
=
& full scale output =(full scale voltage - 1LSB)
6. What is the resolution of a converter?
Resolution (in volts) = 1
2 1
fs
n
V
=
LSB increment Resolution of a converter is the smaller change in

voltage which may be produced the O/P of the converter.
7. What is a Multivibrator?
Multivibrator is a wave shaping circuit which gives symmetric or a symmetric output. It
has two state. They may be either stable or quasi stable depends the type of the Multivibrator
8.What is Schmitt Trigger?
Schmitt Trigger is a regenerative comparator. It converts sinusoidal input into square wave
output. The output of Schmitt trigger swings between upper threshold voltage and lower
threshold voltage, the reference voltages of the input waveform.
9.How many resistors are required in a 12-bit weighed resistor DAC?
For 12 bit DAC the resistor required are 2
0
R, 2
1
R, 2
2
R.2
n
R. The largest resistor is 2048 times the
smallest one for only 12bit DAC
13 resistors are required.
12Connectecd with switches
1 is connected Br feedback resistor.
10. Mention the Barkhauses criterion for oscillation?
Magnitude condition
v
A 1 =
Phase condition
v
A 1 Z =
When Av =Amplifier gain
= feed back gain
PART B
1. Discuss about clipper & clamper circuits?
CLIPPER
A precision diode may also be used to clip-off a certain portion of the input signal to obtain, a
desired output waveform.
Fig (a) Shows a positive clipper. The clipping level is determined by the reference voltage Vref
and could be obtained from the positive supply voltage V+. the input and output waveform are
shown in fig. (b). It can be seen that the portion of the output voltage for u0> Vref are clipped of
(a) Positive clipper circuit
For input voltage u1 < Vref, diode D conducts. The op-amp works as a voltage follower and
output u0 follows input u1 till u1sVref. When ui is greater than V ref, the output u0A of the op-amp
is large enough of drive D into cut-off. The op-amp operates in the open-loop and output voltage
u0 =Vref. However, if Vref is made negative, then the entire output waveform above Vref will get
clipped off as shown in figure.
The positive clipper of fig. (a) can be easily converted into a negative clipper by simply
reversing diode D and changing the polarity of the reference voltage Vref as shown in fig (a). The
negative clipper clips off the negative parts of the input signal below the reference voltage. The
circuit diagram of a negative clipper and the expected waveform for negative Vref and positive Vref
are shown in fig (b and c).
PART B
CLIPPER
PART B
CLIPPER
(b)
CLAMPER:-
The clamper is also known as ac inserter or restorer. The circuit is used to add a desired de level
to the output voltage. In other words, the output is clamped to a desired dc level. If the clamped
de level is positive, it is called positive clamper. Similarly if the clamped dc level is negative, the
clamper is called negative clamper.
Fig (a) shows a clamper with a variable positive dc voltage applied at the (+) input terminal.
This circuit clamps the peaks of the input waveform and therefore is also called a peak clamper.
The output voltage in the circuit is the net result of ac and dc input voltages applied to the (-) and
(+) input terminals respectively. Let us first see the effect of Vref the voltage u is also positive, so
that the diode D is forward biased. The circuit operates as a voltage follower and therefore output
voltage u0 = +Vref.
Now consider the ac input signal ui = Vm sin ct applied at the (-) input terminal. During the
negative half cycle of ui, does D conducts. The capacitor C1 charges through diode D to the
negative peak voltage Vm. since this voltage Vm is in series with the ac input signal, the output
voltage now will be ui + Vm. The total output voltage is
(b)
CLAMPER:-
voltage u0 = +Vref.
(b)
CLAMPER:-
voltage u0 = +Vref.
(a) Peak clamper circuit
Vref +ui +Vm. the input and output waveforms are shown in fig(b). it is possible to obtain negative
peak clamping by reversing the diode D and using a negative reference voltage Vref. The
expected waveform are shown in fig. (c).
2. Discuss the following generators?
a) Triangular Wave Generator b) Sine Wave Generator.
A triangular wave can be simply obtained by integrating a square wave a shown in fig. (a). It is
obvious that the frequency of the square wave and triangular wave is the same as shown in fig
(a). It is obvious that the frequency of the square wave and triangular wave is the same as shown
in fig (b). Although the amplitude of the square wave is constant at Vsat the amplitude of the
triangular wave will decrease as the frequency increases. This is because the reactance of the
capacitor C2 in the feedback circuit decreases at high frequencies. A resistance R4 is connected
across C2 to avoid the saturation problem at low frequencies as in the case of practical integrator.
(a) Triangular waveform generator (b) output waveform
Another triangular wave generator using lesser number of components is shown in fig(a). It
basically consists of a two level comparator followed by an integrator. The output of the
comparator A1 is a square wave of amplitude Vsat and is applied to (-) input terminal of the
integrator A2 producing a triangular wave. This triangular wave is fed back as input to the
comparator A1 through a voltage divider R2R3.
Initially, let us consider that the output of comparator A1 is at Vsat. The output of the
integrator A2 will be a negative going ramp as shown in fig (b). Thus one end of the voltage
divider R2R3 is at a voltage + Vsat. and the other at the negative going ramp of A2. At a time t = t1,
when the negative going ramp attains a value of -Vramp the effective voltage at point P becomes
slightly less than OV.
(a) Triangular waveform generator (b) waveforms
This switches the output of A1 from positive saturation to negative saturation level - Vsat.
During the time when the output of A1 is at Vsat the output of A2 increases in the positive
direction. And at the instant t = t2, the voltage at point P becomes just above thereby switching the
output of A1 from - Vsat to +Vsat. The cycle repeats and generates a triangular waveform. It can be
seen that the frequency of the square wave and triangular wave will be the same. However, the
amplitude of the triangular wave depends upon the RC value of the integrator A2 and the output
voltage level of A1 the output voltage of A1 can be set to desired level by using appropriate zener
diodes. The frequency of the triangular waveform can be calculated as follows.
The effective voltage at point P during the time when output of A1 is at +Vsat level given by,
2
2 3
[ ( )]
amp sat ramp
R
V V V
R R
+ +
+
At t = t1, the voltage at point p becomes equal to zero. Therefore from eq.
-Vramp = -R2 / R3 (+Vsat)
Similarly, at t = t2, when the output of A1
Switches from-Vsat to +Vsat
Vramp = -R2 /R3 (-Vsat)
2
2 3
[ ( )]
amp sat ramp
R
V V V
R R
+ +
+
2
2 3
[ ( )]
amp sat ramp
R
V V V
R R
+ +
+
=R2 /R3 (-Vsat)
Therefore, peak to peak amplitude of the triangular wave is
/ 2
1 1 0
1 1( / 2)
0
1 1
( 0 1/ )
1
0( ) ( )
/ ( )
( )
2
i
T
sat
sat T
sat
u RC V dt
U PP V
RC
V RC or
U PP
T RC
V
=
=
=
=
}
}
Putting the value of U0 (PP) from Eq. 5.21, we get
1 1 2
3
0
3
0
1 1 2
4
the frequency of oscillation f is,
f 1/
4
RC R
T
R
Hence
R
T
RC R
=
= =
Sine Wave Generators:
As oscillator is basically a feedback circuit where a fraction uf of the output voltage V0 of an
amplifier is fed back to the input in the same phase. The block diagram of an oscillator is shown in
figure a
For sustained oscillation, AvB =1. That is, magnitude condition |AvB| =1. and the phase
condition, AvB =0 or 360 must be simultaneously satisfied in the circuit.
There are different types of sine-wave oscillators available according to the range of frequency,
namely RC oscillators for audio frequency and LC oscillators for radio frequency range. Here we
will discuss only two types of audio frequency RC oscillators.
=R2 /R3 (-Vsat)
/ 2
1 1 0
1 1( / 2)
0
1 1
( 0 1/ )
1
0( ) ( )
/ ( )
( )
2
i
T
sat
sat T
sat
u RC V dt
U PP V
RC
V RC or
U PP
T RC
V
=
=
=
=
}
}
1 1 2
3
0
3
0
1 1 2
4
f 1/
4
RC R
T
R
Hence
R
T
RC R
=
= =
figure a
=R2 /R3 (-Vsat)
/ 2
1 1 0
1 1( / 2)
0
1 1
( 0 1/ )
1
0( ) ( )
/ ( )
( )
2
i
T
sat
sat T
sat
u RC V dt
U PP V
RC
V RC or
U PP
T RC
V
=
=
=
=
}
}
1 1 2
3
0
3
0
1 1 2
4
f 1/
4
RC R
T
R
Hence
R
T
RC R
=
= =
figure a
3. Explain the square wave generator.
(or)
Explain the Astable multivibrator.
A simple if-amp square wave generator is shown in figure.
Simple OP-Amp Square Wave generators
A square wave generator is also called free running oscillator. The principle of generation of
square wave output is to force an op-amp to operate in the saturation region. In fig fraction |= R2
/(R1+R2) of the output is feedback to the (+) input terminal. Thus the reference voltage Vref is |V0.
the output is also fed back to the (-) input terminal. Whenever input at the (-) input terminal just
exceeds Vref, switching takes place resulting in a square wave output.
Consider an instant of time when the output is at +Vsat. The capacitor now starts charging
towards input terminal becomes just greater than this reference this voltage, the output terminal
becomes just greater than this reference voltage, the output terminal becomes just greater than this
reference voltage, the output is driven to -Vsat. At this resistant the voltage in the capacitor is
+|Vsat. It begins to discharge through R, that is charged towards capacitor charges more and
more negatively until its voltage just exceeds -|Vsat. The output switches back to +Vsat. The cycle
repeats itself as shown in fig below
(or)
(or)
The frequency is determined by the time it takes the capacitor to charge from -|Vsat to +|Vsat and
vice versa. The voltage across the capacitor as a function of time is give by
Vc(t) = Vf + (vi vf)e
-t/ec
---------------------(1)
Where, the final value
Vf = + Vsat
And the initial value
Vi = ---------------- |Vsat
Therefore,
Vc(t) = Vsar + (|Vsat Vsat)e
-t/RC
Vc(t) = Vsat Vsat (1+|)e
-t/RC
-------------- (2)
At t = T1
Vc(T1) = |Vsat = Vsat Vsat (1 + |)e
-T1/RC
--------- (3)
After algebraic manipulation, we get
1
1+
, In
1-
T R

= ----------------- (4)
and the output wave form is symmetrical
5. Explain about weightier resistor DAC and R-2R ladder DAC win required diagram ?
weightier resistor DAC:
-t/ec
---------------------(1)
Vf = + Vsat
Vi = ---------------- |Vsat
Therefore,
-t/RC
-t/RC
-------------- (2)
At t = T1
-T1/RC
--------- (3)
1
1+
, In
1-
T R

= ----------------- (4)
-t/ec
---------------------(1)
Vf = + Vsat
Vi = ---------------- |Vsat
Therefore,
-t/RC
-t/RC
-------------- (2)
At t = T1
-T1/RC
--------- (3)
1
1+
, In
1-
T R

= ----------------- (4)
One of the simplest circuits showed in Figure uses a summing amplifier with a binary weighted
resistor network. It has n-electronic switches d1, d2 .. dn controlled by binary input to a particular
switch is 1, it connects the resistance to the reference voltage (VR). and if the input bit is 0, the
switch connects the resistor to the ground. From figure the output current 10 for an ideal co-amp
can be written as
I0 = I1 + I2 + .. + In
2
1 2 ..... 2
2 2 2
R R R
n
V V V
d d n
R R R
= + + +
= VR / R (d12
-1
+ d22
-2
+ .. + dn2
-n
The output voltage
Vo = IoRf = VRRf/R(d12
-1
+ d22
-1
+ d22
-2
+ .dn2
-n
Comparing equation (10.1) with equation (10.2) it can be seen that if Rf = R that K = 1 and
VFS = VR
The circuit shown in figure uses a negative reference voltage. The analog output
voltage is therefore positive staircase shown figure for a 3-bit weighted resistor DAC. It may be
noted that
(a) A simple weighted resistor DAC (b) Transfer characteristics of a 3-bit DAC
a) A simple weighted resistor DAC
b) Transfer characteristics of a 3-bit DAC
a. Although the co-amp in figure is connected in inverting mode, it can also be connected in
non inverting mode.
b. The op-amp is simply working as a current to voltage converter.
c. The polarity of the reference voltage is chose in example. For TTL compatible switches, the
reference voltage should be + 5v and the output, will be negative.
The accuracy and stability of a DAC depends upon the accuracy of the resistor and the tracking
of each other with temperature. There are however a number of problems associated with this
type of DAC. One of the disadvantage of binary weighted typed DAC is the observed that for
non inverting mode.
non inverting mode.
better resolution, the input binary word length has to be increased.
Thus, as the number of bit increases, the rang of resistance value increases. For 8-bit DAC, the
resistors required are 2
0
R, 2
1
R, 2
2
R, 2
7
R, the largest resistor is 128 times the smallest one for only 8-
bit MOif the smallest is 2.5 kO, the practical. Also the voltage drop across such a large resistor due
to the bias current would also affect the accuracy. The choice of smallest resistor value as 2.5 kO is
reasonable; otherwise loading effect will be there. The difficult of achieving and maintaining
accurate ratios over such a wide range especially in monolithic form restricts the use of weighted
resistor DACs to bellow 8-bit.
R-2R ladder DAC :
Wide range of resistors are required in binary weighted resistor type DAC. They can be
avoided by using R-2R ladder type DAC where only in two values of resistors are required. It is
well suited for integrated circuit realization. The typical values of R ranges from 2.5 kO to 10 kO.
For simplicity consider a 3-bit DAC as shown in figure, where the switch position d2, d2, d3
corresponds to the binary word 100. The circuit can be simplified to be simplified to the equivalent
from of figure easily calculated by the set procedures of network analysis are
, ) 2/ 3
2 2/ 3 4
R
R
V R
V
R R
=
+
0
R, 2
1
R, 2
2
R, 2
7
R-2R ladder DAC :
, ) 2/ 3
2 2/ 3 4
R
R
V R
V
R R
=
+
0
R, 2
1
R, 2
2
R, 2
7
R-2R ladder DAC :
, ) 2/ 3
2 2/ 3 4
R
R
V R
V
R R
=
+
R-2R ladder DAC (b) Equivalent circuit of (a), (c) Equivalent circuit of (b)
(a) R 2R ladder DAC.
(b) Equivalent circuit of (a) (c) Equivalent
The output voltage
Vo = -2R/R(-VR/16) = VR/2 = VFS / 8
The switch position corresponding to the binary word 001 in 3 bit DAC in
figure the voltage at the nodes (A, B, C) formed by resistor branches easily calculated in a similar
fashion and the output voltages becomes.
Vo = -2R/R(-VR/16) = VR/2 = VFS / 8
The output voltage
Vo = -2R/R(-VR/16) = VR/2 = VFS / 8
Vo = -2R/R(-VR/16) = VR/2 = VFS / 8
The output voltage
Vo = -2R/R(-VR/16) = VR/2 = VFS / 8
Vo = -2R/R(-VR/16) = VR/2 = VFS / 8
(a) R-2R ladder DAC for switch positions 001 (b) Equivalent circuit
In a similar fashion, the output voltage for R-2R ladder type DAC corresponding to other 3-bit
binary words can be calculated.
Explain the following Flash type, successive Approximation and dual slope ADC:
6. converter ADCs ?
Flash type:
The parallel comparator (Flash) A/D converter:
This is the simplest possible A/D converter. It is at the same time, the fastest and most
expensive technique. Figure shows a 3-bit A/D converter.
(a) Basic circuit of a flash type A/D converter
The circuit consists of a resistive divider network, 8 op-amp comparator and its truth table
is shown in figure. A small amount of hysteresis is built into the comparator to resolve any
problems that might if both inputs were of equal voltage as shown in the truth table.
6. converter ADCs ?
Flash type:
6. converter ADCs ?
Flash type:
Fig.
Voltage input Logic output X
Va > Vd X = 1
Va > Vd X= 0
Va > Vd Previous value
Voltage input Logic output
X
Va > Vd X = 1
Va > Vd X= 0
Comparator and its Truth Table
Input Voltage
Va
X7 X6 X5 X4 X3 X2 X1 X0 Y2 Y1 Y0
0 to VR/4 0 0 0 0 0 0 0 1 0 0 0
VR/8 to VR/4 0 0 0 0 0 0 1 1 0 0 1
VR/4 to 3 VR/8 0 0 0 0 0 1 1 1 0 1 0
3 VR/8 to VR/2 0 0 0 0 1 1 1 1 0 1 1
VR/8 to 5 VR/8 0 0 0 1 1 1 1 1 1 0 0
5 VR/8 to 3 VR/4 0 0 1 1 1 1 1 1 1 0 1
3 VR/4 to 7VR/8 0 1 1 1 1 1 1 1 1 1 0
7VR/8 to VR 1 1 1 1 1 1 1 1 1 1 1
Coming back to figure, at each node of the resistive divider, a comparison voltage is
available. Since all the resistors are of equal value, the voltage levels available at the nodes are
equally divided between the reference voltage VR and the ground. The purpose of the circuit is to
compare that analog input voltage Va with each of the node voltages. The truth table for the flash
type AD converter is shown in Figure. The circuit has the advantage of high speed as the
conversion take place simultaneously rather that sequentially. Typical conversion time is 100 nos
or less. Conversion time is limited only by the speed of the comparator and of the priority
encoder. By using an Advanced Micro Devices AMD 686A Comparator and a T1147 priority
encoder, conversion delays of the order of 20 nos can be obtained.
The type of ADC has the disadvantage that the number of comparators required almost
doubles for each added bit. A2-bit ADC required 3 comparators, 3 bit ADC needs 7, whereas 4bit
requires 15 comparators. In general, the number of comparators required are 2
n
-1 when n is the
desired number of bits. Hence the number of comparators approximately doubles for each added
Fig.
Va > Vd X = 1
Va > Vd X= 0
X
Va > Vd X = 1
Va > Vd X= 0
Input Voltage
Va
X7 X6 X5 X4 X3 X2 X1 X0 Y2 Y1 Y0
0 to VR/4 0 0 0 0 0 0 0 1 0 0 0
VR/8 to VR/4 0 0 0 0 0 0 1 1 0 0 1
VR/4 to 3 VR/8 0 0 0 0 0 1 1 1 0 1 0
3 VR/8 to VR/2 0 0 0 0 1 1 1 1 0 1 1
VR/8 to 5 VR/8 0 0 0 1 1 1 1 1 1 0 0
5 VR/8 to 3 VR/4 0 0 1 1 1 1 1 1 1 0 1
3 VR/4 to 7VR/8 0 1 1 1 1 1 1 1 1 1 0
7VR/8 to VR 1 1 1 1 1 1 1 1 1 1 1
n
-1 when n is the
Fig.
Va > Vd X = 1
Va > Vd X= 0
X
Va > Vd X = 1
Va > Vd X= 0
Input Voltage
Va
X7 X6 X5 X4 X3 X2 X1 X0 Y2 Y1 Y0
0 to VR/4 0 0 0 0 0 0 0 1 0 0 0
VR/8 to VR/4 0 0 0 0 0 0 1 1 0 0 1
VR/4 to 3 VR/8 0 0 0 0 0 1 1 1 0 1 0
3 VR/8 to VR/2 0 0 0 0 1 1 1 1 0 1 1
VR/8 to 5 VR/8 0 0 0 1 1 1 1 1 1 0 0
5 VR/8 to 3 VR/4 0 0 1 1 1 1 1 1 1 0 1
3 VR/4 to 7VR/8 0 1 1 1 1 1 1 1 1 1 0
7VR/8 to VR 1 1 1 1 1 1 1 1 1 1 1
n
-1 when n is the
bit. Also the larger the value of n, the more complex is the priority encoder.
Successive Approximation Converter:
The successive approximation technique uses a very efficient code search strategy to
complete n-bit conversion in just n-clock periods. An eight bit converter would require eight clock
pulses to obtain a digital output. Figure shows an eight bit converter.
The circuit uses a successive approximation register (SAR) to find the required value of
each bit by trial and error. The circuit operates as follows. With the arrival of the START
command, the SAR sets the MSB=d1 = 1 with all other bits to zero so that the trial code is 10000000.
The output Vd of the DAC is now compared with analog input Va. If Va is greater than the DAC
output Vd then 10000000 is less than the correct digital representation. The MSB is left at 1 and
the next lower significant bit is made 1 and further tested.
However, if Va is less than the DAC output, then 10000000 is greater than the correct digital
representation. So reset MSB to 0 and go on to the next lower significant bit. This procedure is
repeated for all subsequent bits, one at a time, until all bit positions have been tested. Whenever
the DAC output crosses Va the comparator changes state and this can be taken as the end of
conversion (EOC) command.
A tracking A/D converter (b) Wave forms associated with a tracking A/D converter
Functional diagram of the successive approximation ADC
Figure shows a typical conversion sequence and Figure shows the associated waveforms. It can
be seen that the D/A output voltage becomes successively closer to the actual input voltage. It
requires eight pulses to establish the accurate output regardless of the value of the analog input.
However, one additional clock pulse is used to load the output register and reinitialize the circuit.
Successive approximation conversion sequence for a typical analog I/P
Correct digital
representation
Successive approximation
register o/p
Comparator
output
11010100
10000000
11000000
1
1
Correct digital
representation
register o/p
Comparator
output
11010100
10000000
11000000
1
1
Correct digital
representation
register o/p
Comparator
output
11010100
10000000
11000000
1
1
11100000
11010000
11011000
11010100
11010110
11010101
11010100
0
1
0
1
0
0
A comparison of the speed of an eight bit tracking ADC and an eight bit successive
approximation ADC is made in Figure C. Given the same clock frequency, we see that the tracking
circuit is faster only for small changes in the input. In general, the successive approximation
technique is more versatile and superior to all other circuits discussed so far.
Successive approximation ADCs are available as self contained ICs. The AD 7592 (Analog
Devices Co) a 28-pin dual in line CMOS package is a 12-bit A/D converter using successive
approximation technique.
Integrating Type of ADCs:
The integrating type of ADCs does not require a S/H circuit at the input. If the input
changes during conversion, input averaged over the integration period.
Charge Balancing ADC:
The principle of charge balancing ADC is to first, convert the input signal to a frequency
using a voltage to frequency (V/F) converter. This frequency is then measured by the counter and
converted to an output code proportional to the analog input. The main advantage of these
converters is that it is possible to transmit frequency even in noisy environment or in isolated
form. However, the limitation of the circuit is that one output of V/F converter depends upon an
RC product whose value cannot be easily maintained with temperature and time. The draw back
of the charge balancing ADC is eliminated by the dual slope conversion.
Dual slope ADC:
Figure shows the functional diagram of the dual-slope or dual-ramp converter. The analog
part of the circuit consists of a high input impedance buffer A1, precision integrator A2 and a
voltage comparator. The converter first integrates the analog input signal Va for a fixed duration
of 2n clock periods as shown in figure. Then it integrates an internal reference voltage VR of
opposite polarity until the integrator output is zero is proportional to the value of Va averaged
over the integration period. Hence N represents the desired output code. The circuit operates as
follows:
Before the START command arrives, the switch SW1 is connected to ground and SW2 us
closed. Any offset voltage present in the A1, A2, comparator loop after integration, appears across
the capacitor AZ till the threshold of the comparator is achieved. The capacitor CAZ thus provides
automatic compensation for the input-offset voltages of all the three amplifiers. Later, when Sw2
opens, CAZ acts as a memory to hold the voltage required to keep the offset nulled. AT the arrival
of the START command at t=t1, the control logic opens SW2 and connects SW2 and connects SW1 to
Va and enables the counter staring from zero. The circuit uses an n-stage ripple counter and
therefore for counter resets to zero after counting 2
n
pulses. The analog voltage Va integrated for a
fixed number 2
n
counts of clock pulses after which the counter resets to zero. If the clock period is
T, the integration takes place for a time T1 = 2
n
x T and the output is a ramp going downwards as
shown in Figure.
n
fixed number 2
n
n
shown in Figure.
n
fixed number 2
n
n
shown in Figure.
The counter resets itself to zero at the end of the interval T1 and the switch SW1 is connected
to the reference voltage (-VR). The output voltage Vo will now have a positive slope. As long as Vo
is negative, the output of the comparator is positive and the control logic allows the clock pulse to
be counted. However, when v0 becomes just zero at time t = t3, the control logic issues and end of
conversion (EOC) command and no further clock pulses enter the counter. It can be shown that
the reading of the counter at t3 is proportional to the analog input voltage Va.
n
1 2 1
2 counts
T t t
Clock rate
= =
And
3 2
Digital count N
t t
Clcok rate
=
For an integrator,
Av0 = (-1/RC) V (At)
The voltage vo will be equal to v1 at the instant t2 and can be written as
V1 = (-1/F) Va (t2 t1)
The voltage v1 is also given by
V1 = (-1/RC)(-VR) (t2 t3)
So,
Va (t2 t1) = VR (t3 t2)
Putting the values of (t2 t1) = 2n and (t3 t2) = N, we get
Va (2
n
) = (VR) N
Or, Va = (VR) (N/2
n
)
7. Explain about Instrumentation Amplifier?
Instrumentation Amplifier
In a number of industrial and consumer applications, one is required to measure and control
physical quantities. Some typical examples are measurement and control of temperature,
humidity, light intensity, water flow etc. These physical quantities are usually measured with the
help of transducers. The output of transducer has to be amplified so that it can drive the indicator
or display system. This function is performed by an instrumentation amplifier. The important
features of an instrumentation amplifier are:
i) High gain accuracy
ii) High CMRR
iii) High gain stability with low temperature coefficient
iv) Low dc offset
v) Low output impedance
There are specially designed op-amps such as A725 to meet the above stated requirements of a
good instrumentation amplifier are also available commercially such as AD521, AD524, AD624 by
Analog Devices, LH0036, LH0037 by National semiconductor and INA104, 3626, 3629 by Burr-
Brown.
Consider the basic differential amplifier shown in fig (a). It can be easily seen that the output
voltage V0 is given by,
2 2
0 2 1
3
1 1
4
1
1
R R
V V V
R
R R
R
| |
= + +
|
\ .
ii) High CMRR
iv) Low dc offset
Brown.
2 2
0 2 1
3
1 1
4
1
1
R R
V V V
R
R R
R
| |
= + +
|
\ .
ii) High CMRR
iv) Low dc offset
Brown.
2 2
0 2 1
3
1 1
4
1
1
R R
V V V
R
R R
R
| |
= + +
|
\ .
a) Differential amplifier using single op-amp (b) An improved instrumentation amplifier (c)
Instrumentation amplifier using transducer bridge
2 1
0 2 1
3
1 2
4
1
, V 1
1
R R
or V V
R
R R
R
1
(
| |
( = +
|
(
\ .
+
(
]
for R1 /R2=R3/R4, we obtain
1
1 2
2
( ' ')
R
V V
R
=
Since, no current flows into op-amp, the current i flowing (upwards) in R is I = (V1 V2) /R and
passes through the resistor R.
'
1 1 1 2 2
'
2 2 1 2 2
'
' ( )
'
' ( )
R
V R I V V V V
R
R
and V R I V V V V
R
= + = +
= + = +
Putting the values of V1 and V2 =in Eq we obtain,
2
1
2
0 1 2
1
2 '
( 1 2) ( 1 2)
2 '
, V 1 ( )
o
R R
V V V V V
R R
R R
or V V
R R
1
= +
(
]
| |
= +
|
\ .
The difference gain of this instrumentation amplifier can be varied by using a variable resistance
R.
2 1
0 2 1
3
1 2
4
1
, V 1
1
R R
or V V
R
R R
R
1
(
| |
( = +
|
(
\ .
+
(
]
1
1 2
2
( ' ')
R
V V
R
=
'
1 1 1 2 2
'
2 2 1 2 2
'
' ( )
'
' ( )
R
V R I V V V V
R
R
and V R I V V V V
R
= + = +
= + = +
2
1
2
0 1 2
1
2 '
( 1 2) ( 1 2)
2 '
, V 1 ( )
o
R R
V V V V V
R R
R R
or V V
R R
1
= +
(
]
| |
= +
|
\ .
R.
2 1
0 2 1
3
1 2
4
1
, V 1
1
R R
or V V
R
R R
R
1
(
| |
( = +
|
(
\ .
+
(
]
1
1 2
2
( ' ')
R
V V
R
=
'
1 1 1 2 2
'
2 2 1 2 2
'
' ( )
'
' ( )
R
V R I V V V V
R
R
and V R I V V V V
R
= + = +
= + = +
2
1
2
0 1 2
1
2 '
( 1 2) ( 1 2)
2 '
, V 1 ( )
o
R R
V V V V V
R R
R R
or V V
R R
1
= +
(
]
| |
= +
|
\ .
R.
UNIT IV
SPECIAL ICs
PART A
1. Draw as astable Multivibrator using a timer IC.
2. What is 555 timer?
555 timer is a highly stable device for generating accurate time delay or oscillation. It can
provide time delay ranging from micro seconds to hours whereas counter timer can have a
maximum timing range or days.
3. Give the Pin diagram of 555 timer.
4. What is free running frequency?
The VCO is a free running multivibrator and operates at a set frequency fo. This frequency
UNIT IV
SPECIAL ICs
PART A
UNIT IV
SPECIAL ICs
PART A
is determined by an external timing capacitor and an external resistor.
5. Give the functional block diagram of PLL.
6. What is Lock-in Range?
The range of frequencies over which the PLL can maintain lock with the incoming signal is
called the lock-in range or tracking range.
7. Give the Block diagram of VCO.
8. What are the main blocks of a PLL?
(a) Phase comparator
(b) Low pass filter.
(c) Error Amplifier
(d) Voltage controlled oscillator
9. Draw the Schematic symbol of Multiplier?.
10. Name the few applications of Analog multiplier.
1. Frequency doubling, frequency shifting, phase angle detection, real power computation,
multiplying
2. Signals, dividing & Squaring of signals.
PART B
1. Discuss about PLL and Derive Capture range also explain PLL Application:
The basic schematic of the PLL is shown in figure (a). This feedback system consist of
a) Phase detector / comparator
b) A low pass filter
c) An error amplifier
d) A voltage controlled Oscillator (VCO)
The VCO is a free running multivibrator and operates at a set frequency f0 called free
running frequency. This frequency is determined by an external timing capacitor and an external
resistor. It can also be shifted to either side by applying a dc control voltage uc to an appropriate
terminal of the IC. The frequency deviation is directly proportional to the dc control voltage and
hence it is called a Voltage Control Oscillator or, in short, VCO.
If an input signal os of frequency fs is applied to the PLL, the phase detector compares the
phase and frequency of the incoming signal to that of the output Vs of the VCO. If the two signals
differ in frequency and/or phase, an error voltage Ve is generated. The phase detector is basically a
multiplier and produces the sum (fs + Fo) and difference (fs fo) components at its output. The high
(c) Error Amplifier
multiplying
PART B
(c) Error Amplifier
multiplying
PART B
frequency component (fs + fo) is removed by the low pass filter and the difference frequency
component is an amplified and then applied as control voltage V0 to VCO.
Blocl schematic of the PLL
The signal Vc shifts the VCO frequency in a direction a reduce the frequency difference
between fs and fo. Once this action starts, we say that the signal is in the capture range. The VCO
continues to change frequency till its output frequency is exactly the same as the input signal
frequency. The circuit is then said to be locked. Once locked, the output frequency fo of VCO
identical to fs except for a finite phase difference . This phase difference generate a corrective
control voltage Vc to shift the VCO frequency from fo to fs and thereby maintain the lock. Once
locked, PLL tracks the frequency changes of the input signal. Thus, a PLL goes through three
stages (i) free running (ii) capture and (iii) locked or tracking.
Figure b shows the capture transient. As capture starts a small sine wave appears. This is
due to the difference frequency between the VCO and the input signal. The dc component of the
beat drives the VCO and the input signal. The dc components of the beat drives the VCO towards
the lock. Each successive cycle causes the VCO frequency to move closer to the input signal
frequency. The difference in frequency becomes smaller and a large dc component is passed by the
filter, shifting the VCO frequency further. The process continues until the VCO locks on to the
signal and the difference frequency is dc.
The low pass filter controls the capture range if VCO frequency is far away, the bear
frequency will be too high to pass through the filter and the PLL will not respond. We say that the
signal is out of the capture band. However, once locked, the filter no longer restricts the PLL will
not respond. WE say that the signal is about of the capture band. However, once locked, the filter
no longer restricts the PLL. The VCO can track the signal well beyond the capture band. Thus
tracking range is always larger than the capture range.
Some of the important definitions in relation to PLL are:
Lock in Range:
Once the PLL is locked, it can track frequency changes in the incoming signals. The range of
frequency over which the PLL can maintain lock with the incoming signal is called the lock in
range or tracking range. The lock range is usually expressed as percentage of fo, the VCO
frequency.
Capture Range:
The range of frequencies over which the PLL can acquire lock with an input signal is called
the capture range. This parameter is also expressed as percentage of fo.
Pull-in time:
The total time taken by the PLL to establish lock is called pull in time. This depends on the
initial phase and frequency difference between the two signals as well as on the overall loop gain
and loop filter characteristics.
Derivation of Capture range:
When PLL is not initially locked to the signal, the frequency of the VCO will be free running
frequency fo. The phase angle difference between the signal and the VCO output voltage will be,
= (cs t + us) (co t + uo) = (cs -co) t + Au (9.30)
Thus the phase angle difference does not remain constant but will change with time at a rate given
by
s o
d

dt
= .. (9.31)
The phase detector output voltage will therefore not have a dc component but will produce an ac
voltage with a triangular waveform of peak amplitude K
(t/2) and a fundamental frequency (fs

fo) = Af.
T (jf) =
1
1
1+j(f/f )
(9.32)
Where f1 = 1/2 t RC is the 3 dB point of LPF. In the slope portion of LPF (f/f1)
2
>> 1, then
T (f) =
1
f
jf
.. (9.33)
The fundamental frequency term supplied to the LPF by the phase detector will be the difference
frequency Af = fs fo. If Af > 3f1, the LPF transfer function will be approximately,
T (Af) =f1) Af = f1/ (fs fo) .. (9.34)
The voltage vc to drive the VCO is,
vc = vc T (f) A . (9.35)
Or, vc (max) = vc (max) T (f) A
= K
(t/2) A (f1/Af) (from Eq 9.24) .. (9.37)

Then the corresponding value of the maximum VCO frequency shift is,
(f fo) max = K
v
vc (max) = K
v
vc (max) = K
v
K
(t/2) A (f1/Af) (9.37)

For the acquisition of signal frequency, we should put f = fs so that the maximum signal frequency
range that can be acquired by PLL is,
(fs fo) max = K
v
K
(t/2) A (f1/Afc) . (9.38)

Now, Afc = (fs fo) max
So, (Afc)
2
= k
v
K
(t/2) Af1 (from Eq (9.38)

Since, AfL = K
v
K
(t/2) A
We get, (Afc) =
1 L
f f A ..... (9.39)
Therefore, the total capture range is,
2Afc = 2
1 L
f f A .. (9.40)
Where the lock in range = 2AfL = K
v
K
A t. In case of IC PLL 565, R = 3.6 kO, so the capture

range is
1
2
L
3
f
2(3.6 10 ) C
1 A
]
. (9.41)
Where C is in farads
The capture range is symmetrically located with respect to VCO free running frequency fo as is
shown in fig 9.11. The PLL cannot acquire a signal outside the capture range, but once captured, it
will hold on till the signal frequency goes beyond the lock in range. In order to increase the
ability of lock in range, large capture range in required. However, a large capture range will
make the PLL more susceptible to noise and undesirable signal. Hence a suitable compromise is
often reached between these two opposing requirements of the capture range. Many a times the
LPF band width is first set for a large value for initial acquisition of signal, then once the signal is
captured, the band width of LPF is reduced substantially. This will minimize the interference of
undersirable signals and noise.
PLL Lock in range and Capture range
PLL applications
The output from a PLL system can be obtained either as the voltage signal vc (t) corresponding
to the error voltage in the feedback loop, or as a frequency signal at VCO output terminal. The
voltage output is used in frequency discriminator application whereas the frequency output is
used in signal conditioning, frequency synthesis or clock recovery applications.
Consider the case of voltage output, when PLL is locked to an input frequency, the error
voltage vc (t) is proportional to (fs fo). If the input frequency is varied as in the case of FM signal,
vc will also vary in order to maintain the lock. Thus the voltage output serves as a frequency
discriminator which converts the input frequency changes to voltage changes.
1
2
L
3
f
2(3.6 10 ) C
1 A
]
. (9.41)
PLL applications
1
2
L
3
f
2(3.6 10 ) C
1 A
]
. (9.41)
PLL applications
In the case of frequency output, if the input signal is comprised of many frequency
components corrupted with noise and other disturbances, the PLL can be made to lock, selectively
on one particular frequency component at the input. The output of VCO would then regenerate
that particular frequency (because of LPF which gives output for beat frequency) and attenuate
heavily other frequencies. VCO output thus can be used for regenerating or reconditioning a
desired frequency signal (which is weak and buried in noise) out of many undesirable frequency
signals.
Some of the typical applications of PLL are discussed now.
2. Describe about the functional diagram of 555 timer and its Monostable Operation of 555
timer?
Figure (1) gives the functional diagram for 555 IC timer. Referring to Figure (1), three 5 kO
internal resistors act as voltage divider, providing bias voltage of (2/3) Vcc to the upper comparator
(UC) and (1/3) Vcc to the lower comparator (LC), where Vcc is the supply voltage. Since these two
voltages fix the necessary comparator threshold voltage, they also aid in determining the timing
interval. It is possible to vary time electronically too, by applying a modulation voltage to the
control voltage input terminal (pin 5). In applications where no such modulation is intended, it is
recommended by manufacturers that a capacitor (0.01 F) be connected between control voltage
terminal (pin 5) and ground to by-pass noise or ripple from the supply.
Figure: Functional diagram of 55 timer
In the standby (stable) state, the output Q of the control flip-flop (FF) is HIGH. This makes
the output LOW because of power amplifier which is basically an inverter. A negative going
trigger pulse is applied to pin 2 and should have its dc level greater than the threshold level of the
lower comparator (i.e. Vcc/3), the output of the lower comparator goes HIGH and sets the FF (Q =
1, Q = 0). During the positive excursion, when the threshold voltage at pin 6 passes through (2/3)
Vcc, the output of the upper comparator goes HIGH and resets the FF (Q = 0, Q = 1).
The reset input (pin 4) provides a mechanism to reset the FF in a manner which overrides
the effect of any instruction coming to FF from lower comparator. This overriding reset is effective
when the reset input is less than about 0.4 V. When this reset is not used, it is returned to Vcc. The
transistor Q2 serves as a buffer to isolate the reset input from the FF and transistor Q1. The
transistor Q2 is driven by an internal reference voltage Vref obtained from supply voltage Vcc.
Monostable Operation of 555 timer:
Figure (1) shows a 555 timer connected for monostable operation and its functional diagram
is shown in figure (2). In the standby state, FF holds transistor Q1 on, thus clamping the external
timing capacitor C to ground. The output remains at ground potential, i.e. LOW. As the trigger in
Figure 3(a) passes through Vcc/3, the FF is set, i.e. Q = 0. This makes the transistor Q1 off and the
short circuit across the timing capacitor C is released. As Qis LOW, output goes HIGH (= Vcc).
The timing cycle now begins. Since C is unclamped, voltage across it rises exponentially through R
toward Vcc with a time constant RC as in figure 3(b). After a time period T (calculated later) the
capacitor voltage is just greater than (2/3) Vcc and the upper comparator resets Q=1, transistor Q1
goes on (i.e. saturates), thereby discharging the capacitor C rapidly to ground potential. The
output returns to the standby state or ground potential as shown in figure 3(c).
Figure: Monostable multivibrator
The voltage across the capacitor as in figure 3(b) is given by
vc = Vcc (1 e
-t/RC
) (1)
At t = T, vc = (2/3) Vcc
Therefore
2
3
cc
V =
/
(1 )
T RC
CC
V e
or, T = RC ln(1/3)
or, T = 1.1 RC (seconds)(2)
It is evident from equation (2) that the timing interval is independent of the supply voltage.
It may also be noted that once triggered, the output remains in the HIGH state until time T
elapses, which depends only upon R and C. Any additional trigger pulse coming during this time
will not change the output state. However, if a negative going reset pulse as in figure 3(d) is
applied to the reset terminal (pin-4) during the timing cycle, transistor Q2 goes off, Q1 becomes on
and the external timing capacitor C is immediately discharged. The output now will be as in
Figure 3(e). It may be seen that the output of Q2 is connected directly to the input of Q1 so as to
turn on Q1 immediately and thereby avoid the propagation delay through the FF. Now, even if the
reset is released, the output will still remain LOW until a negative going trigger pulse is again
applied at pin 2. Figure (4) shows a graph of the various combinations of R and C necessary to
produce a given time delay.
vc = Vcc (1 e
-t/RC
) (1)
At t = T, vc = (2/3) Vcc
Therefore
2
3
cc
V =
/
(1 )
T RC
CC
V e
or, T = RC ln(1/3)
vc = Vcc (1 e
-t/RC
) (1)
At t = T, vc = (2/3) Vcc
Therefore
2
3
cc
V =
/
(1 )
T RC
CC
V e
or, T = RC ln(1/3)
Fig. Timer in monostable operation with functional diagram
Sometimes the monostable circuit of figure (1) mistriggers on positive pulse edges, even
with the control pin bypass capacitor. To prevent this, a modified circuit as shown in figure 5 is
used. Here the resistor and capacitor combination of 10 kO and 0.001 F at the input forms a
differentiator. During the positive going edge of the trigger, diode D becomes forward biased,
thereby limiting the amplitude of the positive spike to 0.7V.
Example:-
In the monostable multivibrator of Figure (1) R = 100 k and the time delay T = 100 ms.
Calculate the value of C. Verify the value of C obtained from the graphs of Figure (4).
Solution:-
From Equation (2), we get
Figure: Graph of RC combinations for different time delays
Figure: Modified monostable circuit
Example:-
Solution:-
Example:-
Solution:-
C = T/1.1 R = 100 10
-3
/1.1 100 10
3
= 0.9 F
From the graph of figure 4, the value of C is found to be 0.9 F also.
3. Write about the operation of linear ramp generator in 555 timer.
Linear Ramp Generator
Linear ramp can be generated by the circuit shown in figure (1). The resistor R of the
monostable circuit is replaced by a constant current source. The capacitor is charged linearly by
the constant current source formed by the transistor Q3. The capacitor voltage vc can be written as
t
c
0
1
V idt (8.3)
C
=
}
Where I is the current supplied by the constant current source. Further, the KVI equation can be
written as
Figure: Linear ramp generator
, )
1
cc BE B E c E E
1 2
R
V V 1 I R I R iR (8.4)
R R
= | + = =
+
Where IB Ic are the base current and collector current respectively, |is the current amplification
factor in CE-mode and is very high. Therefore.
, )
, )
1 cc BE 1 2
E 1 2
R V V R R
i (8.5)
R R R
+
=
+
Now putting the value of the current I in Eq. 8.3, we get
C = T/1.1 R = 100 10
-3
/1.1 100 10
3
= 0.9 F
t
c
0
1
V idt (8.3)
C
=
}
written as
, )
1
cc BE B E c E E
1 2
R
V V 1 I R I R iR (8.4)
R R
= | + = =
+
, )
, )
1 cc BE 1 2
E 1 2
R V V R R
i (8.5)
R R R
+
=
+
C = T/1.1 R = 100 10
-3
/1.1 100 10
3
= 0.9 F
t
c
0
1
V idt (8.3)
C
=
}
written as
, )
1
cc BE B E c E E
1 2
R
V V 1 I R I R iR (8.4)
R R
= | + = =
+
, )
, )
1 cc BE 1 2
E 1 2
R V V R R
i (8.5)
R R R
+
=
+
, )
, )
1 cc BE 1 2
c
E 1 2
R V V R R
V xt (8.6)
CR R R
+
=
+
At time t=T, the capacitor voltage Vc becomes (2/3) Vcc then we get
, )
, )
1 cc BE 1 2
c
E 1 2
R V V R R
2
V xT (8.7)
3 R R R C
+
=
+
Which gives the time period of the linear ramp generator as
, ) , )
, )
cc E 1 2
1 cc BE 1 2
2/ 3 V R R R C
T (8.8)
R V V R R
+
=
+
Figure: Linear ramp generator output
The capacitor discharges as soon as its voltage reaches (2/3) Vcc which is the threshold of the
upper comparator in the mono stable circuit functional diagram. The capacitor voltage remains
zero till another trigger is applied. The various wave forms are shown in fig. 8.11.
The practical values can be noted as
R1=47kO; RE = 2.7kO; c=0.1F.
Vcc=5V (any value between 5 to 18v can be chosen)
4. Write about the operation of frequency divider in 555 timer and PWM?
frequency divider:
A continuously triggered mono stable circuit when triggered by a square wave generator
can be used as frequency divider, if the timing interval is adjusted to be longer than the period of
the triggering square wave input signal. The mono stable multivibrator will be triggered by the
first negative going edge of the square wave ;input but the out will remain HIGH (because of
greater timing interval) for next negative going edge of the input square wave as shown in fig.
8.12. The mono-shot will however be triggered on the third negative going input, depending on
the choice of the time delay. In this way, the out put can be made integral fractions of the
frequency of the input triggering square wave.
pulse width modulation in 555 timer:
The circuit is shown in fig. 8.13. This is basically a monostable multivibrator with a
modulating input signal applied at pin-5. By the application of continuous trigger at pin-2, a series
of output pulses are obtained, the duration of which depends of the modulating input at pin 5.
The modulating signal applied at pin-5 gets superimposed upon the already existing voltage (2/3)
Vcc at the inverting input terminal of UC. This in turn changes the threshold level of the UC and
the output pulse width modulation takes place. The modulating signal and the
Out put wave form are shown in fig. 8.14. it may be noted from the out put wave form that the
pulse duration, that is, the duty cycle only varies, keeping the frequency same as that of the
continuous input pulse train trigger.
5. Explain about Astable operation also explain astable as a FSK generator?
The device is connected for astable operation as shown in fig. 8.15. for better
Understanding, the complete diagram of astable multivibtrator with detailed internal diagram of
555 is shown in fig 8.16 Comparing with monostable operation, the timing resistor is now split
into two sections RA and RB pin 7 of discharging transistor Q1 is connected to the junction of RA
and RB when the power supply
Figure: Functional diagram of multivibtrator using 555 timer
Vcc is connected the external timing capacitor c charges towards Vcc with a time constant (RA + RB)
C. during this time, out put (pin3) is high (equals Vcc) as Reset R=0. set S=1 and this combination
makes Q =0 which has unclamped the timing capacitor C.
When the capacitor voltage equals (to be precise is just greater than), (2/3) Vcc the upper
comparator triggers the control flip-flop so that Q =1. this in turn, makes transistor Q1 on and
capacitor C starts discharging towards ground through RB and transistor Q1 with a time constant
RBC(neglecting the forward resistance of Q1). Current also flows into transistor Q1 through RA
Resistor RA and RB must be large enough to limit this current and prevent damage to the
discharge transistor Q1. The minimum value of RA is approximately equal to Vcc/0.2 where 0.2A is
the maximum current through the on transistor Q1.
During the discharge of the timing capacitor C, as it reaches (to be prices, is just less than)
Vcc/3, the lower comparator is triggered and at this stage S=1,R=0, which turns Q=0. Now Q=0
unclamps the external timing capacitor C. the capacitor C is thus periodically charged and
discharged between (2/3) Vcc and (1/3) Vcc respectively. Figure 8.17 shows the timing sequence and
capacitor voltage wave form. The length of time that the out put remains HIGH is the time for the
capacitor to charge from (1/3) Vccto (2/3) Vcc It may be calculated as follows:
Figure: Timing sequence of astable multivibrator
The capacitor voltage for a low pass RC circuit subjected to step input of Vcc volts is given by
t / RC
c cc
V V (1 e )
=
The t1 taken by the circuit to charge form 0 to (2/3) Vcc is,
, )
, )
1
1
t / RC
cc cc
t / RC
1
2/ 3 V V (1 e )
1
1.09 t / RC in in e
3
=
= : = / /
1
1
1
t / RC
t / RC
or
t 1.09RC
2
1 e
3
1
e (8.9)
3
=
=
/
= /
Q1 when the variable resistors are at minimum value. And, if RA is made equal to RB then 50%
duty cycle is achieved.
Symmetrical square wave generated by adding a clocked JK flip-flop to the out put of the
nonsymmetrical square wave generated is shown in Fig. 8.20. The clocked flip-flop acts as binary
divider to the timer output. The output frequency in this case will be one half that of the timer.
The advantage of this circuit is of having output of 50% duty cycle without any restriction on the
choice of RA and RB.
Application of astable mode in FSK generator:
FSK Generator
In digital data communication, binary code is transmitted by shifting a carrier frequency
between two present frequencies. This type of transmission is called frequency shift keying (FSK)
technique. A 555 timer in astable mode can be used to generate FSK signal. The circuit is as
shown in fig 8.21. The standard digital data input frequency is 150 Hz. When input is HIGH,
transistor Q is off and 555 timer works in the normal astable mode of operation. The frequency of
the output waveform given by Eq. (8.1) can be rewritten as
Fo =
A B
1.45
(R +2R ) C
In a tele typewriter using a modulator demodulator (MODEM), a frequency between 1070 Hz
to 1270 Hz is used as one of the standard FSK signals. The components RA and RB and the
capacitor C can be selected so that Fo is 1070 Hz.
When the input is LOW, Q goes on and connects the resistance Rc across RA. The output frequency
is now given by
A c a
1.45
(R ||R ) + 2R
The resistance Rc can be adjusted to get an output frequency 1270 Hz.
Figure: FSK generator
UNIT V
APPLICATION ICs
PART A
1. What are the limitations of 723 regulator?
1. It can be current boasted with an external pass
2. not short circuit protection transistor
3. O/P voltage is fixed
4. Current fold back using external components
2.Diffenretiate between linear and switching regulations?
Linear regulations Switching regulations
1. The series pass transistor operates in the active
region as a linear devices as switching devices
The series pan transistor operator either at cut-off
or at saturation.
2. Since the pass transistor is always in the active
region, power dissipation is more.
Power dissipation is less
3. The efficiency is less The efficiency is more.
3. What are the limitation of linear voltage regulator?
1. The input step down transformer is bulky and the most expensive component of the linear
regulated power supply mainly because of low line frequency.
2. Because of the low line frequency, larger values of filter capacitors are required to decrease
ripple.
3. The efficiency of a series regulator is very low.
4. What are the important features of 723 voltage regulator?
Input voltage 40v max
O/p voltage adjustable from 2v to 37v
150mA O/P current without external pass transistor
Can be used as either linear or a switching regulator
5. Mention some applications of Ic723 voltage regulator?
(i) Basic Low-voltage regulator [V0=2 to 7 Volts]
(ii) High voltage 723 regulator
(iii) Current boosting.
6. Name some of the applications of power amplifiers?
1. Used to drive electronic values
2. push pull solenoids
3. Dc & ac motors
7.Give the functional Block Diagram of ICL8038.?
222
8. Give the test circuit for ICL8038
9. What are the Important characteristics of opto coupler?
(i) current intensity ratio
(ii) isolation impedance
(iii) Response time
(iv) CMRR
10. What are the features of LM380.?
It features an internally fixed gain of 50 (34 dB) and an output which automatically centers
itself at one-half of the supply voltage. A unique input stage allows inputs to be ground
referenced or AC coupled as required. The output stage of the LM380 is protected with both short
circuit current limiting and thermal shutdown circuitry. All of these internally provided features
result in a minimum external parts count integrated circuit for audio applications.
PART B
1. Explain briefly about Voltage regulator?
A voltage regulator is an electronic circuit that provides a stable dc voltage independent of the
load current, temperature and ac line voltage variations. Figure 6.1 shows a regulated power
supply using discrete components. The circuit consists of following four parts:
1. Reference voltage circuit
2. Error amplifier
3. Series pass transistor
4. Feedback network
It can be seen from fig 6.1 that the power transistor Q1 is in series with the unregulated dc
voltage Vin and the regulated output voltage V0. so it must absorb the difference between these
two voltages whenever any fluctuation in output therefore provides sufficient current gain to
drive the load. The output voltage is sampled by the R1 R2 divider and fed back to the (-) input
terminal of the op amp error amplifier. This sampled voltage is compared with the reference
voltage Vref (usually obtained by a zener diode). The output V0 of the error amplifier drives the
series transistor Q1.
If the output voltage increases, say, due to variation in load current, the sampled voltage |V0 also
increases where
| =
2
1 2
R
R +R
This, in turn, reduces the output voltage V0 of the diff amp due to the 180 phase difference
provided by the op amp amplifier. V0 is applied to the base of Q1, which is used as an emitter
follower. So V0 follows V0, that is V0 also reduces. Hence the increase in V0 is nullified. Similarly,
reduction in output voltage also gets regulated.
characteristics and parameters of voltage regulator:
1. V0: The regulated output voltage is fixed at a value as specified by the manufacturer. There
are a number of models available for different output voltages, for example, 78XX series has
output voltage at 5, 6, 8 etc.
2. |Vin| > |V0|+2 volts: The unregulated input voltage must be atleast 2 V more than the
regulated output voltage. For example, if V0 = 5 V, then Vin = 7 V
3. I(0) max: The load current may vary from 0 to rated maximum output current. The IC is
usually provided with a heat sink, otherwise it may not provide the rated maximum output
current.
4. Thermal shutdown: The IC has a temperature sensor (built in) which turns off the IC when
it becomes too hot (usually 125C to 150C). the output current will drop and remain there
until the IC has cooled significantly.
Table gives the electrical characteristics of 7805 voltage regulator and the connection diagram
of packages available. Some of the important performance parameters listed in the data sheet are
explained as follows:
Line / Input regulation
It is defined as the percentage change in the output voltage for a change in the input voltage.
current.
current.
It is usually expressed in millivolts or as a percentage of the output voltage. Typical value of line
regulation from the data sheet of 7805 is 3 mV.
Load regulation
It is defined as the change in output voltage for a change in load current and is also expressed in
millivolts or as a percentage of V0. Typical value of load regulation for 7805 is 15 mV for 5mA < I0
< 1.5 A.
Ripple rejection
The IC regulator not only keeps the output voltage constant but also reduces the amount of
ripple voltage. It is usually expressed in dB. Typical value for 7805 in 78 dB.
3 a). Specify suitable component values to get Vo = 7.5 in the circuit of fig 6.5 using a 7805
regulator
Solution:
From the data sheet of 7805, IQ = 4.2mA. Say we choose IR1=25mA.
As VR = 5 V for 7805,
R1 = 5V/25mA = 200O
We have to choose R2 so as to develop a voltage of 2.5 V across it. So,
R2 = 2.5V/ (IR1 + IQ) = 2.5/ (4.2 + 25) = 85.6O
Chose R2 = 85O
3 b). Write about 723 general purpose regulator?
The three terminal regulators discussed earlier have the following limitations:
1. No short circuit protection
2. Output voltage (positive or negative) is fixed.
These limitations have been overcome in the 723 general purpose regulator, which can be
adjusted over a wise range of both positive or negative regulated voltage. Thus IC is inherently
low current device, but can be boosted to provide 5 amps or more current by connecting external
components. The limitation of 723 is that it has no in built thermal protection. It also has no
short circuit current limits.
Figure 6.7 (a) shows the functional block diagram of a 723 regulator IC. It has two separate
sections. The zener diode, a constant current source and reference amplifier produce a fixed
voltage of about 7 volts at the terminal Vref. The constant current source forces the zener to operate
at a fixed point so that the zener outputs a fixed voltage.
The other section of the IC consists of an error amplifier, a series pass transistor Q1 and a
current limit transistor Q2. The error amplifier compares a sample of the output voltage applied at
the INV input terminal to the reference voltage Vref applied at the NI input terminal. The error
signal controls the conduction of Q1. these two sections are not internally connected but the
various points are brought out on the IC package. 723 regulator IC is available in a 14 pin dual
in line package or 10 pin metal can as shown in fig 6.7 (b) The important features and
electrical characteristics are given in table 6.2.
Figure: Pin diagram for 14 pin DIP and 10 pin metal can
A simple positive low voltage (2 V to 7V) regulator can be made using 723 as shown in the
schematic of fig 6.8 (a). In order to understand the circuit operation, consider the detailed circuit of
fig 6.8 (b). The voltage at the NI terminal of the error amplifier due to R1, R2 divider is,
723 voltage regulator
Important features:
Input voltage 40 V max
Output voltage adjustable from 2V t0 37V
150mA output current without external pass transistor
output currents in excess of 10 A possible by adding external transistors
Can be used as either a linear or a switching regulator
4. Explain about Switching Regulator?
The regulated power supplies discussed so far are referred to as linear voltage regulator,
since the series pass transistor operates in the linear region. The linear voltage regulator has the
following limitations.
The input step down transformer is bulky and the most expensive component of the linear
regulated power supply mainly because of low line frequency (50Hz). Because of the low line
frequency, large values of filter capacitors are required to decrease the ripple. The efficiency of a
series regulator is usually very low (typically 50 percent). The input voltage must be greater than
the output voltage. The greater the difference in input output voltage must be greater than the
output voltage. The greater the difference input output voltage, more will be the power dissipated
in the series pass transistor which is always in the active region. A TTL system regulator (V0 = 5V)
when operated at 10 V dc input gives 50 percent efficiency and only 25 percent for 20 V dc input.
Another limitations is that in a system with one dc supply voltage (Such as +5V for TTL) if there is
need for 15V. for op amp operation, it may not be economically and practically feasible to
achieve this.
Switched mode power supplies overcome these difficulties. The switching regulator, also
called switched mode regulator operate in a significantly different way from that of a conventional
series regulator circuit discussed earlier. In series regulator, the pass transistor is operated in its
linear region to provide a controlled voltage drop across it with a steady dc current flow. Whereas,
in the case of is switched mode regulator the pass transistor is used as a controlled switch and
is operated at either cutoff or saturated state. Hence the power transmitted across the pass device
is in discrete pulses rather than as a steady current flow. Greater efficiency is achieved since the
pass device is operated as a low impedance switch. When the pass device is at cutoff, there is no
current and dissipates no power. Again when the pass device is in saturation, a negligible voltage
drop appears across it and thus dissipates only a small amount of average power, providing
maximum current to the load. In either case, the power wasted in the pass device is very little and
almost all the power is transmitted to the load. Thus efficiency in switched mode power supply is
remarkably high in the range of 70 90%.
Switched mode regulators rely on pulse width modulation to control the average value of
the output voltage. The average value of a repetitive pulse waveform depends on the area under
the waveform. If the duty cycle is varied as shown in Fig. 6.12, the average value of the voltage
changes proportionally.
Figure: Pulse width modulation and average value
The bridge rectifier and capacitor filters are connected directly to the ac line to give
unregulated dc input. The thermistor Rt limits the high initial capacitor charge current. The
reference regulator is a series pass regulator of the type shown in Fig. 6.1 Its output is a regulated
reference voltage Vref which serves as a power supply voltage for all other circuits.
Transistors Q1 and Q2 are alternately switched off and on at 20 kHz. These transistors are
either fully on 1(VCE sat ~ 0.2 v) or cut off, so they dissipate very little power. These transistors
drive the primary of the main transformer. The secondary is centre tapped and full wave
rectification is achieved by diodes D1 and D2. This unidirectional square wave is next filtered
through a two stage LC filter to produce output voltage Ve.
The regulation of V0 is achieved by the feed back circuit consisting of a
5 a). Write Short notes on Function Generator?
5 b). Explain briefly about Optocopler?
Types of Optocopler:
Advantages of Optocopler:

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UNIT I

LSB increment Resolution of a converter is the smaller change in

(t/2) and a fundamental frequency (fs

(t/2) A (f1/Af) (from Eq 9.24) .. (9.37)

(t/2) A (f1/Af) (9.37)

(t/2) A (f1/Afc) . (9.38)

(t/2) Af1 (from Eq (9.38)

A t. In case of IC PLL 565, R = 3.6 kO, so the capture

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UNIT I

LSB increment Resolution of a converter is the smaller change in

(t/2) and a fundamental frequency (fs

(t/2) A (f1/Af) (from Eq 9.24) .. (9.37)

(t/2) A (f1/Af) (9.37)

(t/2) A (f1/Afc) . (9.38)

(t/2) Af1 (from Eq (9.38)

A t. In case of IC PLL 565, R = 3.6 kO, so the capture

Das könnte Ihnen auch gefallen

LIC & Applications

LIC & Applications