Explain why & how a MOSFET works. 2. Draw Vds-Ids curve for a MOSFET.

Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation 3. Explain the various MOSFET Capacitances & their significance 4. Draw a CMOS Inverter. Explain its transfer characteristics 5. Explain sizing of the inverter 6. How do you size NMOS and PMOS transistors to increase the threshold voltage? 7. What is Noise Margin? Explain the procedure to determine Noise Margin 8. Give the expression for CMOS switching power dissipation 9. What is Body Effect? 10. Describe the various effects of scaling 11. Give the expression for calculating Delay in CMOS circuit 12. What happens to delay if you increase load capacitance? 13. What happens to delay if we include a resistance at the output of a CMOS circuit? 14. What are the limitations in increasing the power supply to reduce delay? 15. How does Resistance of the metal lines vary with increasing thickness and increasing length? 16. You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other 17. What happens if we increase the number of contacts or via from one metal layer to the next? 18. Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times 19. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B.

To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output? 20. Draw the stick diagram of a NOR gate. Optimize it 21. For CMOS logic, give the various techniques you know to minimize power consumption 22. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus 23. Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter? 24. In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width? 25. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates) 26. Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram 27. Why dont we use just one NMOS or PMOS transistor as a transmission gate? 28. For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD 29. Draw a 6-T SRAM Cell and explain the Read and Write operations 30. Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation) 31. What happens if we use an Inverter instead of the Differential Sense Amplifier? 32. Draw the SRAM Write Circuitry 33. Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes? 34. How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAMs performance? 35. Whats the critical path in a SRAM? 36. Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

37. Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers 38. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why? 39. How can you model a SRAM at RTL Level? 40. Whats the difference between Testing & Verification? 41. For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic) 42. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

if the input signal is asynchronous with the clock (state machine clock), then you need to double clock the same signal to synchronize with the state machine clock. When signal transfer from one clock domain sequential to another clock domain sequential logic this situation basically arises when a signal does clock domain crossing. to synchronize the clock with the target domain clock and to avoid metastability issues synchronizers which are like double clocking are used in designs

What is LVS, DRC?

LVs means LAyout versus schematic -method to check the correctness of ur layout designed by cross checking with netlist generated from schematic using the tool.

DRC means....?? DRC means Design Rules Checker - a tool for verifying the layout with the Physical layout design rules set so as to make sure that none of the rules have been violated. LVS- LAYOUT VERSUS SHEMATIC TEST FROM NETLIST DESIGN (NORMALLY MANUAL METHOD) DRC-DESIGN RULE CHECK(EX SPICE TOOL WILL GENERATE ERRORS IF YOUR DESIGN NOT MET THE STANDARD DESIGN RULES)

LVS -LAYOUT VERSUS SHEMATIC TEST WHICH COMES IN THE STRACTURIAL DOMAIN IN WHICH WE WILL FIRST SHEMATIC THE CIRCUT AND AFTER BY USING TOOLS WE WILL MAKE THE LAYOUT BY COMAPARING THE BOTH THINGS JUST FOR SEEING WHEATHER ANY MISTAKES IS THERE OR NOT ...........IT IS TESTING PROCESS DRC-DESIGN RULE CHECK THESE USEDE TESTING THE LAYOUT DESIGN AND FOR CHECKING THE CIRCUIT

LVS is when the netlist (normally synthesized verilog) and the physical layout (gdsii) match connections (ie cells and wire connections match the physical layout). DRC is when the physical layout is checked to make sure that the layout of the part is manufacturable using the process that the foundry is capable of. (ie if two metal wires aretoo close together on the same layer, they may short during the manufacturing process, affecting yield, just one of many possible examples on this one) Some of the other answers are right, but don't explain it well.

LVS and DRC and

Means Layout versus schematic,,,To compare the Layout Spice SubCkt.... Means Design Rule Check,,,,To check the connection for checking the Close Proximity

LVS IS LAYOUT VERSUS SCHEMATIC ,this is for the compare the layout with schematic if any thing wrong connection inlayout you can find by using this lvs DRC is Design Rule check this is using for the to check the area of layer and distance between layers LVS mean's layout versus schmetic.. compare to layout and schmetic.. DRC mean's design rule check.. layer to layer between distence in vlsi layout design
1. What is the difference between Behavior modeling and RTL modeling? 2. What is the benefit of using Behavior modeling style over RTL modeling? 3. What is the difference between blocking assignments and non-blocking assignments ? 4. How do you implement the bi-directional ports in Verilog HDL 5. How to model inertial and transport delay using Verilog? 6. How to synchronize control signals and data between two different clock domains? 7. Create 4 bit multiplier using a ROM and what will be the size of the ROM. How can you realize it when the outputs are specified. 8. How can you swap 2 integers a and b, without using a 3rd variable 9. Which one is preferred? 1's complement or 2's complement and why? 10. Which one is preferred in FSM design? Mealy or Moore? Why? 11. Which one is preferred in design entry? RTL coding or Schematic? Why? 12. Design a 2 input OR gate using a 2:1 mux. 13. Design a 2 input AND gate using a 2 input XOR gate. 14. Design a hardware to implement following equations without using multipliers or dividers. a. out = 7x + 8y; b. out = .78x + .17y; 15. Design Gray counter to count 6. 16. Design XOR gate using just NAND gates. 17. Create "AND" gate using a 2:1 multiplexer. (Create all other gates too.) 18. How are blocking and non-blocking statements executed? 19. How do you model a synchronous and asynchronous reset in Verilog?

20. What happens if there is connecting wires width mismatch? 21. What are different options that can be used with $display statement in Verilog? 22. Give the precedence order of the operators in Verilog. 23. Should we include all the inputs of a combinational circuit in the sensitivity list? Give reason. 24. Give 10 commonly used Verilog keywords. 25. Is it possible to optimize a Verilog code such that we can achieve low power design? 26. Which is updated first: signal or variable?

VHDL Interview Questions

What is the difference between using direct instntiations and component ones except that you need to declare the component ? What is the use of BLOCKS ? What is the use of PROCEDURES? What is the usage of using more then one architecture in an entity? What is a D-latch? Write the VHDL Code for it? Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop? Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to? Differences between functions and Procedures in VHDL? Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same? What you would use in RTL a 'boolean' type or a 'std_logic' type and why. What are/may be the implications of using an 'integer' type in RTL. A timing path fails: what are your options? What are VHDL structures, give an example to exploit them What is grey coding, any example where they are used Discuss Async interfaces Metastability

Synopsys unwanted latch Verilog blocking vs non-blocking VHDL variables: example where you have to use them What is pipelining and how it may improve the performance What are multicycle paths. What are false paths What are Async counters, what are advantages of using these over sync counters. and what are the disadvantages Sensitivity List: How does it matter.What will happen if you dont include a signal in the sensitivity list and use/read it inside the process How you will implement a C language pointer in VHDL What is Design For Test and why it is done. What is clock gating? How and why it is done. Low Power: discuss how it may be done Discuss disadvantages/challenges of shrinking technology What is pipelining, how may it affect the performance of a design What is the difference between transport delays and inertial delays in VHDL What determines the max frequency a digital design may work on Why thold(hold time) is not included in the calculation for the above. What will happen if output of an inverter is shorted to its input What is noise margin. Why are p-mos larger than n-mos in CMOS design. Draw DC curve of inverter and Re-Draw it if pmos and nmos are equal. What is Latch-up How can an Inverter work as an amplifier Design a state machine which divides the input frequency of a clock by 3. Why does a pass gate requires two transistors(1 N and 1 P type) Can we use a single transistor N or P type in a pass gate? If not why? and if yes then in what conditions? Why CMOS why not N-MOS or P-MOS logic, when we know that the number of gates required in CMOS are grater than in n-mos or p-mos logic.

How much is the max fan out of a typical CMOS gate. Or alternatively, discuss the limiting factors. What are dynamic logic gates? What are their advantages over conventional logic gates Design a digital circuit to delay the negative edge of the input signal by 2 clock cycles What is the relation between binary encoding and grey(or gray) encoding. Write a vhdl function to implement a length independent grey code counter. alternatively, discuss the logic to do that. How you will constraint a combinational logic path through your design in dc_shell. Make a T Flip Flop using a D Flip Flop How you will make a Nand Gate function like an inverter. Design a state machine to detect a '1101' pattern in a stream. Detect both, overlapping and non overlapping patterns. What are MISRs, example usage?

CMOS Interview Questions

1. Explain why & how a MOSFET works 2. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation 3. Explain the various MOSFET Capacitances & their significance 4. Draw a CMOS Inverter. Explain its transfer characteristics 5. Explain sizing of the inverter 6. How do you size NMOS and PMOS transistors to increase the threshold voltage? 7. What is Noise Margin? Explain the procedure to determine Noise Margin 8. Give the expression for CMOS switching power dissipation 9. What is Body Effect? 10. Describe the various effects of scaling 11. Give the expression for calculating Delay in CMOS circuit 12. What happens to delay if you increase load capacitance? 13. What happens to delay if we include a resistance at the output of a CMOS circuit? 14. What are the limitations in increasing the power supply to reduce delay?

15. How does Resistance of the metal lines vary with increasing thickness and increasing length? 16. You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other 17. What happens if we increase the number of contacts or via from one metal layer to the next? 18. Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times 19. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output? 20. Draw the stick diagram of a NOR gate. Optimize it 21. For CMOS logic, give the various techniques you know to minimize power consumption 22. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus 23. Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter? 24. In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width? 25. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates) 26. Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram 27. Why dont we use just one NMOS or PMOS transistor as a transmission gate? 28. For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD 29. Draw a 6-T SRAM Cell and explain the Read and Write operations 30. Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation) 31. What happens if we use an Inverter instead of the Differential Sense Amplifier? 32. Draw the SRAM Write Circuitry 33. Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes? 34. How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAMs performance? 35. Whats the critical path in a SRAM? 36. Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal? 37. Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers 38. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why? 39. How can you model a SRAM at RTL Level? 40. Whats the difference between Testing & Verification? 41. For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic) 42. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you

avoid Latch Up? =============================================================== 1. Give two ways of converting a two input NAND gate to an inverter 2. Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt) 3. What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit? 4. Give a circuit to divide frequency of clock cycle by two 5. Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock) 6. Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You cant resize the combinational circuit transistors) 7. The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this? 8. What are the different Adder circuits you studied? 9. Give the truth table for a Half Adder. Give a gate level implementation of the same. 10. Draw a Transmission Gate-based D-Latch. 11. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output) 12. How do you detect if two 8-bit signals are same? 13. How do you detect a sequence of "1101" arriving serially from a signal line? 14. Design any FSM in VHDL or Verilog. 15. Explain RC circuits charging and discharging. 16. Explain the working of a binary counter. 17. Describe how you would reverse a singly linked list