CPU Architecture :

Specification

Determine the application, the tasks to be fulfilled

Fetch

Design the Instruction Set Architecture (ISA) select the instructions needed to fulfill the task decide on the register set needed
Decode

Design the state diagram for the CPU specify the micro-instructions needed Identify the datapaths within the CPU

Execute

CPU Architecture :

Carpinellis very simple CPU.

It can access 64 words of memory. Each word is 8 bits wide. It outputs a 6 bit address on pins A[5 .. 0] D0 and reads an 8 bit value on pins D[7 .. 0] A0 A1 D1
D2 D3 A2 A3 A4 A5 read Accumulator

It has four instructions : ADD AND JMP INC

D4 D5 D6 D7

It has one programmer accessible register : AC an 8-bit accumulator

CPU Architecture :

Carpinellis very simple CPU.

It will require the following register set 8 bit Accumulator, AC PC AR DR IR

6 bit Program Counter, 6 bit Address Register, 8 bit Data Register,

2 bit Instruction Register,

CPU Architecture :
Instruction ADD AND JMP INC

Fetch - Execute.
Opcode 00AAAAAA 01AAAAAA 10AAAAAA 11AAAAAA Operation AC < AC + M[AAAAAA] AC < AC ^ M[AAAAAA] GOTO AAAAAA AC < AC + 1

Fetch Instruction : address to memory, on address pins mem ready, so signal read, read data pins Decode is effected by the value in IR Separate states will represent the instruction execution

CPU Architecture :

Fetch cycle. 1

The fetch phase will take three states : FETCH1: AR PC

As AR will be connected to A[5..0], this places the address on the address pins FETCH2: DR M, PC PC + 1

Assert read, data available on D[7..0], store in DR. Increment the Program Counter.

CPU Architecture :

Fetch - cycle. 2

FETCH3:

IR

DR[7..6],

AR

DR[5..0]

Copy the instruction into the IR. Copy the lower 6 bits into the AR as if its an or an
ADD AND

then this will be the address to get the data from. This saves one cycle during execute.

CPU Architecture :

establish the execute steps.

ADD1: DR ADD2: AC AND1: DR AND2: AC JMP1: PC
IR=11

FETCH1

M AC + DR M AC ^ DR DR[5..0] AC + 1

FETCH2

FETCH3 IR=00 IR=01 ADD execute cycle AND execute cycle IR=10 JMP execute cycle INC execute cycle

INC1: AC

CPU Architecture :
READ 6

Establish data paths.

M

Sort the register transfers by destination

D[7..0]

A[5..0] 6 6 AR 6 6

AR :

AR AR PC PC AC AC AC IR

PC DR[5..0] PC + 1 DR[5..0] AC + DR AC ^ DR AC + 1 DR[7..6]

PC

PC :

8 DR

AC :

AC

2 IR

IR :

CLK

8 bit bus

CPU Architecture :

Register Selection.

AR only supplies data to memory, not other components IR doesnt supply data to any component via the internal bus AC does not supply data to any component Bus is 8 bits wide, but not all registers are, so specify the width of connections AC must load sum of AC and DR, also logical AND of AC and DR so we need an ALU

CPU Architecture :

Control Signals.

We need a load signal for all registers that act as destinations for data We need bus enable signals for those registers that output data to the internal bus We need to ensure that all transfers that take place in the same state can occur simultaneously We need to be able to increment the PC register and the AC register.

CPU Architecture :

Final Register Selection.

READ M 6

A[5..0] 6 6 LD ARLOAD AR MEMBUS

D[7..0]

PCBUS

6 LD

PC INC

PCLOAD PCINC DRBUS 8 LD DRLOAD 8 DR 8 8

LD

AC INC

ACLOAD ACINC

2 [7..6]

LD IRLOAD

IR

8 bit bus

CPU Architecture :

Simple ALU.

AC 8

8 MUX 1 parallel adder 8 0 S 8 to AC

DR 8

control signal

CPU Architecture :
input Counter clk ld inc clr

Hardwired Control.
Logic control signals

Decoder

This CPU has 9 states therefore we need : a 4 bit counter a 4 to 16 decoder of which 7 outputs will not be used.

CPU Architecture :

Assigning states.

1) Assign FETCH1 to counter value 0 and use the CLR input to the counter to get to this state. input control
Counter Decoder Logic signals clk FETCH1 is the only state that can be reached by more than one state, ld inc states. clr its reached from four

Branches to FETCH1 can then be made by clearing the counter, this is easy to implement in the control unit logic. All the other states can only be reached from one other state.

CPU Architecture :

Sequential States.

2) Assign sequential states to sequential counter values, using the INC input to the counter to traverse the states. input control
Counter Decoder Logic signals clk Again this reduces the required control logic as a state need only assert the INC signal. ld inc clr

eg. Assign counter value 1 to FETCH2 and counter value 2 to FETCH3. Similarly AND1 and AND2 would be assigned consecutive values.

CPU Architecture :

Execute States.

3) Use the instruction opcode to assign the first state of each execute routine, allowing for the maximum number of steps required for an execute routine. input
Counter Decoder Logic control signals clk eg. if the longest execute cycle is 4 steps and assuming an opcode 01 then a state value of 0100 would be suitable for the first step. ld inc clr

Use the opcode as data input to the counter and load (ld) this value into the counter as the start point for the execute cycle load 0100 ->inc, 0101 -> inc, 0110 -> inc, 0111 ->clr, 0000

CPU Architecture :

States attempt 1

The input to the counter needs to be a function of IR The function needs to be as simple as possible
1 0 IR[1..0]

This gives load values of IR 00 01 10 11 Counter value 1000 1001 1010 1011 State ADD1 AND1 JMP1 INC1

CPU Architecture :

States attempt 2

Given that there are a maximum of two states for an execute

1 IR[1..0] 0 gives a better mapping

IR 00 01 10 11

Counter value 1000 1001 1010 1011 1100 1110

State ADD1 ADD2 AND1 AND2 JMP1 INC1

CPU Architecture :

Control Signals
0 1 2 . . . 8 9 10 11 12 . . . 14 . FETCH1 FETCH2 FETCH3

Decoder Counter 4 1 IR[1..0]0 4

ADD1 ADD2 AND1 AND2 JMP1

INC1

LD

INC

CLR

ADD2 JMP1

AND2 INC1

FETCH1 ADD1

FETCH2 AND1

CPU Architecture :
PCLOAD PCINC DRLOAD ACLOAD ACINC IRLOAD = = = = = =

Control Signals 2

JMP1 FETCH2 FETCH2 \/ ADD1 \/ AND1 ADD2 \/ AND2 INC1 FETCH3

MEMBUS = FETCH2 \/ ADD1 \/ AND1 PCBUS = FETCH1 READ = FETCH2 \/ ADD1 \/ AND1

CPU Architecture :
FETCH1 FETCH3

States attempt 1
ARLOAD FETCH3 AND2 IRLOAD ALUSEL

JMP1 FETCH2 FETCH2 AND1

PCLOAD ADD1 PCINC FETCH2 AND1 FETCH1 MEMBUS

ADD1

DRLOAD

PCBUS

ADD2 ADD2 AND2 ACLOAD JMP1

FETCH3 AND2 DRBUS

INC1

ACINC

ADD1

FETCH2 AND1

READ