Chapter 6 : Memory Interface

By Dr. Ridha Jemal

Electrical Engineering Department College of Engineering King Saud University
Ridha Djemal

6.1. Introduction to Memory Interface 6.2. Memory Interface 6.3. Memory Devices 6.4. Memory Decoding

Dr. Ridha Jemal

EE353: Introduction to Microprocessor

Introduction to Memory Interface

Simple or complex, every microprocessor-based system has a memory system. Almost all systems contain two main types of memory: read-only memory (ROM) and random access memory (RAM) or read/write memory. This chapter explains :
o how to interface both memory types to the Intel family of microprocessors. o How to Interface memory to an 8-, 16-bit data bus. o Interface dynamic RAM to the microprocessor

Memory Connection

The connections that all memory devices have in common are Address inputs, Data Outputs and / or Inputs, some type of Selection Input and at least one Control Input to Read or Write Data.
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Introduction to Memory Interface

Memory Devices

RAM ( Random Access Memory ). Memory is Erased when DC Power is Off. SRAM ( Static Random Access Memory ) DRAM ( Dynamic Random Access Memory ) ROM ( Read Only Memory ). Memory is Permanently Stored even Power is Off. PROM ( Programmable Read Only Memory ) EPROM ( Erasable Programmable Read Only Memory ) EEPROM ( Electrically Erasable Programmable Read Only Memory )

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EE353: Introduction to Microprocessor 1431-1432

Memory Interface
Memory Pin Connections

Address Connections

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10

O0 O1 O2 O3 O4 O5 O6 O7

Data Connections

Write Enable
WE CS OE

Chip Select

Output Enable

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Memory Interface (contd.)

Address Connections
All memory devices have a set of Address Inputs used to select a memory location Within the memory device. The numbers of Address Pins found on a memory device is determined by the number of Memory Locations found within it. The more common memory devices have between 1 K ( 1024 ) and 256 K memory locations, work is on to get 1 M memory locations devices. A 1 K memory device has 10 Address Pins. Therefore 10 Address Inputs are required to single out any one of its 1024 memory locations It takes 10 bit binary number ( 1024 different combinations ) to select any single location on a 1024 memory location device. 2 K ( 2048 memory locations ) memory device will have 11 Address Pins. 4 K ( 4096 memory locations ) memory device will have 12 Address Pins. 8 K ( 8192 memory locations ) memory device will have 13 Address Pins. Therefore the number of memory locations can thus be extrapolated from the number of Address Pins.
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Dr. Ridha Jemal

Memory Interface (contd.)

Data Connections All memory devices have a set of data outputs or input/outputs.
o today, many devices have bidirectional common I/O pins o data connections are points at which data are entered for storage or extracted for reading

Data pins on memory devices are labeled D0 through D7 for an 8-bit-wide

memory device. Not all memory devices are 8 bits wide, there are 4 bits or even 1 bit wide memory devices also. It is often mentioned as 2 K x 8.
An 8-bit-wide memory device is often called a byte-wide memory.
o most devices are currently 8 bits wide, o some are 16 bits, 4 bits, or just 1 bit wide

Catalog listings of memory devices often refer to memory locations times

bits per location.

a memory device with 1K memory locations and 8 bits in each location is often listed as a 1K x 8 by the manufacturer

Memory devices are often classified according to total bit capacity.

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Memory Interface (contd.)

Selection Connections
Each memory device has an Input ( sometimes more then one ) that Selects or Enables memory device. This kind of Input is called CS (Chip Select or G2A) or CE (Chip Enable) input. RAM memory has at least one CS input. ROM memory has at least one CE input. Logic 0 activates CE or CS and memory can Read or Write Logic 1 Deactivates CE or CS and memory can not Read or Write since it is turned Off or Disabled.

Dr. Ridha Jemal

EE353: Introduction to Microprocessor 1431-1432

Memory Interface (contd.)

Control Connections
All memory devices have some form of control or control input.
o ROM usually has only one Control input, OE ( Output Enable ), which allows data to flow out of the Output Data Pins, provided CE ( Chip Enable is also active )

The OE input actually Enables and Disables a Set of Three-State buffer located within the memory device. RAM has One or Two Control inputs.
o If there is One Control input it is often called R/W to select a Read operation or Write operation provided CS (Chip Select is also active). o If RAM has Two Control inputs, they are labeled as WE and OE . WE must be active to perform a memory Write operation and OE must be active to perform a memory Read operation. Both must not be active at the same time.

If both WE and OE are inactive ( Logic 1 ), then Data can neither be Read nor Written
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Memory Devices
ROM Memory
Read-only memory (ROM) permanently stores programs/data resident to the system.
o and must not change when power disconnected

Often called nonvolatile memory, because its contents do not change even if power is disconnected. A device we call a ROM is purchased in mass quantities from a manufacturer.
o programmed during fabrication at the factory

PROM Memory
PROM memory devices are also available, although they are not as common today. The PROM (programmable read-only memory) is also programmed in the field by burning open tiny Nichrome or silicon oxide fuses. Once it is programmed, it cannot be erased.
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Memory Devices (contd.)

EPROM Memory (UV-light-erasable PROM)
An EPROM is programmed in the field on a device called an EPROM programmer. Also erasable if exposed to high-intensity ultraviolet light.
o depending on the type of EPROM

EEPROM Memory (Electrically Erasable PROM)

The devise can be programmed and erased without removing the chip from its socket (like in the case of the EPROM) The programming is done electrically

Dr. Ridha Jemal

EE353: Introduction to Microprocessor 1431-1432

EPROM Programmer

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Memory Devices (contd.)

Flash Memory
A newer type of read-mostly memory (RMM) is called the flash memory. also often called an EEPROM (electrically erasable programmable ROM) EAROM (electrically alterable ROM) or a NOVRAM (nonvolatile RAM) Electrically erasable in the system, but they require more time to erase than normal RAM. The flash memory device is used to store setup information for systems such as the video card in the computer. Flash has all but replaced the EPROM in most computer systems for the BIOS. some systems contain a password stored in the flash memory device Flash memory has its biggest impact in memory cards for digital cameras and memory in MP3 audio players. Figure 102 illustrates the 2716 EPROM, which is representative of most Dr. Ridha Jemal EPROMs EE353: Introduction to Microprocessor 1431-1432 11 common

Memory Devices (contd.)

EEPROM Example

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Static and Dynamic RAMs

Static RAM
Static RAM memory devices retain data for as long as DC power is applied. Because no special action is required to retain data, these devices are called static memory. also called volatile memory because they will not retain data without power The main difference between ROM and RAM is that RAM is written under normal operation, whereas ROM is programmed outside the computer and normally is only read.

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Static and Dynamic RAMs

Static RAM
Basic six-transistor static Memory cell These transistor are connected to form a simple RS flip-flop.
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Static and Dynamic RAMs

Dynamic RAM DRAM
Available up to 256M x 8 (2G bits). DRAM is essentially the same as SRAM, except that it retains data for only 2 or 4 ms on an integrated capacitor. After 2 or 4 ms, the contents of the DRAM must be completely rewritten (refreshed), because the capacitors, which store a logic 1 or logic 0, lose their charges In DRAM, the entire contents are refreshed with 256 reads in a 2- or 4-ms interval. also occurs during a write, a read, or during a special refresh cycle DRAM requires so many address pins that manufacturers multiplexed address inputs.

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Memory Interfaces
SRAM Interface Example
To interface means to connect in a compatible manner. When interfacing memory, all the three system buses the address, control and data buses are involved.

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Memory Interfaces
Interfacing the 8088p.
64K x 8 8088 SRAM interface. Only a single memory chip is required.

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Memory Interfaces
Address Decoding
In order to attach a memory device to the microprocessor, it is necessary to decode the address sent from the microprocessor. Decoding makes the memory function at a unique section or partition of the memory map. Without an address decoder, only one memory device can be connected to a microprocessor, which would make it virtually useless.

Why Decode Memory ?

The 8088 has 20 address connections and the HM62864 has 16 connections. The 8088 sends out a 20-bit memory address whenever it reads or writes data. because the HM62864 has only 16 address pins, there is a mismatch that must be corrected The decoder corrects the mismatch by decoding address pins that do not connect to the memory component.
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Dr. Ridha Jemal

Memory Interfaces
Simple NAND Gate Decoder
When the 64K x 8 SRAM is used, address connections A15A0 of 8088 are connected to address inputs A15A0 of the SRAM. the remaining four address pins (A19A16) are connected to a NAND gate decoder The decoder selects the SRAM from one of the 64K-byte sections of the 1M-byte memory system in the 8088 microprocessor. In this circuit a NAND gate decodes the memory address, as seen in the following figure. If the 20-bit binary address, decoded by the NAND gate, is written so that the leftmost nine bits are 1s and the rightmost 11 bits are dont cares (X), the actual address range of the SRAM can be determined. a dont care is a logic 1 or a logic 0, whichever is appropriate Because of the excessive cost of the NAND gate decoder and inverters often required, this option requires an alternate be found.

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Memory Interfaces
Simple NAMD Gate Decoder Example
Example of an address decoder for the 8088 memory interface in previous figure. The memory will be enabled only when A19-A16 = 1110.

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Memory Interfaces
Memory Mapping
Memory map for the 8088 interface and decoder. The 64K SRAM is mapped to the address range E0000H to EFFFFH.

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Memory Interfaces
Example of Memory Decoding with NAND Gates
Design a Decoder to map the SRAM to the range C0000- CFFFFH using NAND gates.

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Memory Interfaces
Interface Between Memory and 8086 Microprocessor
Even and Odd Memory bank SRAM for even (D0-D7) and SRAM for odd (D8-D15)

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Memory Interfaces
3-to-8-line decoder (74LS138)
Decoder and Function Table

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EE353: Introduction to Microprocessor 1431-1432

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Memory Interfaces
A0

Example of Memory Decoding with 3-to-8-line decoder

We have to connect 8 2764-EPROM circuits for 8Kx8 section of memory in the 8088 microprocessor-based system. The addresses selected in this circuit are F0000H FFFFFH
A0 A1
.

2764 EPROM
A12 O0

O7 OE CE

The decoder selects eight 8K-byte blocks of memory for a total capacity of 64K bytes The outputs of the decoder in the figure, are connected to eight different 2764 Ridha EPROM memory devices. Dr. Jemal EE353: Introduction to Microprocessor 1431-1432 25

Memory Interfaces
Example of Memory Decoding with 3-to-8-line decoder
The outputs of the decoder in the figure, are connected to eight different 2764 EPROM memory devices. This figure also illustrates the address range of each memory device and the common connections to the memory devices. all address connections from the 8088 are connected to this circuit. the decoders outputs are connected to the CE inputs of the EPROMs,

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Memory Interfaces
Example of Memory Decoding with 3-to-8-line decoder
the RD signal from the 8088 is connected to the OE inputs of the EPROMs In this circuit, a three-input NAND gate is connected to address bits A19A17. When all three address inputs are high, the output of this NAND gate goes low and enables input G2B of the 74LS138. Input G1 is connected directly to A16. In order to enable this decoder, the first four address connections (A19A16) must all be high. Address inputs C, B, and A connect to microprocessor address pins A15A13. These three address inputs determine which output pin goes low and which EPROM is selected whenever 8088 outputs a memory address within this range to the memory system.

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Memory Interfaces
Example of Memory Decoding with 2-to-8 line decoder 74LS138
1Mbyte Memory Interface (512K Memory Bank + 512 K memory Bank) for 8086

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Memory Interfaces
Example of 8086 Interface (EPROM and SRAM)
To 32KxEPROM (F0000H-FFFFFH) and 8Kx16 SRAM (00000H-03FFFH)

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Other Decoders
The Dual 2-to-4 line decoder (74LS139)
pin-out and the truth table for the 74LS139 dual 2-to-4 line decoder. 74LS139 contains two separate 2-to-4 line decoderseach with its own address, enable, and output connections. A more complicated decoder using the 74LS139 decoder appears in the figure

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