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Kultur Dokumente
PRESENTED BYNEERAJ KUMAR VISHWAJEET KUMAR YOGENDRA KUMAR RAJU KUMAR MRINMOY MANDAL ABHISHEK GUPTA
Contents
1) Objective 2) What is an Electronic lock? 3) Types of Electronic lock 4) Our approach to the Design 5) Finite State Machines(FSM) 6) Field Programmable Gate Array (FPGA) 7) VHDL Overview & Architecture 8) Xilinx Spartan3 Interfacing 8) Results and Analysis 9) Future Scope 10) Conclusion 11) References & Bibliography
Objective
An electronic lock is a simple type of a keyless door lock System which can be accessed by any person knowing its unlock code.
System Design
For the design of an electronic lock we have utilized an 8-bit PISO shift register & FSM (Mealy Machine). The following block diagram represents our design:
Design Description
Our approach to design an electronic lock begin with the design of an 8-bit FSM. Initially an 8-bit sequence is fed to a 8-bit PISO shift register, the output of the PISO is connected to the FSM. Both the PISO and the FSM are synchronized by a single clock. We choose a 8-bit sequence for the PISO and then draw the state diagram of 8-bit manually, from it we have derive the state table and from state table we design a Logic Diagram. We also have written the code for FSM in VHDL and obtained a state diagram which is similar to the manual drawn state diagram.
Logic Diagram
Mealy Machine
y In a Mealy machine, the
outputs are a function of the present state and the value of the inputs as shown in Figure. y Accordingly, the outputs may change asynchronously in response to any change in the inputs.
Moore Machine
y In a Moore machine the outputs
depend only on the present state as shown in Figure. y A combinational logic block maps the inputs and the current state into the necessary flip-flop inputs to store the appropriate next state. y However, the outputs are computed by a combinational logic block whose inputs are only the flip-flops state outputs. y The outputs change synchronously with the state transition triggered by the active clock edge
VHDL Overview
VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits). It is a hardware description language that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. The VHDL language can be regarded as an integrated amalgamation of the following languages: Sequential language + Concurrent language + NetNet-list language + Timing specifications + Waveform generation language => VHDL
cl k
i f (cl k'event and cl k='1') then i f(reset='1')then reg<=d; el se reg<=reg(6 downto 0)& '0'; end i f; end i f; end process; x<=reg(7); present_state clk
ce No clock enable
z<='0';
z<='0';
reset='1' s0
z<='0'; s1
x='0'
@ELSE z <='1'; s7
x='1'
z<='0'; s2 @ELSE s6
z<='0';
s3
s5
z<='0';
@ELSE
When reset is high (reset=1) the input data is loaded into the register.
After making reset low from previous high state we get output high (z=1) when the FSM detects the correct 8-bit input sequence 01101011 and all the registers are reset.
Future Scope
The overall work done by us led to a particular point from where we can move our project to multiple directions:We can design a hardware using the logic diagram implemented in our project We can directly burn the VHDL code on a memory chip using FPGA kit The level of security can also be enhanced by increasing the number of bits in the code The system can be made more secure by connecting the output end of a lock to an online monitoring system
Conclusions
y Our whole concept of the project was to design a lock
system with an 8-bit code using the Mealy Finite State Machine that we have successfully implemented on software. y We have satisfactorily completed most sections of our aimed project. We could not achieve 100 percent because of some unavoidable constraints. y In spite of the constraints we were able to complete most of the portions and we are very satisfied with our work.