A Transformerless Grid Connected Photovoltaic Inverter with Switched Capacitors

Yunjie Gu, Wuhua Li, Bo Yang, Jiande Wu, Yan Deng, Xiangning He
College of Electrical Engineering, Zhejiang University Hangzhou, 310027, P.R. China Email: woohualee@zju.edu.cn
HU U

AbstractIn the transformerless photovoltaic (PV) system, the

common mode ground leakage current may appear due to the galvanic connection between the PV array and the ground, which causes the safety issues and reduces the efficiency. To solve this problem, a novel inverter topology with switched capacitors is proposed in this paper. By connecting one pole of the PV cell directly to the neutral line of the grid, the common mode current is eliminated. Meanwhile, the switched capacitor technology is applied to increase the DC voltage utilization rate. Furthermore, a modified unipolar sinusoidal pulse width modulation (SPWM) strategy is proposed to reduce the pulsating current caused by the charging and discharging operations of the switched capacitors. Also, several optimization principles are put forward to further reduce the pulsating current to improve the efficiency and reliability. Finally, the proposed topology and modulation strategy are verified with simulation and a 250W experimental prototype.

limits the MPPT range of the PV arrays. In this paper, a novel tranformerless inverter topology with the switched capacitors is proposed, which eliminates the common mode current by connecting one pole of the PV cell directly to the neutral line of the grid. Meanwhile, the switched capacitor technology is applied to increase the DC voltage utilization rate, so that the proposed topology requires the same DC input voltage as the full bridge inverter. Furthermore, a modified unipolar SPWM strategy is proposed to guarantee that the switched capacitors are charged every switching cycle in order to reduce the pulsating current, therefore improving the efficiency and reliability. This paper also quantitatively analyzes the maximum current stress on the power devices caused by the charging of switched capacitors, and gives a design guideline to select the capacitances to optimize performance. Finally, the proposed topology and modulation strategy are verified with simulation and a 250W experimental prototype.

I.

INTRODUCTION

Issues such as reliability, high efficiency, small size and weight, and low price are of great importance to the II. PROPOSED TOPOLOGY AND MODULATION STRATEGY conversion stage of PV power generation systems [1]. The proposed topology is shown in Fig 1. The negative Removing the isolation transformer in the PV system can be pole of the PV array is directly connected to the neutral line an effective way to reach this goal [2]. But if the transformer of grid, so the voltage across the parasitic capacitor C and PV is omitted, a galvanic connection between the grid and the PV the ground impedance Z is constantly zero and the common G cell exists, thus the common mode ground leakage current mode current can be eliminated perfectly. C is the input 1 may appear through the stray capacitance between the PV cell capacitor and C is used to generate the minus voltage via the 2 and the ground, which causes the safety issues and reduces switched capacitors method to increase the DC voltage the efficiency [3]. utilization rate. L is the output filtering inductor. The common mode current can be avoided by using The modified unipolar SPWM strategy of this topology is bipolar SPWM in the conventional full bridge inverter. But displayed in Fig 2. During the positive half cycle, S and S 1 3 the switching losses and the volume of the output filter are are turned on and S is turned off, while S and S commutate 2 4 5 relatively large compared with the unipolar SPWM method. at high frequency complementally. The capacitors C1 and C2 The neutral point clamped (NPC) half bridge inverter can also are in parallel. The circuit rotates between state (a) and state be employed to eliminate the common mode current [4]. (b), as shown in Fig 3. However, a much higher DC input voltage is required, which During the negative half cycle, S5 is turned on and S4 is turned off. S1 and S3 commutate at high frequency This work is sponsored by the National Nature Science Foundation of China synchronously and S2 commutates in complement to them. (50907058) and the Power Electronics S&E Development Program of Delta Environmental & Education Foundation (DREM2009001). The circuit rotates between state (b) and state (c). At state (b),

978-1-4244-8085-2/11/$26.00 2011 IEEE

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C2 is charged by C1 and the DC source. If the capacitances of C1 and C2 are large enough, the time constant of the RC circuit formed by C1, C2 and the equivalent resistances in the charging loop is much larger than the switching period, so the voltage across C1 and C2 will change linearly, as shown in Fig 4, and the charging current can be seen as constant within one switching cycle. At state (c), S1 and S3 are turned off while S2 is turned on, and the minus voltage is generated by C2, therefore increasing the DC voltage utilization rate of the inverter. During this state, C1 is charged by the DC input current, and C2 is discharged by the grid current. The voltage across them either increases or decreases linearly.

will guarantee that C2 is charged every switching cycle, so that the current stress is limited. The proper design of the circuits parameters, such as the values of C1 and C2 and the maximum duty cycle, can further reduce the pulsating current. This is described in detail below.

state (a)

Fig 1. Proposed topology.

state (b)

state (c) Fig 3. Circuits operation states. Fig 2. Unipolar SPWM for proposed topology.

The main characteristic of the proposed topology is that pulsating current with much larger values than the output current may appear on S1 and S3 during the negative half cycle because of the charging of C2 at state (b). This pulsating current increases the conduction and switching losses. Moreover, the increased current stress may cause reliability problems for the power semiconductor devices due to their sensitivity to the over current. Therefore, proper methods should be taken to make sure that the current pulse is as small as possible. The modified unipolar SPWM strategy above

vC1 vC2

c b c b c b c b c b c
Fig 4. Capacitor voltage during the negative half cycle.

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III.

PULSATING CURRENT ANALYSIS AND OPTIMIZATION

During the positive half cycle, the proposed topology works just like the full bridge inverter under the unipolar SPWM. During the negative half cycle, the charging of the switched capacitors leads to the pulsating current on the power devices at state (b), resulting in different characteristics from the full bridge. Reducing the maximum current stress on the power switches iSmax is critical in improving the reliability and efficiency. For this reason, iSmax through S1 and S3 during the negative half grid cycle should be analyzed in detail. Supposing that the time constant of the RC circuit formed by the loop of C1 charging C2 is much larger than the switching period, the voltage and current though C1 and C2 can be assumed to be constant in a single switching state. With the small ripple approximation method, the current stress on S1 during state (b) can be derived as following
iS 1 I bus C2 C1 1 d igrid TS d C1 C2 d C1 C2 (1)

iSmax. On the other hand, C1 should not be too small, or else the time constant of the RC circuit formed at state (b) by C1, C2 and equivalent resistances of S1 and S3 will be smaller than TS, so that the small ripple assumption no longer holds true. When C1 is very small, voltage across it will be charged to be very high during state (c), and drops suddenly when S1 and S3 turn on, resulting in high pulsating current on the devices. This situation should be avoided.
As a trade off, principles below can be used in optimizing the capacitances

C1 0.5 C1 C2 C1C2 ( RS 1 RD 3 RC 2 RC1 ) TS C1 C2

(4)

where RC1 and RC2 are the equivalent serial resistances (ESR) of C1 and C2, while RS1 and RD3 is the conduction resistances of S1 and anti paralleled diode of S3. IV. SIMULATION AND EXPERIMENTAL VERIFICATION

where d is the duty cycle and is defined as Time when S 2 is on d ; igrid is the output current and its Switch period reference direction is shown in Fig 1; igrid TS is the small
ripple approximation of igrid, and TS is the switching period; Ibus is the average value of the DC input current from the PV array. Neglecting the phase shift caused by the output inductor, igrid TS and d can be written as synchronous sinusoidal functions
igrid TS I grid sin( t )

The proposed strategy is verified with the Saber simulation. The switching frequency is 20 kHz, the ESRs of C1 and C2 and the conduction resistances of all power devices are set as 0.05. The forward voltage of all power devices are 0.7V. The DC input voltage is 400V, the root mean square (RMS) value of the grid voltage is 220V, and the output power is 250W. The simulated waveforms of the output current and the current stress on S3 under different values of C1/(C1+C2) are given in Fig 5. It can be seen that iS3 is smaller when C1/(C1+C2)=0.33. This result verifies the optimization principles proposed in (4).
igrid 0.5A/div

d Dm sin(t )
where Igrid is the amplitude of output current and Dm is the maximum duty cycle. Apparently, the maximum value of iS1 comes when sin( t ) 1 , and can be simplified as below

iS 1max

C1 1 Dm 1) I grid ( 2 Dm C1 C2

(2)
iS3 2A/div 10ms/div

Similarly, it can be deduced that

iS 3max

C1 1 Dm 1) I grid I grid ( 2 Dm C1 C2

(3)

(a) C1/(C1+C2) =0.33 (C1 = 470F, C2 = 940F)

From (2) and (3), it can be seen that iS1max and iS3max are affected by three parameters, namely Igrid, Dm and C1/(C1+C2). Based on the results above, proper optimization method can be taken to reduce iSmax.

Igrid is determined by the output power and cannot be alternated. Dm=Vgrid /Vbus, so a higher Vbus is preferred to reduce iSmax. C1/(C1+C2) can be set by the designer. On one hand, C1/(C1+C2) should be as small as possible to reduce

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igrid 0.5A/div

vgrid 100V/div

igrid 1A/div

iS3 2A/div 10ms/div

10ms/div

(b) C1/(C1+C2) =0.67 (C1 = 940F, C2 = 470F) Fig 5. Simulated waveforms of output current and current stress on S3 with different ratio of C1/(C1+C2).

Fig 6. Experimental waveforms of igrid and vgrid.

Also, a 250W experimental prototype is built to further verify the functionality of the proposed circuit. In the prototype, the LCL output filter is used to decrease the output current ripples. The detailed parameters and components used are as following: Input Voltage (Vbus): Grid Voltage (Vgrid): Output Power (Pout): Grid Frequency (fgrid): Switch Frequency (fs): Parasitic Capacitance (CPV): Power Switches (S1~S5): LCL Filter Parameters: Switched Capacitors: 400V 220V(RMS) 250W 50Hz 20kHz 75nF IKP15N60T 15mH, 0.34F, 1mH C1=470F, C2=940F

iS3 1A/div

vS3 200V/div 50 s /div

Fig 7. Current and voltage stress on S3.

The experimental waveform of the inverts output current into the grid is displayed in Fig 6. The total harmonic distortion (THD) is 2.97%, and the power factor is 0.999. The measured output power is 246.3W. The current and voltage stress on S3 is shown in Fig 7. The spiky current during turning off is caused by the reverse recovery of the anti paralleled diode of S3. The effects of different circuit parameters on the maximum current stress on the power devices are demonstrated in Fig 8. The current stress on S3 under different ratio of C1/(C1+C2) is compared in Fig 8 (a) and (b). In (a), C1/(C1+C2)=0.33, while in (b), C1/(C1+C2)=0.67. All other parameters are the same, including the output power and the input voltage. The result shows that the current stress is smaller when C1/(C1+C2)=0.33, verifying the theoretical analysis above. The current stress on S3 under different values of Vbus is compared in Fig 8 (a) and (c). In (a), Vbus=400V and the output power is 250W, while in (c) Vbus=380V and the output power is only 235W. It can be seen that the current stress shown in (c) is larger although the output power is smaller. This demonstrates the sensitivity of iSmax to Vbus/Vgrid.

iS3 2A/div 4ms/div

(a) C1/(C1+C2)=0.33 (C1 = 470F, C2 = 940F), Vbus = 400V

iS3 2A/div 4ms/div

(b) C1/(C1+C2) =0.67 (C1 = 940F, C2 = 470F), Vbus = 400V

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iS3 2A/div 4ms/div

(c) C1/(C1+C2) =0.33 (C1 = 470F, C2 = 940F), Vbus = 380V Fig 8. Current stress on S3 under different conditions.

V.

CONCLUSIONS

A novel transformerless inverter topology with the switched capacitors is proposed for the grid connected PV power generation system. Only five power switches are required in the proposed PV inverter topology. The common mode current is eliminated perfectly. The DC input voltage required is the same as the full bridge inverter. A modified unipolar SPWM strategy is proposed for the topology, enabling it to output three voltage levels. It is also guaranteed that C2 is charged every switching cycle under this SPWM strategy, so that the current pulse on the power devices caused by the switched capacitors is reduced. Furthermore, based on the quantitative analysis of the devices current stress, the principles for optimizing the capacitances of the switched capacitors C1 and C2 are given. The simulation and experimental results are provided to verify the theoretical analysis. REFERENCES
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Gonzalez R, Gubia E, Lopez J, Marroyo L, Transformerless SinglePhase Multilevel-Based Photovoltaic Inverter, IEEE Transactions on Industrial Electronics, vol. 55, no. 7, pp. 2694-2702, 2008. Lopez O, Freijedo F.D, Yepes A.G, Fernandez-Comesaa P, Malvar J, Teodorescu R, Doval-Gandoy J, Eliminating Ground Current in a Transformerless Photovoltaic Application, IEEE Transactions on Energy conversion, vol. 25, no. 1, pp. 140-147, 2010. Araujo S.V, Zacharias P, Sahan B, Novel Grid-Connected NonIsolated Converters for Photovoltaic Systems with Grounded Generator, in Power Electronics Specialists Conference, 2008, pp. 58-65. Lopez O, Teodorescu R, Doval-Gandoy J, Multilevel transformerless topologies for single-phase grid-connected converters, in IEEE Industrial Electronics, IECON 2006-32nd Annual Conference on Digital Object Identifier, 2006, pp. 5191-5196.
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