Z8 Mev Test Mode

~ Zilog

Application Note

June 1982

Copyright 1982 by Zilog, Inc. All rights reserved. No part of this publication may be reproduced without the written permission of Zilog, Inc. The inforlll8tion in this publication is subject to change without notice.

Z8 MCU Test Mode

~ Zilog
This application note is intended for use by those with either a ZB601 or a ZB611 Microcomputer device. It is assumed that the reader is familiar with both the ZB and its assembly language, as described in the following documents:

Application Note

June 1982
The second problem is: since the Test Mode requires that Port operate only in the Address/Data bus mode, how are the other Port 1 modes of operation tested? To solve this problem, an on-chip Test ROM is provided for execution while in Test Mode. The program in the Test ROM checks the other modes of Port 1: input, output, with handshake control, and without handshake control. rigure 1 compares normal and Test Mode operations in the ZB. (In both normal and Test Mode, program execution begins at address OOCH.)

ZB Technical Manual (Reset Section) ( 03-3047-02) ZB ramily ZB601, ZB602, ZB603 Product Spec (00-2037-AO) ZB ramily ZB611, ZB612, ZB613 Product Spec ( 00-203B-AO) ZB PLZ/ASM Assembly Language Programming Manual (03-3023-02)

This note briefly discusses the operation of Test Mode, which is a special mode of operation that facilitates testing of both ZB devices that incorporate an internal program ROM (ZB601, ZB611). There are two problems associated with testing a ZB with an internal program ROM; the solutions are presented below. The first problem is: how can the device be tested with standard microprocessor automatic test equipment? To solve this problem, Test Mode causes the ZB to fetch instructions from Port 1 while it is in the external Address/Data bus mode, instead of fetching instructions from the internal Program ROM. Diagnostic test routines are then forced onto this external bus from the test equipment in the same manner as with microprocessor testing.

ONCHIP
PROGRAM ROM

. . .---OOCH
figure 1.

TEST MODE

CoeIparison of Norellll and Test "'des

2242001

Test Mode csn be entered immedistely after reset by driving the RESET input (pin 6) to a voltage of Vee + 2.5 V. (See the Reset section of the Z8 Technical Manual for a description of the Reset procedure.) rigure 2 shows .the voltage waveform needed for Test Mode. After entering Test Mode, instructions are fetched from the internal Test ROM, which is programmed with Port 1 diagnostic routines. The Z8 stays in Test Mode until a normal reset occurs.

The program listing in the ROM is included at the end of this document. Program Listing A (Internal Test ROM Program) is mask programmed into the internal Te.st ROM of the Z8601. Program Listing B (External Test Program) is an example of a program that could be executed while in Test Mode. It was written as a compliment to the internal Test ROM program, to check the Port input and output functions. To test the other functions of the ZB., the user must execute other programs developed for testing. The interrupt vectors in the Z8601 Test ROM point to the locstions in external memory %800, %803, %806, %809, %80e, %80f. The interrupt vectors in the Z8611 Test ROM point to the locations in external memory %1000, %1003, %1006, %1009, %100e, %100f. This allows the external program to have a 2- or 3-byte jump instruction to each interrupt service routine. Programs that are run in Test Mode can use an LDE instruction for accessing the Test ROM. The LDe instruction can be used for accessing the program ROM.

VR.

RESET PIN

VRL---.1

Note the maximum ramp for application of + 7.5 VDC to RESET pin. After a minimum of 8 XTAL elK cycles, the RESET voltage can be relaxed to VRH.

rigure 2. Progrllll Listing A. 28ASM LaC

Test MOde MBve ror. Internal Test ROM Progr_ STMT SOURCE STATEMENT
1

4.0 OBJ CODE

2
4

28 TEST ROM ROUTINE FOR VERIFYING PORT 1 1/0, WITH AND WITHOUT H.S.

5 TESTROM MODULE
8 $.SECTION PROGRAM 9 $ABS.O lllTERNAL 10 RUPT VECTOR ARRAY [6 WORD]:= 11
6 7

P 0000 0800 P 0004 0806 P 0008 080C

0803 0809 080F

P OOOC P OOOC E6 P OOOF 8D 0012 99 0014 A9 0016 48 P 001P F3 p 001A 61 P 00lC 58 P DOlE E3 P 0020 E3 P 0022 88 P 0024 C9 p 0026 8D F8 96 0812 F8 F7 E3 DE ED E3 6B 7B E3 F8 0831

p p p

12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 31 32 33
22

[S800 S803 S806 S809 S80C S80F] $SDEFAULT INTERNAL TEST PROCEDURE ENTRY $ABS sooe LD P01M #S96 JP EXT STARTl : LD P01M R9 LD P3M Rl0 LD R4 SE3 LD @R13 R14 COM @R13 LD R5 SE3 LD R6 @Rll LDR7@Rll LD R8 SE3 LD P01M R12 JP VERIFYl Pl&PO=EXT MEM,STK=IN,NORMAL ! JUMP TO EXTERNAL TEST CODE ! START OF Pl 110 TEST ! SET H.S.& P2 PU ACTIVE TEST RDY=l,DAV=l ! WRITE PORT ! WRITE PORT ! TEST RDY=O,DAV=l ! READ PORT & STUFF DATA DITTO ! TEST RDY=l,DAV=l ! CONFIGURE FOR EXT ! JUMP TO VERIFY ROUTINE

2242002

Progr_ Listing A.

Internal Teat ROM Progr_

(continued)

P P P P P P P P P

0029 002B 002D 002E 0030 0031 0033 0035 0038

B9 99 lE F9 lE 98 C9 8D

F7 F8 F8 El F8 086D

311 START2: LD P3M Rll LD P01M R9 35 INC Rl 36 LD P01M R15 37 INC Rl 38 LD R9 JEl 39 110 LD P01M R12 41 JP VERIFY2 112 END TEST

START TEST NO H.S. I SET Pl TO INPUT I READ & WRITE Pl AS INPUT I SET Pl TO OUTPUT I READ & WRITE PI AS OUTPUT I SAVE RESULTS IN R9 I Pl&PO=EXT,STK IN,NORMAL ! JUMP TO VERIFY #2 ROUTINE

Progr_ Listing B.

Extema! Test Progr_

P 0800 P P P P P P P P P P P P P P P P P P P P P P P P 0800 0803 0806 0809 080C 080F 0812 0813 0815 0817 0819 081C 081E 0820 0822 08211 0826 08211 082A 082C 082E 0831 08311 0837 aD 8D 8D 8D eD 8D 8F 31 2C 3C E6 IIC 5C 9C AC BC CC DC FC EC E6 E6 8D 0800 Ofl03 0806 0809 080C 080F 00 FF FF F6 88

FF

00 86 39 02 96 01 86 AA 10 10 11 40 0012

P 0831 P P P P 0831 0833 0835 0838 DC BC E6 66 02 01 F6 Ell

00 50

117 48 49 50 51 52 53 511 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 711 75 76 77 78 79 80 81 82 83 811 85 86 87 88 89

INTERNAL SETUP PROCEDURE ENTRY $ABS J800 VECTl VECT2 VECT3 VECT4 VECT5 VECT6 EXT: JP JP JP JP JP JP VECTl VECT2 VECT3 VECTII VECT5 VECT6

DI SRP UOO LD R2 UFF LD R3 UFF LD P2M UFF LD RII U88 R5 noo R9 U86 Rl0 U39 Rl1 U02 R12 U96 R13 nOl R15 U86 Rl11 UAA Jl0 Ul0 Jll n40 STARTl

LD LD LD LD LD LD LD LD LD LD JP END SETUP

INITIALIZE P2 ! DITTO! SET P2 TO INPUT SET P2<>P1 MUX,P3 GRP B MUX ! ALSO DUMMY ADDRS HIGH BYTE ! DUMMY ADDRS LOW BYTE ! Pl OUTPUT MODE VALUE ! Rl0 SETS H.S.MODE & P2 PULLUPS Rll POINTS TO P2 FOR PASSl I R12 SETS P01M TO EXT MEM,ETC. R13 POINTS TO P1 FOR PASS1 ! SAME AS R9 ! DATA LOADED TO TEST PORT ! RDY/DAV RESULT PASS 1 ! DITTO! END SETUP--JUMP TO TEST START

INTERNAL VERIFY PROCEDURE ENTRY $ABS J83l VERIFYl :LD R13 LD Rll LD P2M TCM RII U02 nOl noo U50 R13 POINTS TO P2 FOR PASS2 ! Rll POINTS TO Pl FOR PASS 2 I SETS P2 FOR OUTPUT ! FROM HERE TO THERE WE VERIFY ! TEST RESULTS FOR 1/0 WITH H.S. BOTH PASS 1&2 I

Progr_ Listing B.

External Test Progr_

(continued)

P P P P P P P P P P P P P P P P P P

083B 083E 0841 0844 08117 084A 0811D 0850 0853 0856 0/159 085C 085F 0862 0865 0867 086A 01l6D

ED 64 ED 74 ED A6 ED A6 ED 66 ED A6 E6 E6 9C 6D 8D A6

0880 10 E5 0880 11 E5 0880 E6 AA 0880 E7 55 0880 E8 50 0880 E9 86 10 40 11 10 8E 0012 0029 E9 57 0890

P 0870 6D P 0873

P 0890 0890 8B 0892 FE

0!l80 0880 8B 0882 FE

90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132

JP NZ FAIL TCM R5 ~10 JP NZ FAIL TM R5 ~11 JP NZ FAIL CP R6 UAA JP NZ FAIL CP R7 1155 JP NZ FAIL TCM R8 1150 JP NZ FAIL CP R9 n86 LD ~10 n40 LD ~11 1110 LD R9 n8E JP EQ START1 JP START2 VERIFY2:CP R9 IS57 JP EQ PASS END VERIFY INTERNAL TPASS PROCEDURE ENTRY tABS PASS:JR PASS END TPAss INTERNAL TFAIL PROCEDURE ENTRY tABS FAIL:JR FAIL END TFAIL END TESTROM

IS THIS PASS1? I RDYIDAV RESULT PASS 2 I DITTO I P1 IS GOING TO BE AN OUTPUT I PASS1 SUCCESSFUL--TRY PASS2 I PASS2 SUCCESSFUL--TEST NO H.S. CHECK RESULT OF 1/0 NO H.S.TES

~890

~880

Assembly complete

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