LADDER LOGIC

There are various methods of programming a PLC. Two of these inc ude Ladder Logic and !unction " oc# Diagrams. The choice of which method is dependent on whether the operation $eing automated is machine contro or process contro oriented. Ladder Logic is the method of choice in the case of machine contro and !unction " oc# for process contro . Ladder Schematics E ectricians are fami iar and comforta$ e with adder schematics. These diagrams depict two vertica ines ca ed rai s. The rai s provide power to the circuitr% of the schematic. The power can $e AC or DC and the vo tage ma% var% depending on the re&uirements. 'tandard a$e ing for rai s is L( and L). Circuitr% is p aced $etween the rai s connecting the two power ines. These individua ines are referred to as rungs. The circuitr% is t%pica % ver% specific for adder schematics. !or instance* in the fo owing diagram note the first rung consists of a start $utton that is actua % a momentar% switch.

Inputs
L1

Outputs
L2

Ladder Rung

Ladder Rai

!igure (+. Ladder 'chematic.

Rungs are composed of inputs and outputs. If an imaginar% ine is drawn down the midd e of the previous diagram a the inputs ,switches* etc.- are ocated to the eft. Outputs , ights* etc.- are ocated to the right. Locating a inputs on the eft side of a rung and a outputs on the right is good design practice $ut not re&uired. The atest software versions a ow inputs and outputs to $e intermi.ed on a sing e rung.
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Ladder Diagrams Ladder diagrams are ver% simi ar to adder schematics. A adder diagram is a s%m$o ic representation of an e ectrica circuit. That is* specifics concerning switches* etc. are rep aced with generic s%m$o s $ut the same functiona it% is represented. The primar% factor driving the adder ogic design was the re&uirement to ma#e the s%stem as fami iar as possi$ e to the primar% users/ e ectricians. Therefore* the s%m$o s uti i0ed c ose % resem$ e ,if not identica to- schematic s%m$o s for e ectrica devices. The fo owing diagram is the adder ogic e&uiva ent of the previous adder schematic.
Input 4odu e Re a% Coi E&uiva ent Output 4odu e

Rung 1 Rung 2

Rung 3

G R Re a% Contact E&uiva ent !igure (1. Ladder Diagram with I2O detai inc uded.

3ote each device from the adder schematic has $een rep aced with an e&uiva ent s%m$o . The resu t is a co ection of input and output s%m$o s that represent the genera operation of the device $ut not how that action is achieved. A so note that representing a switch or output device generica % means the adder diagram simp % represents the function of a switch or motor $% whether it is c osed2open or off2on* respective %.

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Outputs and Inputs/Sensors Outputs from a PLC are referred to as coi s on a adder diagram. A coi ma% represent a motor* ight* pump* counter* timer* re a%* etc. The fo owing disp a%s how a coi is represented in a adder diagram.

!igure (5. Coi representation in a adder diagram.

Inputs2'ensors to a PLC are referred to as Contacts and ma% consist of switches* $uttons* etc. Contacts $egin in one of two states norma % open or norma % c osed. A graphica representation of a norma % open and c osed contact is depicted as it wou d appear in a adder diagram.

!igure (6. 3orma % Open and C osed representation in a adder diagram.

These contacts have an initia and fo ow7on state. The states are $est descri$ed if the contact is thought of as a switch. 3orma % open descri$es a switch whose initia state is open. Therefore* with power app ied to $oth rai s of a adder diagram the initia state of a norma % open switch wou d not comp ete the connection. 8hen activated the switch changes to its fo ow7on state. That is* the switch c oses comp eting the connection $etween the adder rai s. 'witch positions for $oth states are shown in the fo owing !igure.

Initia 'tate

!o ow9On 'tate

!igure (:. The 3O and 3C schematic representation for a imit switch.

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3ote that simp % app %ing power to the rai s wi not necessari % resu t in a fo ow7on state for a contact. The DC e&uiva ent circuit and adder diagram for a norma % open contact fo ows/

3orma % C osed descri$es a switch whose initia state is c osed. 8hen activated the switch changes to an open state. The fo owing diagram depicts a norma % c osed push $utton and how it wi operate when connected to a ight and $atter%. If the $utton is not pressed then the circuit is comp ete and the ight is on. ;owever* if the $utton is pressed or activated the circuit is $ro#en and the ight is off.
Push$utton
Push$utton Light

'ing e Input _ +
3ot Pressed ,(Pressed ,>Truth ta$ e On ,(Off ,>-

!igure (<. Circuit schematic of a 3C push$utton and ight and the circuit=s truth ta$ e. The ight wi $e on ,initia state- if the push$utton is not pressed.

This circuit is represented in a adder diagram as fo ows/

If the push $utton* in the diagram* is a norma % open contact then the initia state wou d $e an incomp ete circuit and the ight wi $e off.
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8hen pressed the $utton changes states from open to c ose and the circuit is comp eted there$% powering the ight. Fundamental Logic 'ituations wi arise that re&uire two or more events to occur prior to activation of a coi ,output device-. That is* switch A and switch " must $oth $e c osed ,or $e true- for the ight to turn on. The re ation $etween switches A and " and the ight is referred to as an ?A3D= function. The fo owing depicts a circuit* truth ta$ e* and the ogica gate for this ?A3D= re ationship. The truth ta$ e shows a the switch position com$inations and the resu ting outcome for the ight. The A3D gate is a graphica method for representing A3D situations in a ogic diagram.

!igure )>. Circuit schematic with an A3D configuration.

The end resu t is ever% contact A3Ded together must $e c osed for the ight to activate. The corresponding adder diagram for the A3D scenario is/

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A pro$ em statement depicting an A3D situation might $e/ A dri press re&uires the operator to have one hand on each switch $efore the machine wi activate. 'witch A and " represent the hand7 activated switches and the ight turning on simu ates the dri press activation. Launching of nuc ear missi es is a so an A3D scenario. Two #e%s must $e turned simu taneous % to aunch. 8hat is another A3D scenario@ Pro$ em statements wi sometimes inc ude situations ca ing for an output to $e triggered $% an% num$er of individua or unre ated events. That is* either switch A or " must $e c osed ,or $e true- for the ight to turn on. The re ation $etween switches A* " and the ight is referred to as an ?OR= function. The fo owing depicts a circuit* truth ta$ e* and the ogica gate for this ?OR= re ationship.

!igure )(. Circuit schematic with an OR configuration.

Reviewing the OR truth ta$ e indicates the differences $etween ORs and A3Ds. An% of the OR options is sufficient to activate the ight $% itse f or in com$ination with an% of the other or a of the OR options. 8hen depicting OR scenarios in adder diagrams each option is referred to as a $ranch.

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The corresponding adder diagram for the previous OR scenario is/

A pro$ em statement depicting the OR situation might $e/ 'topping a garage door in an emergenc% situation ma% $e accomp ished $% either pressing the stop $utton or $% p acing an o$Aect in the path of the e ectric e%e. 'witch A represents the stop $utton* switch " represents the e ectric e%e sensor and the ight represents the garage door. If the ight is on the garage door is stopped. 8hat are some other OR scenarios@ Ladder Diagram Rules (. A adder diagram is read i#e a $oo#B from eft to right and from top to $ottom ). The vertica power ines or rai s ma% $e a$e ed L(* L) or the% ma% $e a$e ed C(* C) when the vo tage potentia is derived from a transformer D. Devices or components are shown in order of importance whenever possi$ e. 'top $uttons shou d $e given a higher order of importance and therefore $e shown ahead of other devices. +. E ectrica devices are shown in their norma condition. The norma condition of e ectrica diagrams is the circuit deenergi0ed and with no e.terna forces such as pressure* f ow* etc. acting on the device. 1. Contacts associated with re a%s* timers* motor starters* etc. a wa%s have the same num$er or etter designation as the device that contro s them. This ho ds true no matter where the contacts appear in the circuit. !or e.amp e* in the adder diagram presented on page (1* note the coi a$e ed 4 on rung (. Then note the two contacts in rungs ) and D $oth have an 4 $e ow them. This signifies these contacts as $eing contro ed $% the coi in rung (.

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5. A contacts associated with a device change state when the device is energi0ed. In regard to the previous e.amp e when the coi in rung ( is activated then an% contact contro ed $% that coi wi change from its current state to the fo ow7on state. Therefore* in rung ) the 3orma % C osed ,3C- contact wi open. The 3orma % Open ,3O- contact in rung D wi c ose. 6. Devices that perform a 'TOP function are norma % p aced in series on a rung. :. Devices that perform a 'TART function are norma % p aced in para e or in a $ranch configuration. Branch Instructions There are often occasions when it is desired to turn on an output for more than one condition. !or e.amp e* the door$e shou d sound if either the front or rear door $utton is pushed. The OR option created $% the front or rear door $utton activating the $e is produced in adder diagrams through a $ranch. The $ranch produces two paths that ma% activate the door$e .

!igure D(. An Or $ranch for front and rear door $e operation.

If the front door switch ,A- is c osed* e ectricit% can f ow to the $e . Or if the rear door switch ,"- is c osed* e ectricit% can f ow through the $ottom $ranch to the $e . That is* if at east one of the para e $ranches forms a true ogic path* the run ogic is ena$ ed. "ranches ma% $e composed of sing e or mu tip e components. 3ote in the fo owing the first $ranch consists of an A3D function and the ower $ranch is simp % a sing e component.

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!igure D). A compound $ranch configuration.

Coi D is activated when either A and " OR C OR A* "* A3D C are c osed. On some PLC mode s* $ranches ma% $e uti i0ed for $oth inputs and outputs on a rung.
C D E

!igure DD. An OR configuration for $oth inputs and outputs.

Para e output $ranching a ows a sing e input to activate mu tip e outputs simu taneous %. 3ote that if such a configuration is not permitted $% the PLC design the adder diagram ma% $e reconfigured to accommodate the needed functiona it%. Redesign the adder using the space $e ow.

4E4ORE ORGA3IFATIO3

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4emor% organi0ation refers to how certain areas of memor% in a PLC are uti i0ed. 3ot a PLC manufacturers organi0e memor% in the same manner $ut even so the princip es invo ved are the same. Ph%sica addressing* discussed in a previous section* is the a$i it% to read data from a specific modu e termina or write information to a specific modu e termina . 8hen information is read from a contact or input it is stored in memor%. A portion of memor%* the input image map* is designated to store this input information. Each input t%pica % has* at a minimum* a sing e $it designated to store its information.

!igure )). Associating input and output data with its corresponding memor% ocation.

Data resu ting from ogica ana %sis $% the CPG is stored in memor% a$e ed as the output image map. !rom this point the information is transferred to a designated output modu e and then to the particu ar fie d device. This e.amp e high ights how portions of memor% are designated for particu ar operations. The memor% organi0ation or memor% map for a 4icroLogi. PLC is depicted $e ow. Each segment is assigned a specific function or assists in the performance of a function. !or instance* the Timer fi e stores a information re ated to an% timer uti i0ed $% the PLC. This inc udes status* contro * and $it information. Timer information wi not $e stored in the counter fi e. Gti i0ing memor% in this manner provides for speed% storage and retrieva of data. ;owever* the pre7assigned $ oc#s of memor% can

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!igure )D. 4emor% a ocation for the 4icro Logi. (>>>.

ead to inefficienc% in cases where a the memor% space is a ocated $ut more is needed. There might $e free memor% in the counter $ oc# $ut this cannot $e used since it is designated on % for counters. 8hen referencing timers and counters* each wi $e identified as T+.> and C1.>* respective % for the 4icro ogi. (>>>. The T+ corresponds to the fi e ocation. The > identifies the specific timer instance. Each instance has mu tip e pieces of information associated with it such as timer status and data information. 4emor% uti i0ation or assignment in the Contro Logi. ref ects the schemas incorporated into ever%da% persona computers. 8hen a timer or counter is added to a adder diagram the memor% addresses are not automatica % se ected from a predefined block. 4ost recent % designed PLCs wi reserve a segment of memor $ased on the needs of the sing e device2instruction set. The memor% segment is arge enough to store a the information re ated to the device2instruction. !or instance* a timer wi re&uire memor% to store $it status and contro $it information so the predefined segment inc udes ocations for each. This is ver% simi ar to the 4icroLogi. memor% schema uti i0ation e.cept the predefined segment can reside an%where in the RA4 of the PLC. The resu t is memor% segments for timers* counters* etc. interspersed throughout the RA4. This produces a much more efficient use of memor% $ut re&uires more comp e. storage and retrieva a gorithms in comparison to the 4icroLogi. scheme.

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'CA33I3G PROCE''
The PLC=s CPG monitors the status of a inputs. It ta#es these va ues and energi0es or de7energi0es the outputs according to the adder diagram2user program. This is referred to as scanning. A scan does not consist of a PLC e.ecuting adder diagrams rung $% rung. Instead the PLC performs an I2O and program scan. The I2O scan transfers data to and from the output and input modu es* respective %. The information is transferred in the form of $its and stored in image ta$ es. Remem$er image ta$ es are $ oc#s of memor% designated to store the input and output $it state. The input and output modu es are the portion of the PLC that interface with the outside wor d. The actua $ridge $etween the ph%sica wor d and the interna wor d of the PLC is the optica iso ation circuitr%.
Memo&+
n!ut "ata n!ut $ut!ut E%amine "ata Retu&n &esu#t $ut!ut "ata

n!ut Mo"u#es

$ut!ut Mo"u#es

'&og&am

C(eck)com!a&e)e%amine s!eci*ic con"itions

Take some action

!igure )+. Interna view of PLC scan c%c e.

The scan $egins $% transferring data from the output image ta$ e to the output modu e. This is fo owed $% the PLC ta#ing a snapshot of the current input signa s registered in the input modu e. This snapshot

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!igure )1. Data f ow from the PLC to a contro ed output.

!igure )5. Data f ow into the PLC from an input source.

of data is transferred from the input modu e to the input image ta$ e. The ne.t phase is the program scan. The CPG uti i0es the snapshot of the input image ta$ e to perform a ogica eva uation via the adder ogic. Resu ts of this ogica eva uation are written to the output image

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map during the fina step of the program scan c%c e. If a coi is true ,active* high- a one is written to the corresponding $it in the output image ta$ e* otherwise a 0ero is written to the $it denoting the contact as fa se ,inactive* ow-. Therefore* the CPG $ases its decisions on states of the inputs prior to entering the program scan. If an input is changed during the scan it wi not register unti the ne.t scan c%c e. Comp etion of the program scan ends a sing e scan c%c e and then the process $egins again with the I2O scan.

n!ut Mo"u#e n!ut "e,ice

'&ocesso& Memo&+ Data n!ut mage ta-#e $ut!ut mage ta-#e

$ut!ut Mo"u#e $ut!ut "e,ice

)3 $)5 '&og&am

)3

$)5

!igure )6. Ph%sica and interna view of PLC scan c%c e .

'canning 'teps (. Transfer output map $its to the output modu e ,I2O scan). Input modu e signa s are fro0en i.e. snapshot is ta#en ,I2O scanD. Transfer input modu e $its to the input image map ,I2O scan+. The ne.t phase is initiated $% the CPG reading a data $its current % in the input image map ,Program scan-

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1. CPG eva uates2performs adder ogic on current set of data $its ,Program scan5. Resu ts of eva uation transferred to the output image map ,Program scan-

!AIL7'A!E DE'IG3
!ai 7'afe Design is the procedure of programming to assure safet% of the operator and processes. An e.amp e of this t%pe of design is re&uiring two hand switches and a part presence sensor to $e c osed $efore a machine wi activate. In this scenario the design ensures there is a part in the machine and $oth hands of the operator are in a safe ocation. Consider the se ection of e ectrica connections from a !ai 7'afe standpoint. If wires are cut or connections fai * the e&uipment shou d sti $e safe. !or e.amp e* if a norma % c osed stop $utton is used* and the connector is $ro#en* it wi cause the machine to stop as if the stop $utton has $een pressed. !ai 7'afe Design ru es of thum$ for se ecting 3O or 3C devices are as fo ows/ 3O 9 8hen wiring switches or sensors that start actions* use norma % open switches so if there is a pro$ em with the switch the process wi not start. 3C 9 8hen wiring switches that stop processes use norma % c osed switches so if the% fai the process wi stop. !ai 7'afe a so inc udes scenarios guaranteeing notification of s%stem fai ure. ;ousing a arms uti i0e c osed circuits to indicate that a door or window is in the secure position. 'o if the window or door is opened the circuit is $ro#en and the a arm s%stem registers this as unsecured. Additiona %* this method of design ensures that circuit fai ures wi $e detected. 8ire ess a arm s%stems depend on $atteries for each individua door or window. If the $atter% dies then the fai ure of the circuit is registered $% the a arm s%stem prompting investigation. If an a arm s%stem uti i0es open circuits to indicate a secured door or window and c osed circuits as unsecured then fai ure of a circuit ma% not $e detected. Design of a fai 7safe s%stem re&uires consideration of these a these scenarios.
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