Elimination of Spurious Noise due to Time-to-Digital Converter

Robert Bogdan Staszewski1 , Khurram Waheed, Sudheer Vemulapalli, Prashanth Vallur, Mitch Entezari, and Oren Eliezer Texas Instruments Inc, Dallas, TX 75243, USA 1 Technische Universiteit Delft, The Netherlands
Abstract We propose an improved architecture of a multiGHz all-digital phase-locked loop (ADPLL) that is free from spurious tones caused by the nite resolution of the phase detection process. These tones appear at the RF output when the synthesized frequency is very close to the integer-N multiple of the reference frequency. The phase detection in the ADPLL is performed by a time-to-digital converter (TDC), whose typical resolution of 1030 ps is sufcient for the GSM-quality RF operation. While the TDC quantization noise does not normally produce signicant phase noise degradation, the near-integerN condition makes the loop ill-behaved such that the total quantization energy falls close to dc and will not get ltered by the loop lter. The proposed solution of randomizing the TDC quantization noise is veried through comprehensive and detailed simulations.

as shown in Fig. 1, the TDC produces a digital integer Q proportional to the timing difference between the signicant edges of the reference clock (FREF) of frequency fR and variable clock (CKV) of frequency fV , but with a certain quantization: Q = round( tR tV tr ) = round( ) tres tres (1)

I. I NTRODUCTION In the past several years, there has been a great deal of research on applying digitally-intensive and digital signal processing (DSP) approaches to efciently implement RF wireless circuits in deep-submicron or nanometer-scale digital CMOS technologies. In particular, the RF frequency synthesis has seen a successful adoption of an all-digital PLL (ADPLL) [1], [2], [3], [4], in which the phase/frequency detector with the charge pump and the voltage-controlled oscillator of the traditional PLL have been replaced with a time-to-digital converter (TDC) and a digitally-controlled oscillator (DCO), respectively.
CKV D(1) D(2) D(3) D(4) D(L)

where, tR and tV are the signicant edge timestamps of the reference and variable clocks, respectively, tres is the TDC timing resolution, and round is the quantizing operation of rounding to the next (or, alternatively, previous) integer. Similarly, a stand-alone DCO takes a signed digital integer tune, and deviates the RF oscillating frequency by f with the gain of KDCO : f = KDCO tune (2)

FREF Q(1) Q(2) Q(3) Q(4) Q(L)

tV FREF CKV TV

tR

t r

t buf or tinv
TV

Fig. 1. TDC: simplied schematic view (top); signal timing (bottom). The raw Q output is converted into binary word represented as tr . The delay elements are inverters but shown as non-inverting buffers for simplicity sake.

An undesirable consequence of nite-resolution converting functions is the introduction of quantization noise. As such,

The DCO quantization comes from the fact that its openloop frequency resolution is KDCO in units of Hz/LSB. Typical resolution ranges as achieved in [1], [2], [3], [4] are tres = 1530 ps and KDCO = 1225 kHz/LSB, and are obtained merely through the ne lithography and excellent device matching of the advanced CMOS fabrication process with no particularly special design or layout techniques. Fig. 1 illustrates an example of such simplicity. The above quantization values are ne enough to generally guarantee mobile phone quality of RF transmit and receive operations. Only a very small fraction of the RF channels would exhibit an ill-conditioned frequency relationship in which the quantization energy does not satisfy the white-noise assumption and can produce performance degradation larger than expected from the well-behaved distribution. For example, in exact or near integer-N channels (N = F CW = fV /fR ), the quantization energy of TDC is mostly concentrated in tones close to dc. The direct ADPLL frequency modulation further causes a continuous shift of these tones in correspondence to the modulation commands. These low-frequency tones, if they fall within the pass-band of the PLL, cannot be attenuated by the loop lter and, consequently, they modulate the DCO output, thus distorting the intended modulation. If the spurious tones fall between 300-700 kHz, then they affect the narrowband spectrum mask, potentially exceeding the limits dened for it for GSM/EDGE transmitters. Similar parasitic DCO modulation for an ADPLL-based GMSK transmitter operating

978-1-4244-5484-6/09/$26.00 2009 IEEE

at integer-N channels is explained in [5]. The detailed nature of the ill-behaved spurious tones is analyzed in [6]. Recent research activities attempt to lower the TDC quantization noise by improving the TDC resolution. They include: TDC with fractional resolution [7], noise-shaped TDC [8], TDC with precise calibration and mismatch correction as well as clock doubler [9], TDC with time amplication [10], and TDC with doubling the resolution through additional row of ip-op registers operating on a delayed clock [11]. In this paper, we propose a simple fully-digital method to mitigate the abovementioned low-frequency quantization noise of the TDC. This is done by introducing low-level noiseshaped (e.g., ) randomization of the reference clock by means of a digital-to-time converter (DTC). II. TDC-BASED ADPLL
Data FCW Channel FCW FCW Reference phase Phase error

2t /TV . The total phase noise power is uniformly spread over the span from dc to the Nyquist frequency. The single2 sided spectral density is, therefore, expressed as L = /fR . Since the closed loop transfer function from the TDC to the ADPLL RF output is unity within the loop bandwidth [1], the phase noise spectrum at the output due to the TDC timing quantization is L= (2 )2 12 tres TV
2

1 fR

(3)

FREF

Norm TDC

DCO Loop Filter

Tune

(fV)

(fR)
Variable phase

CKV

Fig. 2. All-digital PLL frequency synthesizer with a wideband frequency modulation capability.

Fig. 2 shows an RF transmitter based on the all-digital PLL (ADPLL) frequency synthesizer with a digital direct frequency modulation capability [1]. The channel and data frequency control words are in the frequency command word (FCW) format dened as the fractional frequency division ratio N with a ne frequency resolution limited only by the FCW wordlength. The exact integer-N channels would be largely free from the abovementioned phase error quantization effects, but here they will result in a time-variant non-zero value of fractional FCW due to the data frequency modulation [5]. In Fig. 2 the simple TDC of Fig. 1 is augmented with the normalizing multiplier [12] that produces a xed-point variable phase, which is then subtracted from the reference phase in order to produce the digital phase error. The phase error is then ltered by a digital loop lter and then normalized by the DCO gain in order to correct the DCO phase/frequency in a negative feedback manner with loop behavior that is independent from process, voltage and temperature. The coarse basic DCO resolution KDCO is signicantly improved through dithering of its varactors. III. TDC R ESOLUTION Q UALITY P ROBLEMS The TDC quantization of phase error estimation affects the phase noise at the ADPLL output. Under the large signal assumption (spanning multiple quantization levels) the variance 2 of the timing uncertainty is: t = t2 res /12. The phase noise is obtained by normalizing the standard deviation of the timing error to the unit interval and multiplying by 2 radians: =

Substituting tres = 30 ps, fV = 1.8 GHz, TV = 556 ps, fR = 26 MHz, we obtain L = -94.3 dBc/Hz, which is adequate even for GSM applications. Eq. (3) reveals, that the TDC phase noise contribution could be minimized by improving the TDC timing resolution and increasing the sampling rate. Next generations of nanoscale CMOS processes can only bring reductions in tres at a scaling rate of 0.7x with each CMOS node. Eq. 3, describing the effect of the TDC resolution on the ADPLL phase noise, is only valid under the large signal assumption in which the timing difference between the FREF and CKV clock edges continuously exercises different quantization levels. This assumption does not hold very well at or near integer-N channels at which the fractional part of the FCW is close to zero (but not exactly zero in case of CW or no modulation). Fig. 3 shows the measure of the transmitter modulation distortion, expressed as an rms phase trajectory error (PTE), versus the relative channel number in the DCS (ca. 1800 MHz) and PCS (ca.1900 MHz) bands. It is evident that the integerN channels suffer from the extra parasitic modulation due to the non-white nature of the TDC quantization noise. The more obvious solution would be to improve the basic TDC resolution [7], [8], [9], [10], [11] as established by the most stable regenerative delay in CMOS, i.e., the inverter delay, typically involving design challenges and increased power consumption. The proposed solution, realized at greater simplicity and without modications to the core TDC circuitry, is to still maintain the otherwise-adequate TDC resolution but to push the quantization noise energy well beyond the loop lters cutoff frequency. IV. TDC N OISE -S HAPE D ITHERING The proposed solution to the ill-conditioned integer-N TDC behavior is to randomize the instantaneous value of the timing difference in a manner as shown in Fig. 4. A constant input to the noise-shaped 5th-order MASH modulator (SDM) will create a high-speed unit-weighted 32-bit output whose time-averaged value equals that of the input. Its power spectral density will be noise-shaped with the quantization energy rising at higher frequencies. The 32-bit SDM output controls the FREF delay by changing the cumulative A-input capacitance of the 32 2-input NAND gates by virtue of their B-input logic states, as shown in Fig. 5. The Y outputs are left unconnected. The static delay is inconsequential since the ADPLL loop will correct for it automatically. The exploited

RMS phase error with no SD dither, DCS channels 2.2

FREF
A Y

Dithered FREF

2.1 FCW=66 2 FCW=67

FCW=68

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d0 d1 d2

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Fig. 5.
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FREF delay circuit by means of a ne-precision DTC.

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Fig. 3. Simulated rms phase error vs. relative channel number in: DCS band (top), PCS band (bottom).
Time-to-digital Converter

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tr tf

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Fig. 4. FREF dithering by means of a DTC and modulating randomizer.

Fig. 6. SPICE simulation of delaying the FREF edge through A-input capacitance of the NA240 gates: strong corner (top), week corner (bottom).

behavior is a property of multi-input ASIC logic cells normally considered undesirable due to the dependency of the circuits propagation delay on its logic state. A. TDC FREF Delay SPICE Simulations The circuit of Fig. 5 was simulated in a low-leakage 90-nm digital CMOS technology. Fig. 6 shows two process, voltage, temperature (PVT) corners of the SPICE simulation results of delaying the FREF edge by the A-input capacitance of the NA240 gates. The delay control per gate varies from 1 to 2 ps over PVT corners. This relatively large timing deviation spread with zero mean is easily tolerable in the system due to adequate suppression in the loop lter and does not need to be compensated for.

V. V ERIFICATION THROUGH S YSTEM -L EVEL S IMULATIONS The proposed solution is veried through detailed top-level simulations of the entire Digital RF Processor (DRPT M )-based commercial RF SoC [4] realized in 90-nm CMOS technology. We used the VHDL-based modeling and simulation approach described in [13], [14], [15], which includes all relevant second-order effects, such as phase noise contribution of the reference and RF oscillator, as well as the TDC transfer function obtained through SPICE simulation with post-layout parasitics that include design-for-manufacturing (DfM) estimations of random metal llings. The modeling and simulation ow is the same as that used for RF performance sign-off of the RF SoCs [2], [3], [4].

RMS phase error for 4th order 5bits SD with 15ps unit delay, code 13, DCS 1.8

FCW=68 1.75

1.7

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1.55

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at or near the integer-N channels produces peculiar behavior due to the insufcient randomization of the TDC quantization noise, whose energy falls in-band and thus cannot be ltered by the loop lter, thus degrading the modulation distortion and possibly violating the modulation mask. We propose and demonstrate, through detailed top-level simulations, a method to randomize the TDC quantization noise by employing a noise-shaped 5th-order dithering of the FREF clock edges by means of a digital-to-time converter (DTC) realized using only standard logic gates. As a result, the ill-conditioned nearinteger-N channels of the traditional ADPLL do not exhibit any performance degradation.
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R EFERENCES
[1] R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS, New Jersey: John Wiley & Sons, Inc., Sept. 2006. [2] R. B. Staszewski, K. Muhammad, D. Leipold, et al., All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS, IEEE Journal of Solid-State Circuits, vol. 39, iss. 12, pp. 22782291, Dec. 2004. [3] R. B. Staszewski, J. Wallberg, S. Rezeq, et al., All-digital PLL and transmitter for mobile phones, IEEE Journal of Solid-State Circuits, vol. 40, iss. 12, pp. 24692482, Dec. 2005. [4] R. B. Staszewski, D. Leipold, O. Eliezer, et al., A 24mm2 quadband single-chip GSM radio with transmitter calibration in 90nm digital CMOS, Proc. of IEEE Solid-State Circuits Conf., sec. 10.5, pp. 208 209, 607, Feb. 2008. [5] O. Eliezer, B. Staszewski, I. Bashir, S. Bhatara, and P. T. Balsara, A phase domain approach for mitigation of self-interference in wireless transceivers, IEEE Journal of Solid-State Circuits, vol. 44, iss. 5, pp. 14361453, May. 2009. [6] S. D. Vamvakos, R. B. Staszewski, M. Sheba, and K. Waheed, Noise analysis of time-to-digital converter in all-digital PLLs, Proc. of Fifth IEEE Dallas Circuits and Systems Workshop: Design, Application, Integration and Software (DCAS-06), pp. 8790, Oct. 2006, Dallas, TX. [7] R. Tonietto, E. Zuffetti and R. Castello, A 2MHz bandwidth low noise RF all digital PLL with 12ps resolution time-to-digital converter, Proc. of European Solid-State Circuits Conf., pp. 150153, Sept. 2006. [8] C.-M. Hsu, M. Z. Strayer and M. H. Perrott, A low-noise, wide-BW 3.6GHz digital fractional-N synthesizer with a noise-shaping timeto-digital converter and quantization noise cancellation, Proc. of IEEE Solid-State Circuits Conf., pp. 340341, Feb. 2008. [9] C. W. Wu, E. Temporiti, D. Baldi and F. Svelto, A 3GHz fractionalN all-digital PLL with precise time-to-digital converter calibration and mismatch correction, Proc. of IEEE Solid-State Circuits Conf., pp. 344 345, Feb. 2008. [10] M. Lee, M. E. Heidari, A. A. Abidi, A low-noise, wideband digital phase-locked loop based on a new time-to-digital converter with subpicosecond resolution, VLSI Symposium on Circuits, pp. 112113, June 2008. [11] J. Tangudu, S. Gunturi, S. Jalan, J. Janardhanan, R. Ganesan, D. Sahu, K. Waheed, J. Wallberg, R. B. Staszewski, Quantization noise improvement of time to digital converter (TDC) for ADPLL, Proc. of 2009 IEEE Intl. Symp. on Circuits and Systems, pp. 10201023, May 2009. [12] R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, 1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS, IEEE Trans. on Circuits and Systems II, vol. 53, no. 3, pp. 220 224, Mar. 2006. [13] R. B. Staszewski, C. Fernando, and P. T. Balsara, Event-driven simulation and modeling of phase noise of an RF oscillator, IEEE Trans. on Circuits and Systems I, vol. 52, no. 4, pp. 723733, Apr. 2005. [14] K. Muhammad, T. Murphy, and R. B. Staszewski, Verication of digital RF processors: RF, analog, baseband, and software, IEEE Journal of Solid-State Circuits, vol. 42, iss. 5, pp. 9921002, May. 2007. [15] I. L. Syllaios, R. B. Staszewski, and P. T. Balsara, Time-domain modeling of an RF all-digital PLL, IEEE Trans. on Circuits and Systems II, vol. 55, no. 6, pp. 601604, Jun. 2008.

RMS phase error for 4th order 5bits SD with 15ps unit delay, code 13, PCS 1.8

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Fig. 7. Simulated rms phase error vs. relative channel number in: DCS band (top), PCS band (bottom). Integer-N channels for N = 66, 67, 68, 72 and 73 are shown with arrows.

To establish the baseline, we started with a large number of channels in the DCS (ca. 1800 MHz) and PCS (ca.1900 MHz) bands and included all the integer-N channels. The results were shown in Fig. 3. In contrast, Fig. 7 shows the improved rms phase error performance of the transmitter vs. the relative channel number in the DCS and PCS bands with the applied dithering on the FREF clock with the following conditions: 4th order 5-bit MASH dither, constant input word of 13/32, and unit delay of 15 ps. While this does not exactly correspond to the chosen conguration, it proves that the ill-conditioned behavior at integer-N channels can be alleviated through easy-to-realize fully-digital signal processing techniques. The only noticeable penalty is a slight performance degradation in non-integer-N channels, which is easily xed by not engaging the dithering at these channels based on software control. VI. C ONCLUSION In this paper, we describe a novel method of improving resolution quality of a time-to-digital converter (TDC) used in alldigital phase-locked loop (ADPLL). The ne TDC resolution of maximum 30 ps results in a GSM-quality phase detection mechanism for the great majority of the frequency channels. However, operating the ADPLL-based frequency synthesizer