OTA000004 SDH Principle

Issue 2.1

Confidential Information of Huawei.

No Spreading without Permission.

1
 Objectives

Upon completion of this

course, you will be able to:

‰Understand the basic of SDH

multiplexing standard

‰ Know the features,

applications and advantages of
SDH based equipment

Internal Use
 Chapter1 SDH Overview

Chapter2 Frame Structure & Multiplexing

Methods

Chapter3 Overhead & Pointers

Chapter4 Logical Functional Blocks

Internal Use
 References

‰ SDH Principle Manual

‰ ITU-T G.701, G.702, G.707

Internal Use
 Emergence of SDH

What is SDH?
---- Synchronous Digital Hierarchy
---- It defines frame structure, multiplexing
method, digital rates hierarchy and interface
code pattern.

Why did SDH emerge?

---- Need for a system to process
increasing amounts of information.
---- New standard that allows mixing
equipment from different suppliers.

Internal Use
 Disadvantages of PDH

1. Interfaces
Plesiochronous
Digital Hierarchy
Electrical interfaces
--- Only regional standards. 3 PDH rate hierarchies for
PDH: European (2.048 Mb/s), Japanese, North American
(1.544 Mb/s).
Optical interfaces
--- No standards for optical line equipments,
manufacturers develop at their will.

Internal Use
 Disadvantages of PDH

2. Multiplexing methods

Asynchronous Multiplexing for PDH

The location of low-rate signals in high-rate signals is
not regular nor predictable.

Internal Use
 Disadvantages of PDH

140 Mb/s 140 Mb/s

34 Mb/s 34 Mb/s

8 Mb/s 8 Mb/s
de-multiplexer multiplexer

de-multiplexer multiplexer

de-multiplexer multiplexer

2 Mb/s

level by level
Not suitable for huge-volume transmission

Internal Use
 Disadvantages of PDH

3. OAM function
--- Weak Operation, Administration & Maintenance function.

4. No universal network management interface

--- Capabilities to setup a TMN is limited.

Telecommunications Management
Network

Internal Use
 Advantages of SDH

1. Interfaces
Electrical interfaces
--- Can be connected to all existing PDH signals.

Optical interfaces
--- Can be connected to multiple vendors’ optical
transmission equipments.

Internal Use
 Advantages of SDH

2. Multiplexing method
--- Basic rate is STM-1, other rates are multiples of
the basic rate
--- PDH signal to/from SDH signal
--- Low level SDH to/from high level SDH

STM-1
622 Mbit/s 622 Mbit/s
De-multiplexing

Multiplexing

STM-1

STM-1
STM-4
STM-1

2 Mbit/s Low rate SDH High rate SDH

Internal Use
 Advantages of SDH

Low rate SDH to higher rate SDH

STM-1 STM-4 STM-16 STM-64

×4 ×4 ×4
155 Mb/s 622 Mb/s 2.5 Gb/s 10 Gb/s

Internal Use
 Advantages of SDH

byte interleaved multiplexing method

One Byte
STM-1 from STM-1 B
A

STM-1 A B C D A B C D A B …
B 4:1 STM-4

STM-1
C

STM-1
D

Internal Use
 Advantages of SDH

--- Synchronous multiplexing method and flexible

mapping structure

--- Use multistage pointer to align PDH loads in SDH

frame, thus, dynamic drop-and-insert capabilities

Internal Use
 Advantages of SDH

3. OAM function

--- Abundant overheads bytes for operation,

administration and maintenance.

--- About 5% of the total bytes are being used

Internal Use
 Advantages of SDH

4. Compatibility
PDH, SDH,
ATM, FDDI
Signals
packing

package STM-N SDH STM-N package

network
Processing transmit receive Processing
unpacking

PDH, SDH,
ATM, FDDI
Signals
Internal Use
 Disadvantages of SDH

Low bandwidth utilization ratio.

Signal Digital Bit Rate Channels
E0 64 kbit/s One 64 kbit/s
PDH Hierarchy
E1 2.048 Mbit/s 32 E0
E2 8.448 Mbit/s 128 E0
E3 34.368 Mbit/s 16 E1
E4 139.264 Mbit/s 64 E1
Bit Rate Abbreviated SDH SDH Capacity
155.52 Mbit/s 155 Mbit/s STM-1 63 E1, 3 E3 or 1 E4
622.08 Mbit/s 622 Mbit/s STM-4 252 E1, 12 E3 or 4 E4
2488.32Mbit/s 2.5 Gbit/s STM-16 1008 E1, 48 E3 or 16 E4
9953.28Mbit/s 10 Gbit/s STM-64 4032 E1, 192 E3, 64 E4

SDH Hierarchy
Internal Use
 Questions

1. Why did SDH emerge?

2. What are the advantages & disadvantages of
SDH?
3. What is the basic transmission rate in SDH
and what are the other common ones?

Time to think
Soon Coffee Time!

Internal Use
 Chapter1 SDH Overview

Chapter2 Frame Structure & Multiplexing

Methods

Chapter3 Overhead & Pointers

Chapter4 Logical Functional Blocks

Internal Use
 Part 2 SDH Frame Structure

From ITU-T G.707:

Frame = 125 us
1. One frame lasts for 125
microseconds (8000
frames/s)
2. Rectangular block 1
structure 9 rows and 270 2
columns(STM-1) 3
3. Each unit is one byte (8 bits) 4 9 rows
4. Transmission mode: Byte 5
by byte, row by row, from 6
left to right, from top to 7
bottom 8
9

270 Columns

Bit rate of STM-1= 9*270*8*8000

Internal Use
 SDH Frame Structure

Frame = 125 us

1
Three parts: 2 RSOH
3
1. Information 4 AU-PTR Information
5 9 rows
Payload Payload
6
2. Section 7 MSOH
Overhead 8
9
3. AU-PTR
9

270 Columns

Internal Use
 Information Payload

Information Payload

√ Also known as Virtual Container level 4 (VC-4)

√ Used to transport low speed tributary signals
√ Contains low rate signals and Path Overhead (POH)
√ Location: rows #1 ~ #9, columns #10 ~ #270

LPOH, TU-PTR

RSOH
package
AU-PTR
HPOH

9 rows Payload low rate signal

MSOH
package

LPOH, TU-PTR
9 1 Data
package
270 Columns
Internal Use
 Section Overhead

Fulfills the section layer OAM

functions

1
2 RSOH Types of Section Overhead
3
AU-PTR Information 1. RSOH monitor the
5 9 rows
Payload regenerator section
6 2. MSOH monitor the
7 MSOH
multiplexing section
8 Location:
9 1. RSOH: rows #1 ~ #3,
9 columns #1 ~ #9
2. MSOH: rows #5 ~ #9, columns
270 Columns
#1 ~ #9

Internal Use
 AU-PTR

Indicates the first byte of RSOH

VC4
4 AU-PTR Information
► Location: 9 rows
Payload
row #4, columns #1 ~ #9
MSOH

270 Columns

Internal Use
 SDH Multiplexing

SDH Multiplexing includes:

√ Low to high rate SDH signals (STM-1 Æ STM-N)

√ PDH to SDH signals (2M, 34M & 140M Æ STM-N)
√ Other hierarchy signals to SDH Signals (ATM Æ STM-N)

Some terms and definitions:

► Mapping
► Aligning
► Multiplexing

Internal Use
 SDH Multiplexing Structure
×1 Mapping
STM-64 AUG-64
Aligning
×4
×1 Multiplexing
STM-16 AUG-16
×4 Pointer processing
×1
STM-4 AUG-4

×4
×1 ×1
STM-1 AUG-1 AU-4 VC-4 C-4 139264 kbit/s

×3

×1 34368 kbit/s
TUG-3 TU-3 VC-3 C-3

×7
TUG-2

×3 TU-12 VC-12 C-12 2048 kbit/s

Internal Use
 SDH Tributary Multiplexing (140M)

140 Mbit/s to STM-N

C4 VC4
1
1
H
Rate Add HPOH P Next
140M
adaptation page
O
9 Mapping H 9
1 260 1 261
125 μs 125μs

Internal Use
 SDH Tributary Multiplexing (140M)

AU-4 AUG-1 STM-1

1 270
10 270

Add RSOH
AU-PTR Add Info
AU-PTR ×1 SOH AU-PTR
Payload
MSOH
9
Aligning Multiplexing STM-N
AUG-N 1
270X N

One STM-1 frame can load only Add

one 140Mbit/s Signal SOH
9

Internal Use
 SDH Tributary Multiplexing (34M)

34 Mbit/s to STM-N

C3 VC3
1 1
L
34M Rate Add LPOH P Next
Adaptation page
O
9 H 9
1 84 Mapping 1 85
125μs 125μs

Internal Use
 SDH Tributary Multiplexing (34M)

TU-3 TUG-3 VC-4

1 86 1 86 1 261
3
1 1 H1 1
H1 H2
H2 H3
H3 P
1st Fill O R
×3 R
gap H
align R

9 9 9

Aligning Multiplexing Same

procedure
as 140M

Internal Use
 SDH Tributary Multiplexing (2M)

2 Mbit/s to STM-N

C12 VC12 TU12

1 4 1 LPOH 4 1 4
1 1 1

Rate Add Add Next

2M
Adaptation LPOH TU-PTR page

9 9 9

125μs Mapping Aligning TU-PTR

Internal Use
 SDH Tributary Multiplexing (2M)

TUG-2 TUG-3
1 12 1 86
1 1

R R
×3 ×7

9 9

Same
Multiplexing Multiplexing procedure
as 34M

Internal Use
 Questions

1. What are the main parts of the SDH Frame

structure?

2. What is the transmission speed of STM-4?

How to calculate it?

Internal Use
 Glossary

► Mapping - A process used when tributaries are

adapted into VCs by adding POH information

► Aligning - This process takes place when a pointer is

included in a Tributary Unit (TU) or an Administrative
Unit (AU), to allow the 1st byte of the VC to be located

► Multiplexing - This process is used when multiple low-

order path signals are adapted into a higher-order
path signal, or when high-order path signals are
adapted into a Multiplexing Section

Internal Use
 Glossary

C = Container
VC = Virtual Container
TU = Tributary Unit
AU = Administrative Unit
TUG = Tributary Unit Group
AUG = Administrative Unit Group
STM = Synchronous Transfer Module

Internal Use
 Chapter1 SDH Overview

Chapter2 Frame Structure & Multiplexing

Methods

Chapter3 Overhead & Pointers

Chapter4 Logical Functional Blocks

Internal Use
 Part 3 Section Overheads

R A1 A1 A1 A2 A2 A2 J0
S
B1 ∆ ∆ E1 ∆ F1
O
H D1 ∆ ∆ D2 ∆ D3

AU-PTR

B2 B2 B2 K1 K2
M D4 D5 D6
S
O D7 D8 D9
H D10 D11 D12
S1 M1 E2
∆ = Media dependent bytes
STM-1
Internal Use
 A1 and A2 Bytes

‹ Framing Bytes – Indicate the beginning of the

STM-N frame

‹ The A1, A2 bytes are unscrambled

‹ A1 = f6H (11110110), A2 = 28H (00101000)

‹ In STM-N: (3XN) A1 bytes, (3XN) A2 bytes

STM-N STM-N STM-N STM-N STM-N STM-N

Finding frame head

Internal Use
 A1 and A2 Bytes

Framing

N
Find
A1,A2

OOF
Y
over 3ms

LOF

Next AIS
process

Internal Use
 D1 ~ D12 Bytes

Data Communications Channels (DCC) Bytes

‹ RS-DCC – D1 ~ D3 – 192 kbit/s (3X64 kbit/s)

‹ MS-DCC – D4 ~ D12 – 576 kbit/s (9X64kbit/s)

NE NE NE NE

DCC channel
TMN OAM Information: Operation, Administration
and maintenance

Internal Use
 E1 and E2 Bytes

‹ Orderwire Bytes

‹ E1 – RS Orderwire Byte – RSOH orderwire message

‹ E2 – MS Orderwire Byte – MSOH orderwire message

NE NE NE NE

E1 and E2

Digital telephone channel

E1-RS, E2-MS

Internal Use
 B1 Byte

Bit interleaved Parity Code (BIP-8) Byte –

‹ A parity code (even parity), used to check the
transmission errors over the RS
‹ B1 BBE is represented by RS-BBE( performance event)

A1 00110011 STM-N

A2 11001100 Tx Rx
A3 10101010
BIP-8
A4 00001111 Calculate
2#STM-N
1#STM-N B1, B2

Verify B1
B 01011010 2#STM-N
B2 1#STM-N

Internal Use
 B2 Byte

Bit interleaved Parity Code (MS BIP-24) Byte

‹ This bit interleave parity NX24 code is used to

check the bit errors over the MS

‹ B2 BBE is represented by MS-BBE( performance event)

‹ The mechanism of B2 is same like B1

Internal Use
 M1 Byte

Multiplexing Section Remote Error Indication Byte

‹ A return message from Rx to Tx ,when Rx find B2 bit errors
‹ A count of BIP-24xN (B2) bit errors
‹ Tx generate corresponding performance event MS-FEBBE

Traffic

Tx Rx

Return M1
Generate Find B2 bit errors
MS-FEBBE Generate MS-BBE

Internal Use
 K1 and K2( b1-b5)

Automatic Protection Switching

(APS ) bytes

Transmitting APS protocol

Used for network multiplexing

protection switch function

Internal Use
 K2 (b6 ~ b8)

¾Rx detects K2 (b6-

Start
b8)="111" generate MS-AIS
alarm
Detect
¾ Rx detects K2 (b6- K2(b6- 110
b8)="110" generate MS-RDI b8)

alarm 111

Generate
MS-AIS

Return MS- Generate

RDI MS-RDI

Internal Use
 S1 Byte

Synchronization Status Message Byte (SSMB): S1 (b5~

b8)
¾ Value indicates the sync. level

bits 5 ~ 8 Meaning
0000 Quality unknown (existing sync. Network)
0010 G.811 PRC
0100 SSU-A (G.812 transit)
1000 SSU-B (G.812 local)

1011 G.813 (Sync. Equipment Timing Clock)

1111 Do not use for sync.

Internal Use
 Path Overheads

1 2 3 4 5 6 7 8 9 10
J1 VC-n Path Trace Byte
B3 Path BIP-8
C2 Path Signal Label
G1 Path Status
F2 Path User Channel
H4 TU Multiframe Indi
F3 Path User Channel
K3 AP Switching
N1 Network Operator

Higher Order Path Overhead

Internal Use
 Path trace byte: J1

Detect J1

> The first byte of VC-4

> User-programmable
N Y
> The received J1 should Match
match with the expected
J1
Next
HP-TIM process

Internal Use
 B3 Byte

> Path bit parity

code byte (even parity code)
Verify B3
> Used to detect bit errors

¾Mechanism is same like

B1and B2 N Y
correct

HP-BBE Next
process

Internal Use
 Signal label byte: C2

> Specifies the mapping type in Detect C2

the VC-N

> 00 H Æ Unequipped
02 H Æ TUG structure N
00H
Y
13 H Æ ATM mapping
Y N
¾The received C2 should match Match HP-UNEQ
with the expected C2

Next HP-SLM
process

Insert AIS
downward

Internal Use
 Path Status Byte: G1

Detect receiving
¾Return performance VC4
message from Rx to Tx

> HP-REI Æ b1 ~ b4 HP-

N UNEQ Y
> HP-RDI Æ b5 HP-TIM
HP-SLM
N HP- Y Return
BBE
HP-RDI

Next Return
process HP-REI

Internal Use
 Path Overheads

Low Order Path Overhead

1 4
1 V5 J2 N2 K4

VC-12 VC-12 VC-12 VC-12

9
500μs VC-12 multiframe
Internal Use
 Path Overhead Bytes

V5
> First byte of the multiframe
> Indicated by TU-PTR
> Functions: Error checking, Signal Label and Path
Status of VC-12

z b1 ~ b2 Æ Error Performance Monitoring (BIP-2)

z b3 Æ Return Error detected in VC-12 (LP-REI)
z b4 Æ Return Failure declared in VC-12 (LP-
RFI)
z b5 ~ b7 Æ Signal Label for VC-12
z b8 Æ Indicate Defect in VC-12 path (LP-RDI)

Internal Use
 Path Overhead Bytes

Detect V5

Detect b5-b7
Verify b1 b2

N Y
000 N Y
match
Y N LP-UNEQ
Match
LP-BBE Next
Next process
process LP-SLM

Return LP-
REI (b3)
Return LP-
RDI (b8)

Internal Use
 Pointers

Pointers

AU-PTR TU-PTR

Internal Use
 AU-PTR

1 RSOH Negative Positive

justification justification

4 H1YYH2FF H3H3H3 0— — 1— — ------ 86— —

MSOH
9 435— — 436— — ------ 521— — 125us
1 522— — 523— — -----608— —
RSOH
696— — 697— — ------782— —
4 H1YYH2FFH3H3H3 0— — 1— — ------ 86— —

MSOH

9 250us
1 9 270

Internal Use
 TU-PTR
1 4
1

VC-12 VC-12 VC-12 VC-12

V1 V2 V3 V4
9
500μs VC-12 multiframe

TU POINTERS
Internal Use
 Questions

‰ Which byte is used to monitor the MS-AIS and MS-RDI?

‰ What is the mechanism for R-LOF generation?

‰ Which bytes implement the RS(MS/HP) error monitoring?

Internal Use
 Chapter1 SDH Overview

Chapter2 Frame Structure & Multiplexing

Methods

Chapter3 Overhead & Pointers

Chapter4 Logical Functional Blocks

Internal Use
 Part 4 Common SDH NE

TM (Terminal Multiplexer)
z Two ports device: Line Port (Optical Port), Tributary Port
z Used in the terminal station of a network
z Cross-connect function: TU ÅÆ LU

TM

STM-N W

E1 E4
Hua Wei
E3 Note: M<N
Default STM-M

Internal Use
 Common SDH NE

ADM (Add and Drop Multiplexer)

z Three ports device: Tributary Port, Line Port West (Left), Line Unit
East (Right)
z Used as an intermediate station, the most important NE type
z Cross-connect function: TU ÅÆ LU (W/E), LU (W) ÅÆ LU (E)

ADM
STM-N W E STM-N

E1 E4
Note: M<N
E3
Internal Use
STM-M
 Common SDH NE

Applications of TM & ADM

ADM

W E
STM-N STM-N
E1 E4
Note: M<N
E3 STM-M
ADM

TM ADM ADM TM ADM ADM

chain
ring ADM
Internal Use
 Common SDH NE

REG
z Two ports device: LU (W) & LU (E)
zUsed due to the long distance between Multiplexers
z O/E, Signal regenerating

W E
REG
STM-N STM-N

Internal Use
 Common SDH NE

DXC
z Multi-port device
z Used to interconnect larger number of STM-N signals
z Can be used for the grooming (consolidating & segregating)
of STM-Ns
z Used in complex & backbone network
z DXC m/n (m ≥ n)
m represent highest cross-connect rate
n represent lowest cross-connect rate

m or n 0 1 2 3 4 5 6
rate 64kb/s 2Mb/s 8Mb/s 34Mb/s 140Mb/s 622Mb/s 2.5Gb/s
155Mb/s

Internal Use
 SDH Logical Functional Blocks

ITU-T recommends a
unified basic functional
block standard

Internal Use
 Logical Functional Block for SDH
Equipment
w TTF

STM A B C D E F
SPI RST MST MSP MSA

HOI
140Mb/s G.703
M L G
PPI LPA HPT HPC
F

LOI HOA

2Mb/s G.703 K I G F
PPI
J LPA LPT
H LPC H HPA HPT
34Mb/s

Note: Taking 2Mb/s

as example Q Interface
SEMF MCF
F Interface
OHA OHA Interface P N
D4—D12 D1—D3

External Synchronous
SETS SETPI
Signal Interface
Internal Use
 SPI Functional Block

SPI: Synchronous Physical Interface

Æ Implements interface function
Æ O/E, extracts timing signal from SPI
STM-N
Æ Monitors corresponding alarm

Receiving Transmitting
AÆB BÆA

O/E Receive Fail E/O

Extract R-LOS
Timing
Signal

Internal Use
 RST Functional Block

Receiving
BÆC

R-LOS Framing
Put all “1” at C A1, A2

Fail Normal
R-OOF, R-LOF Unscramble
RST: Regenerator Section All “1” at C Process E1, D1~D3
Termination
Æ Processes RS overheads
Verify B1
Æ Processes RSOH in Rx RS-BBE
direction
Æ Writes RSOH in Tx direction

Internal Use
 RST Functional Block

Transmitting
CÆB

Writes Scrambles
RSOH STM-N frame

Calculates Add E1
B1 D1-D3

Internal Use
 MST Functional Block

MST: Multiplex Section

Termination Receiving
Æ Processes MSOH CÆD

Extract APS Detect Detect

K1, K2 (b1-b5) K2 (b6-b8) B2

111 Abnormal Overflow

110
MS-AIS MS-BBE MS-EXC (B2)
MS-RDI All “1” at D
All “1” at D

Internal Use
 MST Functional Block

Transmitting
D→C

Write MSOH

Receiving MS-BBE Receiving MS-AIS

Return M1ÆMS-REI Return K2Æ110 MS-RDI

Internal Use
 MST Functional Block

Concept of RS, MS

MST RST SPI SPI RST MST

RS (regenerator section)
MS (multiplex section)

Internal Use
 MSP Functional Block

MSP: Multiplex Section Protection

Æ Implements MS layer protection switch
Æ Switch conditions: R-LOS, R-LOF, MS-AIS alarm

Network topology Functional Block

Main Main Signal Path

M M
TM TM M MST MST M
S S
A S S A
Stand-by P P
MST MST

Stand-by Signal Path

Internal Use
 MSA Functional Block

Receiving
MSA: Multiplexing Section EÆF
Adaptation
Æ Implements AUG to
VC-4 or VC-4 to AUG De-interleaved
conversion AUG Æ N×AU-4

Read
AU-PTR

H1H2H3 are all “1” Invalid pointer or 8 NDF

AU-AIS AU-LOP
All “1” at F All “1” at F
Internal Use
 MSA Functional Block

Transmitting
FÆE

Writes Byte interleaved

AU-PTR N×AU- 4 Æ AUG

Internal Use
 Functional Blocks

HPC: High-Order Path Cross-connection

HPT: High-Order Path Termination

Æ Processes HPOH in VC-4

Internal Use
 HPT Functional Block

Receiving
FÆG

Verify B3 Detect J1 Detect C2 Transmit H4

Invalid Mismatch Mismatch to HPA
Æ HP-BBE Æ HP-TIM Æ HP-SLM
Æ 00H: HP-UNEQ

All “1” at G All “1” at G

Internal Use
 HPT Functional Block

Transmitting
GÆF

Receiving HP-TIM,
Write HO-POH Receiving HP-BBE HP-SLM, HP-UNEQ
Return HP-REI (G1) Return HP-RDI (G1)

Internal Use
 Functional Block

z HOI: High-Order Interface (HPT, LPA, PPI)

Æ 140 M --- VC-4

z HOA: High-Order Assemble (HPT, HPA)

Æ VC-12 --- VC-4

z LPC: Low-Order Path Connection

Æ For VC-12 & VC-3 Cross-connect Matrix
Æ Only chooses route, does not process signals

z LPT: Low-Order Path Adaptation

Æ Real-Time Monitoring of Low-Order VC-12

Internal Use
 Functional Block

LPA: Low-Order Path Adaptation

Æ Implements pack/unpack and restores original signal
Æ PDH <---> C

PPI: PDH Physical Interface

Æ Extract PDH tributary signal timing
Æ Code pattern conversion
Æ Interface between device and PDH line

Internal Use
 PPI Functional Block

PPI

Receiving Transmitting
LÆM MÆL
JÆK KÆJ

Code pattern No input signal

Code pattern
conversion T-ALOS,
conversion
Extract timing EX-TLOS

Internal Use
 HPA Functional Block

Receiving
GÆH
HPA: High order Path
Adaptation
Æ Implements C4 to
De-interleaved
VC-12 conversion C4 Æ 63XTU-12

Read
TU-PTR

V1V2V3 are all “1” Invalid pointer or 8 NDF

TU-AIS TU-LOP
All “1” at H All “1” at H

Internal Use
 HPA Functional Block

Transmitting
HÆG

Write Pointer Byte Interleave

TU-PTR, VC-12ÆTU12 TU12ÆC-4

Internal Use
 LPT Functional Block

LPT: Low-Order Path Termination

Æ Process LO-POH

LPT

Receiving Transmitting
HÆI IÆH

Detect V5 Write LO-POH

LP-BBE Receive LP-BBE, Return LP-REI
LP-SLM, LP-UNEQ Receive LP-SLM, UNEQ, Return LP-RDI

Internal Use
 Auxiliary Functional Blocks

SEMF: Synchronous Equipment Management Function

Æ Monitoring center of the whole equipment
Æ Implements OAM of local equipment and other equipment
MCF: Message Communication Function
Æ Provides D1~D3 Interface for communication
Æ Implements network management termination interface to
equipment: f/Qx

Internal Use
 Auxiliary Functional Blocks

SETS: Synchronous Equipment Timing Source

Æ Provides local timing clock signal to other functional
blocks
Æ Provides timing clock signal to other equipment
SETPI: Synchronous Equipment Timing Physical Interface
Æ Provides external interface of SETS
Æ External timing clock signal and output timing clock
signal
OHA: Overhead Access
Æ Processes order wire messages E1, E2, F1

Internal Use
 Alarm Flow Chart

R-LOS R-LOF

MS-EXC MS-AIS

AU-LOP AU-AIS HP-UNEQ HP-TIM HP-SLM

TU-AIS

Internal Use
Internal Use