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Floating Gate Memory Simulator


MOS Characteristics tutor

The double-gate MOS has been introduced in MICROWIND for the simulation of non-volatile memories such as EPROM, EEPROM and FLASH. The command "UV exposure" erases floating gates and removes all electrons. The programming is performed by a very high voltage supply on the gate (7V in 0.12m), a 1.2V voltage difference between drain and source. Some electrons are sufficiently accelerated to pass through the gate oxide by hot tunneling effect.

A valuable screen to understand the MOS characteristics, with a user interface that designers will like. Change the model parameters and see their effects on Id/Vd, Id/Vg Id(log)/Vg, threshold vs. length. You can also fit the simulations with measurements we made in test-chips fabricated in 0.35, 0.25 and 0.18m. In the manual, a tutorial on MOS models is given, with details on all parameters. MICROWIND supports MOS models 1, 3 and BSIM4.

l Simulation of non-volatile memories such as EPROM, EEPROM and FLASH using double-gate MOS l Erasure of floating gates and removal all electrons. l Programming can be performed by a very high voltage supply on the gate

l Change the model parameters and see their effects on Id/Vd, Id/Vg, Id(log)/Vg, threshold vs Length. l You can also fit the simulations with measurements we made in testchips fabricated in 0.35, 0.25 and 0.18 m l Full length tutorial on MOS models is provided in manual, with details on all parameters. l Supports level1, level3 and BSIM4 MOS models. l Documentation includes several aspects of MOS modeling.


Cross sectional and 3D Viewer

You will never teach deep-sub micron technology like before. As VirtualFab offers you a facility to analyze and view cross sectional view of silicon layers and 3D view of circuits. With MICROWIND v3.5 VirtualFab enables to draw real-time images of the layout and navigate in full-3D on the surface or inside the IC. This command is based on OpenGL and offers outstanding picture quality. The user can modify the viewing position in X,Y,Z and play with light sources to create illustrative views of the layout.

3D fabrication process simulator with cross sectional viewer. Step-by-step 3-D visualization of fabrication for any portion of layout. See how the contacts and metallizations are created. See the self-aligned diffusion after the polysilicon gate is fabricated. Check planes of VDD, VSS, and others signals. Check the oxide structure, the low dielectric (Low K) and high K (SiO2) Sandwich, and passivation. l User can check the gate oxide and the MOS lateral drain diffusion structure. l Advanced 3D layout view with GEL technology l 2D cross sectional viewer with strain technology support. l l l l l l

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PROthumb VirtualFab





MICROWIND is truly integrated EDA software encompassing IC designs from concept to completion, enabling chip designers to design beyond their imagination. MICROWIND integrates traditionally separated front-end and back-end chip design into an integrated flow, accelerating the design cycle and reduced design complexities. It tightly integrates mixed-signal implementation with digital implementation, circuit simulation, transistor-level extraction and verification providing an innovative education initiative to help individuals to develop the skills needed for design positions in virtually every domain of IC industry.


Mix-signal Simulator


Precision CMOS Layout Editor

No SPICE or external simulator is needed for verification of CMOS circuits. Microwind program has in built analog like simulator which supports MOS Level 1, Level 3 or BSIM4 model. With features like fast time-domain, voltage and current estimation, very intuitive post processing, frequency estimation, delay estimation, makes PROthumb a time saver. Even power estimation of circuit simulation can be checked on-screen.

MICROWIND possess a precision CMOS layout editor, which supports technologies right from 1.2 m till 22 nm with unsurpassed illustration capabilities. With its enhanced editing commands and layout control your development times would be shorter than you ever imagined.

l Huge technology support till 22 nanometers. l Sub-micron, deep-submicron, ultra deep-submicron, nanoscale technology support. l Design-error-free cell library (Contacts, vias, MOS devices, etc.). l Advanced macro generator (Capacitor, MOS transistor, matrix, ROM, pads, inductors, path, etc.) l Virtual components library (R,L,C, etc) for faster simulation response. l Incredible translator from logic expression into compact design-error free layout. l Powerful automatic compiler from Verilog structure circuit into layout. l On-line design rule checker with large rule base. l Built-in extractor which generates a SPICE netlist from layout. l Extraction of all MOS width and length. l Parasitic capacitance, inductance, crosstalk and resistance extracted for all electrical nodes. l Modular design support with insert mask layout facility. l Import/Export CIF layout from 3rd party layout tools. l Supports up to 100,000 elementary boxes. l Lock & unlock layers to protect some part of the design from any changes. l Support upto 8 metal layers for DSM technologies. l Global delay evaluation of circuit with facility to dump RC values. l Global cross talk analyzer. l Inversion of diffusions boxes. l Easy label listing. l Enhanced mathematical signal description for advance users. l Zoom in navigator. l Enhanced memory utilization for faster simulation. l Silicon atom viewer with 3D support allows students to understand Si atom structure.

l Built-in SPICE-like analog simulator. l Features fast time-domain, voltage and current estimation, with very intuitive post processing: frequency estimation, delay estimation. (No external SPICE/ analog Simulator required). l Supports level1, level3 and BSIM4 models for all technologies from 1.2m till 22 nm. l MOS characteristic viewer with access to parameters of main model. l Ability to label nodes allows intuitive control of the simulation (Supply, clock, pulse, PWL, sinus, maths). l Time-domain voltage and current waveforms available at the press of one single button. l DC/AC characteristics, signal frequency vs. time, eye diagrams. Min/Typ/Max analog simulation. l Convenient Monte-carlo simulation. l Powerful Fast-Fourier Transform to support radio-frequency circuit simulation. l Eye diagram view for signal output. l On screen power estimation. l Sophisticated parametric simulation to investigate the effect of several key parameters on the circuit performances: R,L,C, temperature, supply voltage, etc. l Huge device simulation model library. l Inbuilt interconnect analyzer to compute field between ground planes and conductor. l Enhanced memory utilization for faster simulation. l Onscreen storage of waveforms for result hold-on. l Forward & backward buttons to move in simulation results.


Schematic Editor and Digital Simulator

The DSCH program is a logic editor and simulator. DSCH is used to validate the architecture of the logic circuit before the microelectronics design is started. DSCH provides a user-friendly environment for hierarchical logic design, and fast simulation with delay analysis, which allows the design and validation of complex logic structures. DSCH also features the symbols, models and assembly support for 8051 and 16F84 controllers. Designers can create logic circuits for interfacing with these controllers and verify software programs using DSCH.

l User-friendly environment for rapid design of logic circuits. l Supports hierarchical logic design. l Handles both conventional pattern-based logic simulation and intuitive on screen mouse-driven simulation. l Improved built-in extractor which generates a SPICE netlist from the schematic diagram (Compatible with PSPICETM and WinSpiceTM). l Generates a VERILOG description of the schematic for layout conversion. l Immediate access to symbol properties (Delay, fanout). l Model and assembly support for 8051 and PIC 16F84 microcontrollers. l Sub-micron, deep-submicron, nanoscale technology support. l Supported by huge symbol library. l Tool for fault analysis at the gate level of digital circuits.