SEQUENTIAL

LOGIC CIRCUIT
[28 Marks]
















Chapter 4

Chapter Details

Objectives
4.1 Introduction
Flip-flop, Control Signals
4.2 Trigger Levels used in the
Flip-flop Triggering
4.3 1-Bit Memory Cell
4.4 Types of Flip-flop
Set-Reset (S-R) Flip-flop, Clocked
S-R Flip-flop, J-K Flip-flop, Master-
Slave J-K Flip-flop, D Type
Flip-flop, T Type Flip-flop,
Comparison between D Flip-flop
and T Flip-flop
4.5 Excitation Table of Flip-flop
4.6 Study of IC 7474 and IC 7475
(D Flip-flop)
4.7 Applications of Flip-flops
4.8 Counters
4.9 Types of Counters
Ripple of Asynchronous Counters,
Synchronous Counters,
Comparison of Asynchronous
Counter and Synchronous
Counter
4.10 Counter Applications
4.11 Shift Registers
Flip-flop as a Storage Element,
Types of Shift Registers, A
Universal Shift Register,
Applications of Shift Register


4-2
Principles of Digital Techniques


Graphical and Statistical representation of questions asked from this chapter
in previous years MSBTE Question Papers


30
32
54
0
10
20
30
40
50
60
T
o
t
a
l

M
a
r
k
s
W-2009 S-2010 W-2010
Years
Graphical Representation




Statistical Analysis
MSBTE paper Total marks questions asked in this chapter
W-2009 30
S-2010 32
W-2010 54




4-3 Sequential Logic Circuit
OBJECTIVES
In this unit you will learn the following things:
i. Difference between combinational logic circuit and sequential logic circuit.
ii. Triggering methods of flip-flops.
iii. One bit memory cell.
iv. Flip-flops: The basic building block of semiconductor memory and their types such
as S-R f/f, J-K f/f, M-S J-K f/f, D f/f and T f/f.
v. Study of different f/f ICs.
vi. Applications of f/fs such as shift register and counters.
vii. Operation of synchronous and asynchronous counters, modulus counter, updown
counter.
viii. Data transfer mechanism in serial / parallel input, serial / parallel output shift
register.
ix. Study of IC 7490.
x. Applications of shift register.
4.1 INTRODUCTION
The sequential circuits are those in which there is at
least one memory element and their outputs at a given
instant depend on the present inputs and past
inputs/outputs. Memory elements are used to store past
information. A sequential logic system may have
combinational sub-system.
A block diagram of a sequential circuit is shown in fig. 4.1.
It consists of a combinational circuit to which memory
elements are connected to form a feedback path.
Combinational
circuit
Memory
element
Output Input

Figure 4.1: Block diagram of sequential circuit
The memory elements are devices capable of storing
binary information within them. The binary information
stored in the memory elements at any given time defines
the state of the sequential circuit.

There are basically two types
of digital logic circuits:
i. Combinational logic
circuits
ii. Sequential logic circuits

In combinational logic
circuits, output depends on
present inputs.
e.g., Logic gates,Multiplexers

In sequential logic circuits,
output depends on present
inputs as well as previous
inputs /output.
e.g., Flip-flops, Counters





4-4
Principles of Digital Techniques
The sequential circuit receives binary information from external inputs. These inputs,
together with the present state of the memory elements, determine the binary value at
the output terminals. They also determine the condition for changing the state in the
memory elements. The block diagram demonstrates that the external outputs in a
sequential circuit are a function not only of external inputs but also of the present state of
the memory elements. The next state of the memory elements is also a function of
external inputs and the present state. Thus, a sequential circuit is specified by a time
sequence of inputs, outputs, and internal states.

English Word = ==| = ==| = ==| = ==| =
Synchronous = |= -=|
-=
Amplitude = =|
+=- t='+:= :=
==+|+ ==+ =+, '=-
|, =











There are two main types of sequential circuits. Their
classification depends on the timing of their signals. A
synchronous sequential circuit is a system whose
behavior can be defined from the knowledge of its
signals at discrete instants of time. The behavior of an
asynchronous sequential circuit depends upon the order
in which its input signals change and can be affected at
any instant of time. The memory elements commonly
used in asynchronous sequential circuits are time-delay
devices.
Practical synchronous sequential logic systems use fixed
amplitudes such as voltage levels for the binary signals.
Synchronization is achieved by a timing device called a
master-clock generator which generates a periodic train
of clock pulses.
The memory elements used in clocked sequential
circuits are called flip-flops. These circuits are binary
cells capable of storing one bit of information. A flip-flop
circuit has two outputs, one for the normal value and one
for the complement value of the bit stored in it. Binary
information can enter a flip-flop in a variety of ways, a
fact which gives rise to different types of flip-flops. This
chapter describes few Sequential circuits includes flip-
flop, registers, and counters.
Combinational circuits Sequential circuits
In combinational circuits, the output variables are at
all times dependent on the combination of input
variables.
In sequential circuits, variables are dependent not
only on the present input variables but they also
depend upon the past history of these input variables.
Memory unit is not required in combinational circuits. Memory unit is required to store the past history of
input variables in the sequential circuit.
Combinational circuits are faster in speed because
the delay between input and output is due to
propagation delay of gates.
Sequential circuits are slower than the combinational
circuits.
Combinational circuits are easy to design. Sequential circuits are comparatively harder to design
Parallel adder, logic gates, multiplexers are
combinational circuits.
Flip-flops, counters are sequential circuits.

BTE W.20, S.10 - 4M
1. What is difference
between
combinational and
sequential logic
circuits?
2. Compare sequential
logic circuit and
combinational logic
circuit.


4-5 Sequential Logic Circuit

4.1.1 Flip-fl op
Flip-flop is the fundamental building block of all
semiconductor memory. A flip-flop is a basic memory
element used to store one bit of information. It is also
called a bi-stable multi-vibrator or latch.
A flip-flop is a bistable electronic circuit. It has two
stable outputs, 0 and 1. It remains in one of the states
until something is done to change its output. Thus, it
behaves as a memory cell. It is constructed using logic
gates.
Symbol: A flip-flop is represented as a square with
inputs, outputs and the clock signal.
Input 1 Output
Clock
Input 2 Output
Flip-flop

Figure 4.2: Flip-flop
4.1.2 Control Si gnals
Control signals are electronic signals given to flip-flops
or register to control their operation. These signals are as
follows:
a. Clock: This is a signal which contains electronics
pulses (high and low). The operation of the Flip
Flop and Registers is performed according to these
pulses.
Example
Positive
edge
Negative
edge

Figure 4.3 : Clock signal
b. Set: This signal sets the output to a specific value
(either high or low).
c. Reset: This signal, when high, resets the output to
the default value.
d. Clear: This signal clears the contents of the flip
flop or register.


The basic digital memory
circuit which can store one
bit information is known as
flip-flop.




English Word = ==| = ==| = ==| = ==| =
Flip-flop = |= =- |= =|
==







Positive
edge
Negative
edge
1
0 Low state
High state
Clock pulse











BTE W.2009 - 2M
What is a clock? State
its use.


4-6
Principles of Digital Techniques


Triggering methods
i. Level triggering
a. Positive level
triggering
b. Negative level
triggering
ii. Edge triggering
a. Positive edge
triggering
b. Negative edge
triggering







4.2 TRIGGER LEVELS USED IN
THE FLIP-FLOP TRIGGERING
The triggering methods are classified as under:
Negative edge
triggering
Positive edge
triggering
Negative level
triggering
Positive level
triggering
Edge triggering Level triggering
Triggering methods

The flip-flops can be designed to respond either to the
HIGH or LOW logic levels or to the rising and falling
edges of the clock pulse as shown in fig. 4.4. The flip-
flops are designated according to the kind of triggering
used. If the flip-flops uses logic levels to trigger, then it
is called as level triggered flip-flops. If the flip-flop
outputs are changed corresponding to the input at rising
or falling edge of the clock pulse, then it is called as
edge triggered flip-flop.
A
m
p
l
i
t
u
d
e
Time
Low level
Leading or rising
or positive edge
Trailing or falling
or negative edge
High level

Figure 4.4: High, low level and rising, falling edge of the clock pulse
If the flip-flop uses HIGH level for triggering then it is called as positive level triggered
flip-flops.
If the flip-flop uses LOW level for triggering then it is called as negative level triggered
flip-flops.
The positive level triggered flip-flops and negative level triggered flip-flops symbols are
shown in fig. 4.5 (a) and 4.5 (b) respectively.

BTE S.10, W.09 - 2M
1. Explain triggering
methods in brief.
2. What are the
different triggering
methods in digital
circuits?


4-7 Sequential Logic Circuit
F/F
(a) Positive level
triggered
F/F
(b) Negative level
triggered
F/F
(c) Positive edge
triggered
F/F
(d) Negative edge
triggered

Figure 4.5: Positive and negative level and edge triggering
If the flip-flop uses rising edge of the clock pulse for triggering then it is called as
positive edge triggered flip-flops.
If the flip-flop uses falling edge of the clock pulse for triggering then it is called as
negative edge triggered flip-flops.
Notice that, the bubble at the clock input indicates a negative logic and that without
bubble indicates a positive logic. To differentiate between level and edge triggered, a
dynamic input indicator like a triangle is used. It is the key to identify the flip-flop by
its logic symbol. It is the small triangle inside the block at the clock input. The presence
of indicates that the circuit is positive edge triggered and its absence indicates it is
level triggered. The positive and negative edge triggered flip-flops are shown in
fig. 4.5 (c) and 4.5 (d) respectively.
4.3 1-BIT MEMORY CELL
The basic digital memory circuit is known as flip-flop. It has
two stable states which are known as the 1 (high) state and
the 0 state. It can be obtained by using NAND or NOR gates. We shall be systematically
developing a flip-flop circuit starting from the fundamental circuit shown in fig. 4.6. It
consists of two cross coupled inverters using NAND gates (fig. 4.6 (a)) or using NOR
gates (fig. 4.6 (b)). The output of G
1
is connected to the input of G
2
(A
2
) and the output of
G
2
is connected to the input of G
1
(A
1
).
When the power is switch on, output Q is in one of the stable states (Q = 0 or Q = 1).
G
1
G
2
A
1
A
2
O
O Q
Q G
1
G
2
A
1
A
2
(a) Cross coupled inverts using
NAND gates
(b) Cross coupled inverts
using NOR gates

Figure 4.6

BTE W.2010 - 2M
Draw the logical diagram
of 1-bit memory cell.


4-8
Principles of Digital Techniques
Let us assume the output of G
1
to be Q = 1, which is also the input of G
2
(A
2
= 1).
Therefore, the output of G
2
will be Q

= 0, which makes A
1
= 0 and consequently
Q = 1 which confirms our assumptions.
If Q = 0 then Q

= 1 and this is also consistent with the circuit connection.

From the above discussion we note the following:
i. The output Q and Q

are always complementary.

ii. The circuit has two stable states, in one of the stable Q = 1 which is referred as the
1 state (or set sate) whereas in the other stable state Q = 0 which is referred to as
the 0 state (or reset state).
iii. If the circuit is in 1 state, it continues to remain in this state and similarly if it is in 0
state, it continues to remain in this state. This property of the circuit is referred to
as memory. Since this information is locked or latched in this circuit, therefore, this
circuit is also referred.
In the latch of fig. 4.6 there is no way of entering the desired digital information to be
stored in it. In fact, when the power is switched on, the circuit is switched to one of the
stable sates (Q = 1 or Q = 0) and it is not possible to predict the state. Hence this circuit
is modified and we get flip-flop.
4.4 TYPES OF FLIP-FLOP
Types of flip-flops are as given below
i. S-R flip-flop ii. Clocked S-R flip-flop
iii. J-K flip-flop iv. Master-Slave J-K flip-flop
v. D type flip-flop vi. T type flip-flop
Next section describes types of flip-flops in greater details.
S (set) terminal is used to set
the flip-flop. If S = 1, R = 0
then Q = 1.

R (reset) terminal is used to
reset the flip-flop. If S = 0,
R = 1 then Q = 0.




4.4.1 Set - Reset (S-R) Flip-fl op
The most basic flip-flop is called the S-R flip-flop. The
block logic symbol for the S-R flip-flop is shown in
fig. 4.7. The logic symbol shows two inputs, labeled set
(S) and reset (R). The outputs are typically labeled Q and
Q

. The Q output is considered as the normal output and

is the one most used. The output Q

is simply the
complement of Q and is referred to as the
complementary output. Under normal conditions these
outputs are always complementary. Hence, if Q = 1 then
Q

= 0; or if Q = 0 then Q

= 1.


BTE W.2010 - 4M
Draw and explain with
truth table S-R flip-flop
using NAND gates.


4-9 Sequential Logic Circuit
S
R
Q
Q
Set
Reset
Inputs Outputs
Normal
Complementary

Figure 4.7: Logic symbol of S-R flip-flop
The S-R flip-flop can be constructed from logic gates. The S-R flip-flop constructed using
four NAND gates is shown in fig. 4.8.
S
Set
R
Reset
Q
Q
G
1
G
2
G
3
G
4

Figure 4.8
To see the operation of S-R flip-flop we consider all the four possible input conditions.
i. If S = 0 and R = 0 then the output of Gates G
1
and G
2
will be 1. Therefore, outputs
Q and Q

depends on previous output conditions. If Q = 0 previously, the output of

G
4
(Q

) will be 1 which makes output of G

3
(Q = 0). Hence Q remains in its previous
state.
There is no change in the output states of Q and Q

when S = 0 and R = 0.
ii. If S = 0 and R = 1 then the output of G
1
will be 1 and G
2
will be 0. Since one input
of G
4
is 0 then its output (Q

) will be 1. Now both inputs of Gate G

3
will be 1. Hence
Q = 0.
Thus if S = 0 and R = 1 then Q = 0 and thus R(reset) terminal resets (Q = 0) the
flip-flop.
iii. If S = 1 and R = 0 then outputs of Gate G
1
= 0 and G
2
= 1. This makes output of G
3

(Q) = 1 and therefore Q

= 0.
Thus If S = 1, R = 0 then Q = 1, Q

= 0. Thus S(set) terminal sets the flip-flop.

iv. If S = 1 and R = 1 then outputs of Gates G
1
and G
2

will be zero (0). Therefore both the outputs Q and
Q

will try to become 1 which is not allowed.

Therefore this input condition is prohibited.
This is the drawback of S-R flip-flop.
Drawback of S-R flip-flop
When S = 1 and R = 1 then
output Q is forbidden. So we
cannot use this state.



4-10
Principles of Digital Techniques
Figure 4.1: Truth table of S-R flip-flop
Inputs Output Operation
S R Q
0 0 Q (N.C.) Last state (no change)
0 1 0 Reset
1 0 1 Set
1 1 Prohibited Not allowed
4.4.2 Clocked S-R Fl ip-flop
The basic S-R flip-flop is an asynchronous sequential circuit. It does not work with a
clock or timing device. The electronic circuits take time to change the output after the
inputs are applied. This time delay is known as propagation delay and is in milliseconds
to nanoseconds. If the inputs are changed faster than the propagation delay time then,
before the previous input cause change in the output, new input will change the
condition. Thus we will not get the satisfactory results. Thus it is important here to study
the behavior of the circuit at discrete intervals of time. The inputs and outputs of the
circuit must change only at discrete instants. That is, when new inputs are being
accepted by the circuit, its previous output should not change. On the other hand, when
the output is changing, its inputs should not change or new inputs should not be
accepted. Thus we need synchronization in the circuit operations. The concept of
synchronization can be understood with the example of the drum beats used in the
parade of the NCC troops. They use the drum beats to synchronize the actions during the
parade. Thus we need the circuits to be operated in step with the clock or timing device.
The clock used in the electronic circuits, is a square wave signal from astable
multivibrator. The clock signal is shown in fig. 4.9.
A
m
p
l
i
t
u
d
e
T
on
T
off
T = T + T
on off
Time

Figure 4.9: Timing signal
The signal amplitude changes HIGH and LOW alternately. The time for which the signal
level is HIGH is called as ON time (T
on
) and the time for which it is LOW is called as
OFF time (T
off
). The ON and OFF times may or may not be same. The pulse height is the
amplitude of signal and is +5 volts in most of the digital circuits (TTL logic family).