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ESD7004 Transient Voltage Suppressors

Low Capacitance ESD Protection Diode for High Speed Data Line
The ESD7004 transient voltage suppressor is designed to protect high speed data lines from ESD. Ultralow capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. The flowthrough style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance between high speed differential lines such as USB 3.0 and HDMI.
Features http://onsemi.com MARKING DIAGRAM
UDFN10 CASE 517BB 4M MG G

Low Capacitance (0.4 pF Typical, I/O to GND) Protection for the Following IEC Standards: Low ESD Clamping Voltage This is a PbFree Device
Typical Applications

4M = Specific Device Code (tbd) M = Date Code G = PbFree Package (*Note: Microdot may be in either location)

IEC 6100042 (Level 4)

PIN CONFIGURATION AND SCHEMATIC


N/C N/C 10 1 I/O 9 2 I/O GND N/C N/C 8 3 GND 7 4 I/O 6 5 I/O

USB 3.0 HDMI Display Port eSATA

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating Operating Junction Temperature Range Storage Temperature Range Lead Solder Temperature Maximum (10 Seconds) IEC 6100042 Contact (ESD) IEC 6100042 Air (ESD) Symbol TJ Tstg TL ESD ESD Value 55 to +125 55 to +150 260 15 15 Unit C C C kV kV
Pin 1 Pin 2 Pin 4 Pin 5

Pins 3, 8

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

See Application Note AND8308/D for further description of survivability specs.

ORDERING INFORMATION
Device ESD7004MUTAG Package UDFN10 (PbFree) Shipping 3000 / Tape & Reel

For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2012

April, 2012 Rev. 3

Publication Order Number: ESD7004/D

ESD7004
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise specified)
Parameter Reverse Working Voltage Breakdown Voltage Reverse Leakage Current Clamping Voltage (Note 1) Clamping Voltage (Note 2) Clamping Voltage TLP (Note 3) See Figures 6 through 9 Junction Capacitance Junction Capacitance Symbol VRWM VBR IR VC VC VC I/O Pin to GND IT = 1 mA, I/O Pin to GND VRWM = 5 V, I/O Pin to GND IPP = 1 A, I/O Pin to GND (8 x 20 ms pulse) IEC6100042, 8 KV Contact IPP = 8 A IPP = 16 A IPP = 8 A IPP = 16 A VR = 0 V, f = 1 MHz between I/O Pins VR = 0 V, f = 1 MHz between I/O Pins and GND See Figures 1 and 2 11.4 15.6 4.5 8.1 0.2 0.4 0.3 0.5 pF pF 5.5 1.0 10 Conditions Min Typ Max 5.0 Unit V V mA V V

CJ CJ

1. Surge current waveform per Figure 5. 2. For test procedure see Figures 3 and 4 and application note AND8307/D. 3. ANSI/ESD STM5.5.1 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.

Figure 1. IEC6100042 +8 KV Contact ESD Clamping Voltage

Figure 2. IEC6100042 8 KV Contact Clamping Voltage

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ESD7004
IEC 6100042 Spec.
Test Voltage (kV) 2 4 6 8 First Peak Current (A) 7.5 15 22.5 30 Current at 30 ns (A) 4 8 12 16 Current at 60 ns (A) 2 4 6 8 I @ 60 ns 10% tP = 0.7 ns to 1 ns I @ 30 ns IEC6100042 Waveform Ipeak 100% 90%

Level 1 2 3 4

Figure 3. IEC6100042 Spec

ESD Gun

TVS

Oscilloscope

50 W Cable

50 W

Figure 4. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note AND8308/D Interpretation of Datasheet Parameters for ESD Devices. ESD Voltage Clamping

For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC6100042 waveform. Since the IEC6100042 was written as a pass/fail spec for larger
100 % OF PEAK PULSE CURRENT 90 80 70 60 50 40 30 20 10 0 0 20 tP tr

systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D.

PEAK VALUE IRSM @ 8 ms PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms HALF VALUE IRSM/2 @ 20 ms

Figure 5. 8 X 20 ms Pulse Waveform

40 t, TIME (ms)

60

80

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ESD7004
22 20 18 16 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 VOLTAGE (V) 14 16 18 20 CURRENT (A) CURRENT (A) 22 20 18 16 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 16 18 20 VOLTAGE (V)

Figure 6. Positive TLP IV Curve Transmission Line Pulse (TLP) Measurement

Figure 7. Negative TLP IV Curve

Transmission Line Pulse (TLP) provides current versus voltage (IV) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 8. TLP IV curves of ESD protection devices accurately demonstrate the products ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 9 where an 8 kV IEC 6100042 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP IV curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. A typical TLP IV curve for the ESD7004 is shown in Figures 6 and 7.

L
50 W Coax Cable

S Attenuator

10 MW IM

50 W Coax Cable

VM

VC Oscilloscope

DUT

Figure 8. Simplified Schematic of a Typical TLP System

Figure 9. Comparison Between 8 kV IEC 6100042 and 8 A and 16 A TLP Waveforms

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ESD7004

Without ESD

With ESD7004

Figure 10. USB3.0 Eye Diagram with and without ESD7004. 5.0 Gb/s, 400 mVPP

Without ESD

With ESD7004

Figure 11. HDMI1.4 Eye Diagram with and without ESD7004. 3.4 Gb/s, 400 mVPP

Without ESD

With ESD7004

Figure 12. ESATA3.0 Eye Diagram with and without ESD7004. 6 Gb/s, 400 mVPP

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ESD7004
Test Board Region DUT Region Test Board Region

DIFFERENTIAL IMPEDANCE (W)

TDR max = 92.7 W

TIME (ps) ** USB spec requirement is 90 W 10%

Figure 13. USB TDR Measurement. 90 W Differential Impedance Target, 200 ps Rise Time
Test Board Region DUT Region Test Board Region

DIFFERENTIAL IMPEDANCE (W)

TDR min = 97 W

TIME (ps) ** HDMI spec requirement is 100 W 15%

Figure 14. HDMI TDR Measurement. 100 W Differential Impedance Target, 200 ps Rise Time

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ESD7004
4 S21 INSERTION LOSS (dB) 2 0 2 4 6 8 10 1.E+06 1.E+07 1.E+08 FREQUENCY (Hz) 1.E+09 1.E+10 ESD7004 IOGND ESD7004 IOIO

Figure 15. ESD7004 Insertion Loss

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ESD7004
USB 3.0 Type A Connector StdA_SSTX+ Vbus

StdA_SSTX ESD7004 ESD7L5.0 D

GND_DRAIN

D+

StdA_SSRX+

GND StdA_SSRX

Figure 16. USB3.0 Standard A Connector Layout Diagram

USB 3.0 Micro B Connector ESD7004 Vbus D D+ ID GND

ESD7004

MicB_SSTX MicB_SSTX+ GND_DRAIN MicB_SSRX MicB_SSRX+

Figure 17. USB3.0 Micro B Connector Layout Diagram http://onsemi.com


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ESD7004 HDMI Type A Connector D2+ GND D2 D1+ GND D1 ESD7004 D0+ GND D0 CLK+ GND CLK CEC N/C (or HEC_DAT HDMI1.4) SCL SDA GND 5V HPD (and HEC_DAT HDMI1.4)

NUP4114

Figure 18. HDMI Layout Diagram


e S ATA Connector GND

A+ ESD7004

GND

B+

GND

Figure 19. eSATA Layout Diagram http://onsemi.com


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ESD7004
PACKAGE DIMENSIONS
UDFN10 2.5x1, 0.5P CASE 517BB ISSUE O
L D
PIN ONE REFERENCE 2X 2X

A B L1 E
OPTIONAL CONSTRUCTIONS

0.10 C

0.10 C


DETAIL B

DETAIL A

NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. DIM A A1 A3 b b2 D E e L L1 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 0.35 0.45 2.50 BSC 1.00 BSC 0.50 BSC 0.30 0.40 --0.05

TOP VIEW A3 A

EXPOSED Cu

0.10 C
10X

0.08 C SIDE VIEW


2X DETAIL A

A1 A1 C
SEATING PLANE


DETAIL B 0.50
10X

MOLD CMPD

A3

OPTIONAL CONSTRUCTION

b2
1 5

10X

RECOMMENDED SOLDERING FOOTPRINT*


2X

0.45

10

6 8X

1.30 b 0.10 C A B
PACKAGE OUTLINE

BOTTOM VIEW

0.05 C

NOTE 3

0.50 PITCH

8X

0.25

DIMENSIONS: MILLIMETERS

*For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION


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ESD7004/D