FPGA Implementation of Flexible Interpolators and Decimators

Institutionen fr systemteknik
Department of Electrical Engineering

Examensarbete
FPGA Implementation of Flexible Interpolators and Decimators
Examensarbete utfrt i Elektroniksystem vid Tekniska hgskolan vid Linkpings universitet av Venkatavikram Dabbugottu LiTH-ISY-EX--13/4654--SE
Linkping 2013
Department of Electrical Engineering Linkpings universitet SE-581 83 Linkping, Sweden
Linkpings tekniska hgskola Linkpings universitet 581 83 Linkping
FPGA Implementation of Flexible Interpolators and Decimators
Examensarbete utfrt i Elektroniksystem vid Tekniska hgskolan i Linkping av

Venkatavikram Dabbugottu LiTH-ISY-EX--13/4654--SE
Handledare: Examinator:
Amir Eghbali
isy, Linkpings universitet
Hkan Johansson
isy, Linkpings universitet
Linkping, 21 February, 2013
Avdelning, Institution Division, Department Division of Electronic system Department of Electrical Engineering Linkpings universitet SE-581 83 Linkping, Sweden Sprk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats vrig rapport ISBN ISRN
Datum Date
2013-002-21
LiTH-ISY-EX--13/4654--SE Serietitel och serienummer ISSN Title of series, numbering
URL fr elektronisk version

http://www.es.isy.liu.se http://www.ep.liu.se
Titel Title
Svensk titel FPGA Implementation of Flexible Interpolators and Decimators
Frfattare Venkatavikram Dabbugottu Author
Sammanfattning Abstract The aim of this thesis is to implement exible interpolators and decimators on Field Programmable Gate Array (FPGA). Interpolators and decimators of dierent wordlengths (WL) are implemented in VHDL. The Farrow structure is used for the realization of the polyphase components of the interpolation/decimation lters. A xed set of sublters and adjustable fractional-delay multiplier values of the Farrow structure give dierent linear-phase nite-length impulse response (FIR) lowpass lters. An FIR lter is designed in such a way that it can be implemented for dierent wordlengths (8-bit, 12-bit, 16-bit). Fixed-point representation is used for representing the fractional-delay multiplier values in the Farrow structure. To perform the xed-point operations in VHDL, a package called xed point package [1] is used. A 8-bit, 12-bit, and 16-bit interpolator are implemented and their performances are veried. The designs are compiled in Quartus-II CAD tool for timing analysis and for logical registers usage. The designs are synthesised by selecting Cyclone IV GX family and EP4X30CF23C6 device. The wordlength issues while implementing the interpolators and decimators are discussed. Truncation of bits is required in order to reduce the output wordlength of the interpolator and decimator.
Nyckelord Keywords Interpolation, Decimation, Linear-phase FIR interpolation, VHDL implementation of interpolators and decimators
Abstract
The aim of this thesis is to implement exible interpolators and decimators on Field Programmable Gate Array (FPGA). Interpolators and decimators of dierent wordlengths (WL) are implemented in VHDL. The Farrow structure is used for the realization of the polyphase components of the interpolation/decimation lters. A xed set of sublters and adjustable fractional-delay multiplier values of the Farrow structure give dierent linear-phase nite-length impulse response (FIR) lowpass lters. An FIR lter is designed in such a way that it can be implemented for dierent wordlengths (8-bit, 12-bit, 16-bit). Fixed-point representation is used for representing the fractional-delay multiplier values in the Farrow structure. To perform the xed-point operations in VHDL, a package called xed point package [1] is used. A 8-bit, 12-bit, and 16-bit interpolator are implemented and their performances are veried. The designs are compiled in Quartus-II CAD tool for timing analysis and for logical registers usage. The designs are synthesised by selecting Cyclone IV GX family and EP4X30CF23C6 device. The wordlength issues while implementing the interpolators and decimators are discussed. Truncation of bits is required in order to reduce the output wordlength of the interpolator and decimator.
Acknowledgments
I would like to thank my examiner Prof. Hkan Johansson and my supervisor Dr. Amir Eghbali for giving the opportunity to do my master thesis and for their help and guidance throughout the thesis period. I would also like to thank Dr. Kent Palmkvist for his valuable suggestions and help.
vii
Contents
0.1 List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 3 3 4 4 5 5 5 6 7 10 10 10 12 15 15 15 16 16 18 20 23 23 23 24 24 27 29
1 Introduction 1.1 Introduction . . . . . . 1.2 Background . . . . . . 1.3 Purpose of the Thesis 1.4 Thesis Outline . . . .
2 Interpolation and Decimation 2.1 Introduction . . . . . . . . . . . . . . . . . 2.2 Interpolation . . . . . . . . . . . . . . . . 2.3 Decimation . . . . . . . . . . . . . . . . . 2.4 Sampling Rate Conversion by a Rational Factor . . . . . . . . . . . . . . . . . . . . 2.5 Polyphase Interpolation and Decimation Structures . . . . . . . . . . . . . . . . . . 2.5.1 Polyphase Representation . . . . . 2.5.2 Noble Identities . . . . . . . . . . . 2.6 Converters with Time-Varying Coecients
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Flexible Interpolators and Decimators 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Farrow Structure . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Farrow Structure for SRC . . . . . . . . . . . . . . . . . . . . 3.4 Linear-Phase FIR Interpolation and Decimation Utilizing the row Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Interpolator and Decimator structures . . . . . . . . . 3.5 Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 VHDL Implementation 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Fixed Point Package . . . . . . . . . . . . . . . . . . . 4.3 VHDL Implementation of the Interpolator . . . . . . . 4.3.1 VHDL Implementation of the Filter H0 (z ) . . 4.3.2 VHDL Implementation of the Sublters Gk (z ) 4.3.3 VHDL Implementation of the Delay Block dk m . ix . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . Far. . . . . . . . . . . . . . . . . . . . . . . . . . .
x 4.4 4.5 Wordlength Issues in Interpolator . . . . . . . . . VHDL Implementation of the Decimator . . . . . 4.5.1 VHDL Implementation of the Delay Block 4.5.2 VHDL Implementation of Sublters . . . . . . . dk m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 34 34 35 39 39 39 39 40 40 43 45 45 51 51 51 53 53 53 54 55 56 58
5 Testbench and Simulation Results 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 5.2 Design Flow for Testing Interpolator . . . . . . . . . 5.2.1 Generating a Sine Wave . . . . . . . . . . . . 5.2.2 VHDL Testbench . . . . . . . . . . . . . . . . 5.2.3 Simulation results . . . . . . . . . . . . . . . 5.3 Testbench for the Decimator . . . . . . . . . . . . . 5.4 Synthesis and Timing Analysis . . . . . . . . . . . . 5.4.1 Synthesis and Time Quest Analyzer Reports
6 Conclusion and Future Work 6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A Appendix A.1 VHDL Code . . . . . . . . . . . . . . . . . . . . . . . A.1.1 VHDL Code for Sublter . . . . . . . . . . . . A.1.2 VHDL Code for Delay Block of Decimator . . . A.1.3 VHDL Code for Farrow Structure of Decimator A.1.4 User Package . . . . . . . . . . . . . . . . . . . Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 3.1 3.2 3.3 3.4 3.5 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 Interpolation by a factor of L. . . . . . . . . . . . . . . . . . . . . . Original sequence and the upsampled sequence by a factor of 3. . . Spectra of the original, intermediate, and output sequences. . . . . Decimation by a factor of M . . . . . . . . . . . . . . . . . . . . . . Spectra of the ltered x1 (m) and the decimated sequence. . . . . . Sampling rate converter for conversion by a rational factor L/M . . Deriving a polyphase interpolator . . . . . . . . . . . . . . . . . . . Deriving a Polyphase Decimator . . . . . . . . . . . . . . . . . . . Noble identities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Polyphase interpolator. . . . . . . . . . . . . . . . . . . . . . . . . . Polyphase decimator. . . . . . . . . . . . . . . . . . . . . . . . . . . Interpolator realization using time-varying coecients, m = nM + i and ki is the largest integer smaller than or equal to (N i)/M . . Farrow structure. . . . . . . . . . . . . . . . . . . . . Modied Farrow structure . . . . . . . . . . . . . . . Realization of the polyphase components Hm (z ) and the interpolator structure. . . . . . . . . . . . . . . . Flexible intepolator structure. . . . . . . . . . . . . . Flexible decimator structure. . . . . . . . . . . . . . . . . . . . . . . . . . HM m ( z ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 8 8 9 9 11 12 13 13 13 14 16 17 18 19 19 25 26 27 29 31 32 34 35 36 40 41 42 43 44 44 45 46 47 47 48
Flowchart for implementing the interpolator. . . . . . . . . . RTL representation of FIR lter. . . . . . . . . . . . . . . . . The Gk (z ) block with six sublters. . . . . . . . . . . . . . . . Block diagram for VHDL implementation of the interpolator. Sublters and delay multiplier chain block. . . . . . . . . . . Delay multiplier chain block with truncation. . . . . . . . . . Block diagram for VHDL implementitation of the decimator. A 16-bit delay multiplier chain block with truncations. . . . Block diagram of Decimator. . . . . . . . . . . . . . . . . . . Design ow for testing interpolator. . . . . . . . output of interpolator in Modelsim. . . . . . . . Testbench for the Interpolator. . . . . . . . . . sinusoidal signal and the interpolated sinusoidal Frequency response for the interpolator output. Frequency response for the interpolator output. Frequency response for the interpolator output. Output of the decimator in Modelsim. . . . . . Frequency response for the decimator output. . Frequency response for the decimator output. . Frequency response for the decimator output. .
. . . . . . . . . . . . . . . . . . . . . . . . . . . signal (M =3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
List of Tables
3.1 3.2 3.3 4.1 4.2 4.3 5.1 Impulse response of The lter H0 (z ) . . . . . . . . . . . . . . . . . Impulse response of sublters G0 (z ), G1 (z ), G2 (z ) . . . . . . . . . . Impulse response of sublters G3 (z ), G4 (z ), G5 (z ) . . . . . . . . . . Table of specication. . . . . . . . . . . . . . . . . . . . . . . . . . Table for operation sizing rules. . . . . . . . . . . . . . . . . . . . . Fractional-delay multiplier values for M = 8 and M = 5. . . . . . . Table for resource utilization and performance. . . . . . . . . . . . 20 21 21 24 24 30 45
0.1
List of Abbreviations
SRC-Sampling ratio conversion WL-Word length FPGA- Field programming gate array FIR- Finite impulse response VHDL- VHSIC Hardware description language ASIC - Application specic integrated circuits CPLD - Complex programmable logic device DSP - Digital signal processing CD - Compact disc DAT - Digital audio tape
Chapter 1
Introduction
1.1 Introduction
Nowadays, the modern digital systems are more complex. They consist of several DSP (Digital Signal Processing) processors that operate at dierent sampling frequencies. For example, in smart mobile phones we can nd separate DSP processors for video, photo-camera, music, video-voice recording and communication [2]. Furthermore, there are three common sample rates utilized in the audio community. They are 32 KHz stream rate for broadcast industry, 44.1 KHz stream rate for compact disc and 48 KHz for digital audio tape (DAT) [3]. A common sample rate should be employed for these signals to combine/mix the three environments digitally. The stream at lower sample rate is interpolated to increase the sample rate in-order to match the higher sample rate signal. Interpolators can be found in mixed-signal processing systems, digital receivers and in sigma-delta modulators [2]. In the sigma-delta modulators, the interpolation operation, i.e. oversampling, moves the signal frequency and quantization noise apart from each other. Decimators are used to reduce the higher sample rate to lower sample rate.
1.2
Background
For high interpolation factors most of the sample values are zero, so there is an unnecessary additional computation. The computational workload can be reduced by using the polyphase interpolators and decimators. The polyphase interpolation and decimation are ecient when compared with straightforward realization of interpolation and decimation. The disadvantages of the polyphase interpolator (decimator) structure are that they require new lters if the sample rate conversion (SRC) ratio changes. This limits the exibility of interpolation (decimation) with dierent SRC ratios. More memory is required to store the coecient if the interpolation factor is high. These problems can be solved elegantly by the linear-phase FIR interpolation (decimation) utilizing the Farrow structure. This structure is 3
Introduction
exible to the conversion factors, and also for an arbitrary set of integer factors, including prime numbers.
1.3
Purpose of the Thesis
In this thesis work, an interpolator and decimator FPGA prototype is designed. For many applications, FPGA implementation brings advantages that include: low cost, higher precision processing, design exibility, and low power. The main objective of this thesis work is to implement the exible interpolators and decimators on FPGA. The implementation is done in VHDL. In this thesis the interpolation/decimation factor can be varied from 2 to 20.
1.4
Thesis Outline
This thesis report has ve chapters. Chapter 2 provides the basics of interpolation and decimation, SRC and polyphase interpolation and decimation. It also includes the basics of SRC by rational factors. Chapter 3 gives a brief introduction to the Farrow structure, interpolation and decimation lters, SCR utilizing the Farrow structure and linear-phase FIR interpolation and decimation utilizing the Farrow structure. Chapter 4 is about the VHDL implementation of the interpolators and decimators. This chapter discusses how the FIR lter and sublters are implemented. The wordlength issues and the truncation in the design are mentioned in this chapter. Chapter 5 gives the testbench for the interpolator and decimator. The frequency response of the interpolators and decimators with dierent interpolation and decimation factors are plotted. Chapter 6 gives the conclusion and future work.
Chapter 2
Interpolation and Decimation

2.1 Introduction
There are many systems where the sampling rate of a signal needs to be converted into an equivalent signal with a dierent sampling rate [4]. Multiple sampling frequencies are used in many applications, in order to reduce and simplify the computational workload [5]. For example, in digital audio, three dierent sampling rates are used, 32 KHz in broadcasting, 44.1 KHz in digital compact disc, and 48 KHz in DAT. This chapter begins with the basics of interpolation and decimation, and a brief overview of SRC. The concepts of polyphase interpolation and decimation structures are discussed.
2.2
Interpolation
Interpolation is a process of increasing the sampling rate and the system which performs it is called interpolator [5]. The aim of the interpolation is to get a new sequence with higher sampling rate without losing the information. Interpolation is a two-stage process, rst the input signal is upsampled and then the upsampled signal is ltered. In the rst stage, L-1 zero-valued samples are inserted in between consecutive samples of the original sequence, where L is the interpolation factor. Figure 2.1 shows the block diagram of the interpolator. Figure 2.2 illustrates the original sequence x(n) and the upsampled sequence x1 (m). The new signal, generated after the upsampler is [5] x1 (m) = x( m L) 0 for m = 0, L, 2L.. otherwise. 5 (2.1)
The Fourier transform of x1 (m) can be expressed as [5]
x1 (ejT1 ) =
n=
x(n)ejnT = X (ejLT1 ).
(2.2)
In the z -domain, we have [5] X1 (z ) = X (z L ). (2.3)
Figure 2.1. Interpolation by a factor of L.
The sampling period of the new sequence x1 (m) is T1 = T L . As the sampling rate of the new sequence is increased by L, the spectrum of the sequence x1 (m) contains not only the original signal but also repeated images of the original signal. A lowpass lter is used to remove the images and the stopband edge must be at s T = L [5]. Figure 2.3 shows the spectra of the original sequence, the upsampled sequence x1 (m), and the signal after ltering y (m).
2.3
Decimation
Decimation is the process of reducing the sampling rate and the system which performs this task is called decimator [5]. Decimation of a signal with a factor M is a two-stage process. The rst stage contains an anti-aliasing lter and in the next stage, a downsampler. By extracting every M th value of a signal, the sampling rate of the signal is reduced by a factor of M . This process is done by a downsampler. Figure 2.4 shows the block diagram of the decimator. The output y (n) is [5] y (n) = x1 (nM ). (2.4) The Fourier transform of y (n) can be expressed as [5] Y (ejT ) = 1 M
M 1
X1 (ej (T1 2k/M ) ).

k=0
(2.5)
The sampling period of y (n) is T = M T1 with T1 being the sampling period for x1 (m). Figure 2.5 shows the intermediate sequence and the output sequence of the signal. The output sequence consists of a sum of shifted, expanded replicas of the original signal. The stopband attenuation of the lter should be in such a way that the signal x1 (m) is not attenuated and high enough to prevent the aliased components. The signal x1 (m) must be band limited to M [5].
2.4 Sampling Rate Conversion by a Rational Factor
Figure 2.2. Original sequence and the upsampled sequence by a factor of 3.
2.4
Sampling Rate Conversion by a Rational Factor
Sections 2.2 and 2.3 discussed the increasing or decreasing the sampling rate by an integer factor. This section gives a brief introduction on increasing the sampling rate by a rational factor. L The sampling rate can be increased by a factor of M with L > M , where L and M are integers [5]. This sampling rate is achieved rst by interpolating with a factor of L and then decimating by a factor of M , as shown in Fig. 2.6. The stopband edge of the lter H (z ) should be at s T = min(/L, /M ). Example 2.1: SRC by a rational number Consider a signal with sampling frequency of 500 Hz where the new sampling rate has to be increased to 1600 Hz. First interpolating it with a factor 16, gives 16 500 = 8000 and then decimating it by a factor of 5 (8000/5=1600 Hz), results in an increase of the sampling frequency by a factor of 3.2 [6]. In Fig. 2.6, the upsampler and the lter perform the same task as discussed in Section 2.2. After the sampling rate is increased, we discard the samples we do not need and keep the ones required. In this process, many of the samples computed via interpolation are discarded, which is an inecient process. To implement fractional
Figure 2.3. Spectra of the original, intermediate, and output sequences.
Figure 2.4. Decimation by a factor of M .
2.4 Sampling Rate Conversion by a Rational Factor
Figure 2.5. Spectra of the ltered x1 (m) and the decimated sequence.
Figure 2.6. Sampling rate converter for conversion by a rational factor L/M .
10
interpolation and decimation eectively, there are many advanced techniques [5]. One ecient way is the polyphase interpolation and decimation.
2.5
2.5.1
Polyphase Interpolation and Decimation Structures

Polyphase Representation
This is a three-step process. First, M signals are formed from h(n), where h(n) is a sum of M partial signals [5] hi (n) = h(nM + i), i = 0, 1, 2....., M 1. Second, the hi (n) are upsampled by M , i.e., hi
(M )
(2.6)
(n) =
n hi ( M ) for n = 0, L, 2L.. 0 otherwise. (M )
(2.7)
Third, summing all the shifted versions of hi

M 1
(n) as (2.8)
h(n) =
i=0
hi
(M )
(n i).
The polyphase representation of a signal h(n) in the z -domain is [5]

M 1
H (z ) =
i=0
z i Hi (z m ),
(2.9)
where Hi (z ) =
hi (n)z
n=0
=
n=0
hi (nM + i)z n .
(2.10)
2.5.2
Noble Identities
The noble identities allows to move the order of upsampling/downsampling and ltering [7]. Figure 2.9 shows the representation of the noble identities. Combination of the polyphase representation and noble identities gives the ecient realization of multirate structures. For example with M =2, the polyphase representation of H (z ) is derived from Eq. (2.9) as H (z ) = H0 (z 2 ) + z 1 H1 (z 2 ). (2.11)
From the above equation, H (z ) is an addition of two sublters and a delay shown in Fig. 2.7. Using the noble identities, the upsampler is moved forward as shown in Fig. 2.7. In reality the polyphase interpolator is realized as shown in Fig. 2.10, where a device called commutator is used instead of summation at the output.
2.5 Polyphase Interpolation and Decimation Structures
11
Figure 2.7. (a) Interpolation by two, (b) obtained structure utilizing polyphase representation from Eq. 2.11, (c) restructured of (b), (d) polyphase interpolator using noble identities and (e) polyphase interpolator with commutator.
12
Figure 2.8. (a) Decimation by 2, (b) polyphase decimator for M =2, and (c) polyphase decimator with commutator.
At each time instant, the inputs of the summation has only one non-zero sample, so the output can be taken alternatively, beginning from the upper branch. A decimator is derived from the interpolator by reversing the signal-ow graph and replacing the upsampler by a downsampler [8] which is shown in Fig. 2.8. The polyphase interpolator and decimator are shown in Figs. 2.10 and 2.11. In these structures, all the sublters operate at the lower sampling rate which leads to eective interpolation and decimation.
2.6
Converters with Time-Varying Coecients
In the polyphase interpolation/decimation we have M parallel sublters. If all the sublters are FIR lters with direct form structures, then it is possible to share the delay elements between the sublters. The interpolator/decimator can be realised by changing the lter coecients periodically, that is with time-varying coecients. The interpolator can be realized by a lter with periodically timevarying coecients [5], as illustrated in Fig 2.12. The input signal x(n) is fed into a chain of Ni cascaded delay elements, where Ni denotes the order of the lter. The content in the delay elements are multiplied
2.6 Converters with Time-Varying Coecients
13
Figure 2.9. Noble identities.
Figure 2.10. Polyphase interpolator.
Figure 2.11. Polyphase decimator.
14
by the impulse response values of hi (n), hi (n)=h(nM + i), i = 0, 1, ..., M 1 [5]. The output signal y (m) at the time instance nM + i is [5]
Ni
y (nM + i) =
k=0
hi (k )x(n k )
(2.12)
Figure 2.12. Interpolator realization using time-varying coecients, m = nM + i and ki is the largest integer smaller than or equal to (N i)/M .
Chapter 3
Flexible Interpolators and Decimators

3.1 Introduction
This chapter gives a brief introduction to the Farrow structure, interpolation/decimation lters, SRC utilizing the Farrow structure, and linear-phase FIR interpolation and decimation utilizing the Farrow structure. The Farrow structure based interpolators and decimators have been used for converting sampling rate from 44.1 KHz to 48 KHz in digital audio [9]. The Farrow structure based interpolators are used in applications like symbol timing recovery in QAM demodulation receiver [9], echo cancellation in digital modems and sampling rate equalization in WIMAX and GSM communication systems [9].
3.2
Farrow Structure
The ecient way of implementing the polyphase interpolation/decimation lters are by using the Farrow structure. The Farrow structure is composed of xed FIR lters. The output of each lter is obtained after a delay of a single unit from the previous lter output [9]. Figure 3.1 shows the Farrow structure. The transfer function is [8]
L
H (z ) =
k=0
Gk (z )dk m,
m = 1, 2, .....M 1
(3.1)
where G0 (z ), G1 (z ), .... GK (z ) are linear-phase FIR lters and dm are the fractionaldelay coecients. The lters Gk (z ) are designed to obtain a fractional-delay lter H (z ) = z dm [7]. If the fractional-delay coecient value is the same for all inputs, the Farrow structure gives the delayed version of inputs, with a delay dm . The Farrow structure used in this thesis is shown in Fig. 3.1. 15
16
Figure 3.1. Farrow structure.
3.3
Farrow Structure for SRC
In the polyphase interpolation and decimation structures, if the SRC ratio changes, new lters are needed which limits the exibility of interpolating and decimating with dierent SRC ratios. The polyphase interpolation and decimation structures lead to a large number of coecients and more memory is required if the interpolation/decimation factor is high. This can be solved elegantly by utilizing the Farrow structure [10]. To perform any integer SRC, it is required to modify the fractional-delay values required by the Farrow structure and, it is possible to use one set of sublters [11]. A delayed version of the input signal is generated by the Farrow structure, when dm is constant for all input samples [11]. The Farrow structure performs SRC, if the dm value changes for every input signal. For example re-sampling a 8 KHz signal to 44.1 KHz, requires interpolation by 441 and decimation by 80. For these conversions, the polyphase interpolation and decimation structures are not preferable. Hence, SRC utilizing Farrow structure are preferred [10]. For more literature on SRC utilizing Farrow structure we refer to [8], [7], [12]. The interpolation/decimation lters in [8] uses the modied Farrow structure shown in Fig. 3.2. But in this thesis the Farrow structure shown in Fig. 3.1 is used. There is no dierent in these two structures, the structure shown in Fig. 3.1 is used because, it is easy to implement in VHDL.
3.4
Linear-Phase FIR Interpolation and Decimation Utilizing the Farrow Structure
This section gives the introduction of the interpolation and decimation lter transfer function proposed in [8] and a brief description on linear-phase FIR interpolator
3.4 Linear-Phase FIR Interpolation and Decimation Utilizing the Farrow Structure 17
Figure 3.2. Modied Farrow structure
and decimator. For the design of the interpolation and decimation lters we refer to [8]. The lters proposed in [8] are based on the properties of interpolation and decimation lters polyphase components. The transfer function of the polyphase components is written as [8]
M 1
H (z ) =
m=0
z m Hm (z M )
(3.2)
where Hm (z ) are polyphase components and H (z ) is a linear-phase interpolation or decimation lowpass lter. The lter H (z ) is to approximate z N/2 in the ideal passband region T [/M, /M ] and zero in the ideal stopband T [, /M ] [/M, ] [8]. This approximation is achieved when the delay of each z m Hm (z M ) approximates z N/2 in the passband region [8]. That is, z m Hm (z M ) z N/2 Hm (z M ) z ((N/2)m) Hm (z ) z ((N/2)m)/M . (3.3)
From Eq. 3.3, it follows that Hm (z ) is an allpass lter with a fractional delay of ((N/2) m)/M . Based on this approximation, the polyphase components are selected [8]. First H0 (z ), is an N0 th-order, Type-I linear-phase FIR lter of even order. The selection of H0 (z ) ensures that H0 (z M ) can approximate z N/2 , provided N satises [8] N = N0 M. (3.4) The polyphase components Hm (z ) are realized using the Farrow structure shown in Fig. 3.1 and the transfer functions Hm (z ) are expressed as [8]
L
Hm ( z ) =
k=0
dk m Gk (z ),
m = 1, 2, .....M 1
(3.5)
18
Figure 3.3. Realization of the polyphase components Hm (z ) and HM m (z ) in the interpolator structure.
where Gk (z ) are odd-order sublters (linear-phase FIR lters) of order N1 and dm represents fractional-delay coecients which are anti-symmetric [8]. The impulse response of sublters, i.e., gk (n) = gk (N1 n) (k is even) for symmetric and gk (n) = gk (N1 n) (k is odd) for anti-symmetric. The sublters Gk (z ) are here of odd order [8]. The lter Hm (z ) approximates an all-pass lter with a fractional delay of N1 /2 + dm , provided N satises [8] N = (N1 + 1)M. The delay ((N/2) m)/M must be equal to the delay N1 /2 + dm leading to dm = m 1 + M 2 (3.7) (3.6)
where dm possess anti-symmetric according to dm = dM m .
3.4.1
Interpolator and Decimator structures
In the interpolation and decimation lters, the polyphase components Hm (z ) as in Eq.( 3.5) have dm exhibiting anti-symmetric form, so the polyphase components Hm (z ) and HM m (z ) can be written as [8] Hm (z ) = Fm1 (z ) + Fm2 (z ) HM m (z ) = Fm1 (z ) Fm2 (z ) where Fm1 (z ) =
k=0 L/2 2k dm G2k (z )
(3.8) (3.9) (3.10)
3.4 Linear-Phase FIR Interpolation and Decimation Utilizing the Farrow Structure 19
Figure 3.4. Flexible intepolator structure.
Figure 3.5. Flexible decimator structure.
(L+1)/2
Fm2 (z ) =
k=1
k 1 d2 G2k1 (z ) m
(3.11)
where L/2 is the largest integer smaller than or equal to L/2 and for (L +1)/2 it is largest integer smaller than or equal to (L + 1)/2. The polyphase components Hm (z ) and HM m (z ) can be realized simultaneously using the same dm [8]. The even polyphase components are realized from Fm1 (z ) and odd polyphase components by Fm2 (z ) as shown in Fig. 3.3. When M is even, dM/2 = 0 resulting in HM/2 (z ) = G0 (z ). Also note that for M = 2, the lters reduce to Type-I linear-phase FIR lters. The interpolator can be realized as shown in Fig. 3.4. The wide arrow between Gk (z ) and dk m indicates L + 1 parallel signals. The interpolator structure has three main blocks, they are H0 (z ), Gk (z ) and dk m , where H0 (z ) is a linear-phase FIR lter of even order and Gk (z ) are linear-phase FIR sublters of odd order. The block dk m contains all the fractional-delay multipliers and adders to form the polyphase component outputs. The decimator structure is a transpose of interpolator structure and is shown in Fig. 3.5.
20
Flexible Interpolators and Decimators h(0) = 0.00194202018921064 h(2) = 0.00852167200160272 h(4) = 0.0198982811398188 h(6) = 0.0326345311590520 h(8) = 0.0411489015845974 h(10) = 0.0411489015845974 h(12) = 0.0326345311590520 h(14) = 0.0198982811398188 h(16) = 0.00852167200160272 h(18) = 0.00194202018921064 h(1) = 0.00454034034339180 h(3) = 0.0137483480181378 h(5) = 0.0264294829651506 h(7) = 0.0377645426334144 h(9) = 1.04233196249064 h(11) = 0.0377645426334144 h(13) = 0.0264294829651506 h(15) = 0.0137483480181378 h(17) = 0.00454034034339180
Table 3.1. Impulse response of The lter H0 (z ) .
By adding additional dk m (converter) to the same lters (H0 (z ),Gk (z )) several interpolators can be implemented simultaneously [8].
3.5
Filter Design
1 c HR (T ) 1 + c , s HR (T ) s , T [0, c T ]
The specication of the overall lowpass lter is T [s T, ] (3.12)
The frequency response of the overall lter can be written as H (ejT ) = ejN T /2 HR (T ) where N N HR (T ) = h( ) + 2 h( n) cos(T n). 2 2 n=1
N/2
(3.13)
HR (T ) is the real zero-phase frequency response of H (z ). The passband edge is at c T = /M , > 0, and the stopband edge is assumed to be at /M or /M + . Refer to the paper [8] for optimization problem. The values for L and N1 are selected in a proper way. The value of L is selected from the outline of [13]. The values of L and N1 are more or less independent of M . In this thesis the specications of the lter are c T = 0.5/M , s T = /M , c = 0.01, and s = 0.001. We have L = 5 and N1 = 17. The impulse response of lter H0 (z ) is shown in Table 3.1. The impulse responses of the sublters Gk (z ) are shown in Tables 3.2 and 3.3. The coecients of the lter H0 (z ) and sublters Gk (z ) are rounded to its respective wordlength. The WL=6 for 8-bit interpolator/decimator, WL=14 for 16-bit interpolator/decimator. The extra 2-bits are sign bit and gaurd bit. h0_rounded_values = round(h0. 2W L ); The wordlength issues and rounding of coecients are dissused in Chapter 4.
3.5 Filter Design
21
g0 (0) = g0 (17) = 0.000423907467491607 g0 (1) = g0 (16) = 0.00278295410277547 g2 (2) = g0 (15) = 0.00778067242572729 g0 (3) = g0 (14) = 0.0168907327062642 g0 (4) = g0 (13) = 0.0321984118929472 g0 (5) = g0 (12) = 0.0573660539510253 g0 (6) = g0 (11) = 0.101173603068474 g0 (7) = g0 (10) = 0.195576074607548 g0 (8) = g0 (9) = 0.630911493115840 g0 (9) = 0.630911493115840 g0 (10) = 0.195576074607548 g0 (11) = 0.101173603068474 g0 (12) = 0.0573660539510253 g0 (13) = 0.0321984118929472 g0 (14) = 0.0168907327062642 g0 (15) = 0.00778067242572729 g0 (16) = 0.00278295410277547 g0 (17) = 0.000423907467491607
Table 3.2. Impulse response of sublters G0 (z ), G1 (z ), G2 (z ) .
Table 3.3. Impulse response of sublters G3 (z ), G4 (z ), G5 (z ) .
Chapter 4
VHDL Implementation
4.1 Introduction
In this thesis work, the linear-phase FIR interpolator and decimator are implemented in VHDL (VHSIC Hardware Description Language) where VHSIC stands for Very High Speed Integrated Circuits. A brief introduction to the linear-phase FIR interpolator and decimator was given in Chapter 2. The VHDL is intended for the circuit simulations and synthesis but not all the VHDL designs are synthesizable. The main applications of VHDL are in CPLDs (Complex Programmable Logic Devices), FPGAs (Field programmable Gate Arrays) and in the eld of ASICs (Application Specic Integrated Circuits). The VHDL code can be simulated, synthesized and implemented using several EDA tools [14]. Some EDA tools are Alteras Quartus II, for Alteras CPLD/FPGA and Xilinxs ISE suite, for Xilinxs CPLD/FPGA. In this thesis work, the VHDL code is simulated in Modelsim, version Modelsim.SE 6.4 and compiled in Quartus II for timing analysis and register usage. VHDL is mostly used for simulation and synthesis of electronic designs. The process of compiling and mapping the VHDL code into an FPGA or an ASIC is called synthesis. All the VHDL constructs are not suitable for synthesis. For example, the construct wait for 10 ns is not synthesizable but valid for simulations. The tools for synthesis of VHDL are inexpensive when compared with ASIC synthesis tools. Both the hardware design and testbenches are portable between design tools and vendors. The VHDL provides technology independent design [14]. To implement the design in new technology, we can go back to the behavioral VHDL description and then implement it the new technology knowing the correct functionality is preserved [14].
4.2
Fixed Point Package
A package called Ieee_proposed.f ixed_pkg is used for implementing the fractionaldelay block (dk m ) in the interpolator and decimator. The xed point package 23
24 Simulation tool H0 (z )alinear phaseF IRf ilter Gk (z ) sublters L=5
VHDL Implementation ModelSim SE-64 6.4a, MATLAB, Quartus-II order=18 order=17 k=0,1,2...5
Table 4.1. Table of specication.
Operation A+B A-B A*B A rem B
Result Range Max(Aleft, Bleft)+1 downto Min(Aright, Bright) Max(Aleft, Bleft)+1 downto Min(Aright, Bright) Aleft + Bleft +1 downto Aright + Bright Min(Aleft, Bleft) downto Min(Aright, Bright)
Table 4.2. Table for operation sizing rules.
(ieee_proposed.f ixed_pkg ) has the advantage of representing the numbers less than 1.0 and rational values which has a xed decimal point. Fixed point is a step between integer math and oating point [1]. Fractional valued multipliers are used in the interpolators and decimators. This package is used for the fractional or rational multiplication and addition operations. Table 4.2 shows the operation sizing rules. For more information we refer to the xed point package users guide [1].
4.3
VHDL Implementation of the Interpolator
The owchart in Fig. 4.1 explains the step-by-step procedure ow of implementing the linear-phase FIR interpolator. The lter H0 (z ) has to be implemented in such a way that the design has to be re-used for a sublter implementation. The lter H0 (z ) coecients are xed, so the coecients are given as constants in the implementation instead of giving them as inputs. The sublters Gk (z ) block has six sublters with dierent coecients but of same order. Instead of designing six sublters, a sublter can be designed by making coecients as inputs. Therefore, six sublters are implemented by instantiating the sublter six times.
4.3.1
VHDL Implementation of the Filter H0 (z )

N 1
The transfer function of an FIR lter is [4] H (z ) =

k=0
h[k ]z k .
(4.1)
In the time domain, we have

N 1
y [ n] =
k=0
h[k ]x[n k ].
(4.2)
4.3 VHDL Implementation of the Interpolator
25
Figure 4.1. Flowchart for implementing the interpolator.
The input signal is stored in the shift registers and the output of the shift registers is connected to the multipliers and then to the adders as shown in Fig. 4.2. The VHDL code of lter H0 (z ) is shown in 4.1. It is very important that the VHDL code is written in such a way that it is reusable or shared. It should be as generic as possible. By changing the order, XIN _W L and COEF _W L in line 13, an FIR lter of any order and wordlength can be implemented. The lter H0 (z ) has xed coecients, so they can be given as constants, shown in lines 36 and 37. When RST is HIGH the coecients are converted to signed bits. When RST is LOW the input signal stored in the shift registers is multiplied with coecients and then added, as shown in between lines 55-64.
Listing 4.1. VHDL code for lter H0 (z )
1 H0_FIR FILTER
26
VHDL Implementation
Figure 4.2. RTL representation of FIR lter.
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
MAIN CODE LIBRARY IEEE ; USE IEEE . STD_LOGIC_1164 . ALL ; USE IEEE . NUMERIC_STD . ALL ; USE IEEE . STD_LOGIC_unsigned . ALL ; LIBRARY W O R K; USE W O R K. ALL ; ENTITY ENTITY H0_FILTER_16BIT I S GENERIC (ORDER : INTEGER: = 1 8 ;XIN_WL : INTEGER: = 1 6 ;COEF_WL: INTEGER: = 1 6 ) ; WL I S XIN_WL . IT I S W O R D LENGTH OF THE INPUT SIGNAL . COEF_WL I S W O R D LENGTH OF THE COEFFICIENTS OR TAPS . PORT( CLK, RST : IN STD_LOGIC ; XIN : IN SIGNED (XIN_WL 1 D O W N T O 0 ) ; INPUT PORT YOUT: OUT SIGNED ( (XIN_WL + COEF_WL 1) D O W N T O 0 ) OUTPUT PORT ); END H0_FILTER_16BIT ; ARCHITECTURE ARCHITECTURE BEHAVIOURAL OF H0_FILTER_16BIT I S SIG_ARR I S D FLIP_FLOP ARRAY. TYPE SIG_ARR I S ARRAY (ORDER 1 D O W N T O 0 ) OF SIGNED (XIN_WL 1 D O W N T O 0) ; COEFFICIENTS TYPE COEF_ARR I S ARRAY (ORDER D O W N T O 0 ) OF SIGNED (COEF_WL 1 D O W N T O 0) ; t y p e COEFFICIENTS i s a r r a y ( 0 t o o r d e r ) o f i n t e g e r ; SIGNALS SIGNAL DFF : SIG_ARR ; CONSTANT COEF_H0 : COEFFICIENTS: = ( 6 0 , 9 2 , 1 5 9 , 2 4 7 , 3 3 6 , 4 3 0 , 5 1 7 , 5 9 3 , 6 3 8 , 17040 , 638 ,593 , 517 ,430 , 336 ,247 , 159 ,92 , 60) ; BEGIN PROCESS INTAL : PROCESS(CLK, RST) VARIABLE M_OUT,ADD_OUT: SIGNED ( (XIN_WL + COEF_WL 1) D O W N T O 0 ) : = (OTHERS= > 0 ) ; v a r i a b l e COEF :COEF_ARR; BEGIN IF (RST= 1 ) THEN FOR I IN ORDER 1 D O W N T O 0 LOOP f o r j i n XIN_WL 1 downto 0 l o o p DFF( I ) ( j ) <= 0 ; end l o o p ; END LOOP ; FOR I IN 0 TO ORDER LOOP COEF( I ) := t o _ s i g n e d (COEF_H0( i ) ,COEF_WL) ; END LOOP ; ELSIF RISING_EDGE(CLK) THEN ADD_OUT:= COEF( 0 ) XIN ; FOR I IN 1 TO ORDER 1 LOOP M_OUT:=COEF( I ) DFF(ORDER 1 I ) ; ADD_OUT:=ADD_OUT + M_OUT; END LOOP ;

61 62 63 64 65 DFF <= XIN & DFF(ORDER 1 D O W N T O 1) ; end i f ; YOUT <= ADD_OUT; END PROCESS ; END BEHAVIOURAL ;
27
4.3.2
VHDL Implementation of the Sublters Gk (z )
In the block Gk (z ) we have six sublters. Instead of implementing six dierent sublters, it is ecient to implement one sublter and it can be instantiated Ltimes (L=5, where k =0,1,2,3,4,5) to implement the Gk (z ) block. The coecients are dierent for every sublter. A sublter can be implemented from the lter code of H0 (z ), by changing the coecients to inputs instead of constants. Figure. 4.3 shows the instantiation of six sublters forming the block Gk (z ). The VHDL code for the sublter is given in the appendix A.1.1.
Figure 4.3. The Gk (z ) block with six sublters.
The VHDL code for the block Gk (z ) is shown 4.2. The sublter named F IR_F ILT ER_16BIT is declared rst, which is shown in between lines 3138. From line 36 it is clear that the sublter has an input port for coecients and the input port is of type SIG_16, which is a special array declared in the user package. The user package is shown in the appendix. The coecients of six sublters are declared in between lines 42-53. In the process (lines 65-89) the coecients are converted into signed bits. The process executes when there is a change in the reset. All the sublters instantiated between lines 93-104 are executed simultaneously.
Listing 4.2. VHDL code for block Gk (z )
1 2 3 MAIN CODE LIBRARY IEEE ;
28
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 USE IEEE . STD_LOGIC_1164 . ALL ; USE IEEE . NUMERIC_STD . ALL ; USE W O R K. PKG_SIGNED . ALL ; USER DEFINED PACKAGE u s e IEEE . STD_LOGIC_unsigned . ALL ; USE STD . TEXTIO . ALL ; LIBRARY W O R K; USE W O R K. ALL ; ENTITY
VHDL Implementation
ENTITY FARROW_STRUCTURE_16BIT I S GENERIC( F : INTEGER: = 6 ;WL: INTEGER: = 1 6 ; COEF_WL: INTEGER: = 1 6 ;ORDER: INTEGER: = 1 7 ) ; PORT( CLK, RST : IN STD_LOGIC ; XIN : IN SIGNED (WL 1 D O W N T O 0) ; FOUT :OUT SIG_32 ( 1 TO F ) CHANGE WHEN WL I S CHANGED ); END FARROW_STRUCTURE_16BIT ; ARCHITECTURE ARCHITECTURE BEHAV OF FARROW_STRUCTURE_16BIT I S COMPONENT DECLARATION SUB FILTER (G( Z ) ) COMPONENT FIR_FILTER_16BIT I S GENERIC (WL: INTEGER) ; PORT( CLK, RST : IN STD_LOGIC ; XIN : IN SIGNED (WL 1 D O W N T O 0) ; COEF : IN SIG_16 ( 0 TO ORDER) ; YOUT: OUT SIGNED( 2 WL 1 D O W N T O 0) ); END COMPONENT; ARRAY DECLARATION type c o e f f i c i e n t s i s array (0 to order ) o f i n t e g e r ; c o n s t a n t coef_1 : c o e f f i c i e n t s :=(33 , 69 ,164 , 323 ,582 , 989 ,1699 , 3230 , 10348 ,10348 , 3230 ,1699 , 989 ,582 , 323 ,164 , 69 ,33) ; c o n s t a n t coef_2 : c o e f f i c i e n t s :=( 254 ,462 , 711 ,1058 , 1510 ,1978 , 2706 , 4361 , 23066 ,23066 , 4361 ,2706 , 1978 ,1510 , 1058 ,711 , 462 ,254) ; c o n s t a n t coef_3 : c o e f f i c i e n t s :=( 101 ,110 , 636 ,1410 , 2635 ,4605 , 7911 ,14322 , 9288 , 9288 ,14322 , 7911 ,4605 , 2635 ,1410 , 636 ,110 , 101) ; c o n s t a n t coef_4 : c o e f f i c i e n t s :=(62 , 973 ,1276 , 1983 ,3213 , 4208 ,6917 , 13282 ,23043 , 23043 ,13282 , 6917 ,4208 , 3213 ,1983 , 1276 ,973 , 62) ; c o n s t a n t coef_5 : c o e f f i c i e n t s :=( 388 , 259 ,801 , 1357 ,2033 , 3390 ,5255 , 6306 , 3064 ,3064 , 6306 ,5255 , 3390 ,2033 , 1357 ,801 , 259 , 388) ; c o n s t a n t coef_6 : c o e f f i c i e n t s :=(44 , 139 , 43 ,99 , 157 ,347 , 1143 ,3033 , 4898 ,4898 , 3033 ,1143 , 347 ,157 , 99 ,43 ,139 , 44) ; SIGNALS DECLERATION SIGNAL FIR_OUT : SIG_32 ( 1 TO F ) ; CHANGE COEF_WL CHANGES SIGNAL COEF_FARROW_1: SIG_16 ( 1 TO ORDER+1) ; CHANGE COEF_WL CHANGES SIGNAL COEF_FARROW_2: SIG_16 ( 1 TO ORDER+1) ; CHANGE COEF_WL CHANGES SIGNAL COEF_FARROW_3: SIG_16 ( 1 TO ORDER+1) ; CHANGE COEF_WL CHANGES SIGNAL COEF_FARROW_4: SIG_16 ( 1 TO ORDER+1) ; CHANGE COEF_WL CHANGES SIGNAL COEF_FARROW_5: SIG_16 ( 1 TO ORDER+1) ; CHANGE COEF_WL CHANGES SIGNAL COEF_FARROW_6: SIG_16 ( 1 TO ORDER+1) ; CHANGE COEF_WL CHANGES SIGNAL TEST :D_ARRAY; BEGIN PROCESS( r s t ) VARIABLE COEF_VAR_1 : SIG_16 ( 1 VARIABLE COEF_VAR_2 : SIG_16 ( 1 VARIABLE COEF_VAR_3 : SIG_16 ( 1 VARIABLE COEF_VAR_4 : SIG_16 ( 1 VARIABLE COEF_VAR_5 : SIG_16 ( 1 VARIABLE COEF_VAR_6 : SIG_16 ( 1 BEGIN TO TO TO TO TO TO ORDER+1) ; CHANGE ORDER+1) ; CHANGE ORDER+1) ; CHANGE ORDER+1) ; CHANGE ORDER+1) ; CHANGE ORDER+1) ; CHANGE COEF_WL COEF_WL COEF_WL COEF_WL COEF_WL COEF_WL CHANGES CHANGES CHANGES CHANGES CHANGES CHANGES
FOR i IN 0 TO o r d e r 1 LOOP COEF_VAR_1( I +1) :=TO_SIGNED(COEF_1( I ) COEF_VAR_2( I +1) :=TO_SIGNED(COEF_2( I ) COEF_VAR_3( I +1) :=TO_SIGNED(COEF_3( I ) COEF_VAR_4( I +1) :=TO_SIGNED(COEF_4( I ) COEF_VAR_5( I +1) :=TO_SIGNED(COEF_5( I ) COEF_VAR_6( I +1) :=TO_SIGNED(COEF_6( I ) END LOOP ; COEF_FARROW_1 <= COEF_VAR_1 ; COEF_FARROW_2 <= COEF_VAR_2 ; COEF_FARROW_3 <= COEF_VAR_3 ; COEF_FARROW_4 <= COEF_VAR_4 ; COEF_FARROW_5 <= COEF_VAR_5 ; COEF_FARROW_6 <= COEF_VAR_6 ; END PROCESS ; COMPONENT INSTANTIATED
,COEF_WL) ,COEF_WL) ,COEF_WL) ,COEF_WL) ,COEF_WL) ,COEF_WL)
; ; ; ; ; ;
FIR1 : FIR_FILTER_16BIT GENERIC MAP(WL) PORT MAP(CLK, RST , XIN ,COEF_FARROW_6, FIR_OUT ( 1 ) ) ; FIRST SUBFILTER

95 96 97 98 99 100 101 102 103 104 105 106 107 FIR2 : FIR_FILTER_16BIT GENERIC MAP(WL) PORT MAP(CLK, RST , XIN ,COEF_FARROW_5, FIR_OUT ( 2 ) ) ; SECOND SUBFILTER FIR3 : FIR_FILTER_16BIT GENERIC MAP(WL) PORT MAP(CLK, RST , XIN ,COEF_FARROW_4, FIR_OUT ( 3 ) ) ; THIRD SUBFILTER FIR4 : FIR_FILTER_16BIT GENERIC MAP(WL) PORT MAP(CLK, RST , XIN ,COEF_FARROW_3, FIR_OUT ( 4 ) ) ; FOURTH SUBFILTER FIR5 : FIR_FILTER_16BIT GENERIC MAP(WL) PORT MAP(CLK, RST , XIN ,COEF_FARROW_2, FIR_OUT ( 5 ) ) ; FIFTH SUBFILTER FIR6 : FIR_FILTER_16BIT GENERIC MAP(WL) PORT MAP(CLK, RST , XIN ,COEF_FARROW_1, FIR_OUT ( 6 ) ) ; SIXTH SUBFILTER FOUT <= FIR_OUT ; END BEHAV;
29
4.3.3
VHDL Implementation of the Delay Block dk m
Figure 4.4. Block diagram for VHDL implementation of the interpolator.
Figure 4.4 shows how an interpolator is implemented in VHDL. The lter H0 (z ) and sublters Gk (z ) are instantiated rst and then the delay block code is written. The components H0 (z ), Gk (z ) instantiation is showed in between lines 31-44 in 4.3. These components are declared in lines 58 and 59. The output of Gk (z ) is connected to a signal SOU T and the output of H0 (z ) is connected to a signal H 0_SIGN . The delay block dk m consists of M 1 delay multiplier chain blocks, where M is interpolation factor. Each delay multiplier chain block gives one polyphase component Hm , where m = 1, 2.., M 1. The lter H0 (z ) gives the zeroth polyphase component H0 . The lower part of Fig. 4.5 shows a delay multiplier chain block. The Fig. 4.5 shows how the sublters and delay multiplier chain block can form a Farrow structure. The sampled value from sublter G5 (z ) is multiplied by the fractional-delay multiplier value and then added to the sampled value from the sublter G4 (z ). This value is again multiplied with the fractional-delay multiplier value and then added to the sampled value of sublter G3 (z ), this process ends after adding the sampled value from the sublter G0 (z ) as shown between lines 110-117 in the code below. The values dm are generated using Eq. (4.3).
30 Even Factor M = 8 d0 =1/2 d1 =3/8 d2 =1/4 d3 =1/8 d4 =0 d5 =-1/8 d6 =-1/4 d7 =-3/8
VHDL Implementation Odd Factor M = 5 d0 =1/2 d1 =3/10 d2 =1/10 d3 =-1/10 d4 =-3/10
Table 4.3. Fractional-delay multiplier values for M = 8 and M = 5.
Equation. (4.3) is a modied form of Eq. (4.4). dm+1 = where d0 = 1/2. 1 + dm M (4.3)
m 1 + (4.4) M 2 The generation of fractional-delay multiplier value (dm ) is shown in between lines 93-103. The values dm for M =8 and M =5 are given in Table 4.3. The Fractionaldelay multiplier values are converted into binary representation using to_sf ixed. Example 3.1 shows how a fractional number is converted into binary. As the addition and multiplication rules are dierent compared with the normal binary addition and multiplication, truncation of bits are required. RESIZE is used for truncating the bits and an example is shown below. dm = Example 4.1: conversion and resizing variable ADD(16downto 5); ADD:=0000000000000000.00000 initially. ADD := to_sf ixed(15.5, ADD); The binary value of ADD is: ADD:=0000000000001111.10000. To change the wordlength from 16-bit to 8-bit variable size_ADD (8downto 5) size_ADD := resize(ADD, size_ADD); size_ADD=00001111.10000 Figure 4.6 shows how a delay multiplier chain block for 16-bit interpolator is implemented and also shows where truncation of bits is performed. The sampled values of the sublters are 16-bit (15 downto 0) and it is multiplied with 8-bit (2 downto -5) delay multiplier dm value results in 24-bit (18 downto -5). The multiplied value is added to the 16-bit (15 downto 0) sample from the next sublter resulting in 25-bits (19 downto -5). This 25-bit value is truncated to 16-bit (15 downto 0). The dm values are small and when the sampled output of the sublters
31
Figure 4.5. Sublters and delay multiplier chain block.
are multiplied by the delay multiplier values they become very small. So ve LSB and four MSB bits are truncated, line 114 from the code shows the truncation of bits after addition.
Listing 4.3. VHDL code for the interpolator
1 2 3 4 5 6 7 8 9 10 11 12 13 14 MAIN CODE LIBRARY IEEE ; USE IEEE . STD_LOGIC_1164 . ALL ; USE IEEE . NUMERIC_STD . ALL ; l i b r a r y ieee_proposed ; u s e i e e e _ p r o p o s e d . f i x e d _ p k g . a l l ; f i x e d p o i n t p a c k a g e s USE W O R K. PKG_SIGNED . ALL ; USER DEFINED PACKAGE u s e IEEE . STD_LOGIC_unsigned . ALL ; u s e STD . t e x t i o . a l l ; LIBRARY W O R K; USE W O R K. ALL ; ENTITY
32
VHDL Implementation
Figure 4.6. Delay multiplier chain block with truncation.
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
ENTITY DELAY_BLOCK_RW_16BIT I S GENERIC( F : INTEGER: = 6 ; WL: INTEGER: = 1 6 ; DELAY_WL: INTEGER: = 8 ; COEF_WL: INTEGER: = 1 6 ;IP_FACTOR : INTEGER: = 2 ) ; PORT( CLK, RST : IN STD_LOGIC ; XIN : IN SIGNED (WL 1 D O W N T O 0) ; FIN :OUT SIG_32 ( 0 TO F 1) ; CHANGE WHEN WL OR COEF_WL I S CHANGED CHANGE WHEN WL OR COEF_WL I S CHANGED (SPE_ARRAY) FROM PACKAGE. IOUT :OUT SPE_ARR_32( 0 TO IP_FACTOR 1) ); END DELAY_BLOCK_RW_16BIT ; ARCHITECTURE ARCHITECTURE BEHAV OF DELAY_BLOCK_RW_16BIT I S COMPONENT FARROW_STRUCTURE_16BIT I S PORT(CLK, RST : IN STD_LOGIC ; XIN : IN SIGNED (WL 1 D O W N T O 0) ; FOUT:OUT SIG_32 ( 0 TO F 1) CHANGE WHEN WL OR COEF_WL CHANGES ); END COMPONENT; COMPONENT H0_FILTER_16BIT I S PORT( CLK, r s t : IN STD_LOGIC ; XIN : IN SIGNED ( WL 1 D O W N T O 0 ); YOUT :OUT SIGNED (COEF_WL + WL 1 D O W N T O 0) ); END COMPONENT; ARRAY DECLERATION TYPE SIG_ARR_1_8 I S ARRAY ( 0 TO IP_FACTOR) OF SFIXED ( 2 D O W N T O 5) ; IF (A+B) THEN TYPE SIG_ARR_9 I S ARRAY ( 0 TO IP_FACTOR 1) OF SFIXED ( 3 D O W N T O 5) ; SIGNAL DECLERATION SIGNAL SOUT : SIG_32 ( 0 TO F 1) ; CHANGE WHEN WL OR COEF_WL I S CHANGED CHANGE WHEN WL OR COEF_WL I S CHANGED (SPE_ARRAY) FROM PACKAGE. SIGNAL WRITEOUT: SPE_ARR_32( 0 TO IP_FACTOR 1) ; SIGNAL H0_SIGN : SIGNED (COEF_WL + WL 1 D O W N T O 0) ; s i g n a l t e s t : SFIXED ( 2 D O W N T O 5) ; BEGIN COMPONENT i n s t a n c a t i o n FARROW: FARROW_STRUCTURE_16BIT PORT MAP(CLK, RST , XIN , SOUT) ; T_FIR_FILTER : H0_FILTER_16BIT PORT MAP(CLK, RST , XIN , H0_SIGN ) ; PROCESS PI : PROCESS(CLK, RST) VARIABLE Dm_SIGNED1 : SIG_ARR_9 ; VARIABLE Dm_SIGNED : SIG_ARR_1_8 ; VARIABLE TEMP_IP_FACTOR: SFIXED ( 2 D O W N T O 5) ; CHANGE WHEN WL OR COEF_WL I S CHANGED VARIABLE SOUT_TEMP: SIGS_32 ( 0 TO F 1) ;

67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 VARIABLE PROD : SFIXED (COEF_WL + WL +2 D O W N T O 5) ; VARIABLE ADD : SFIXED (COEF_WL + WL +3 D O W N T O 5) ; VARIABLE ADD_T: SFIXED (COEF_WL + WL 1 D O W N T O 0) ; VARIABLE H0 : SFIXED (COEF_WL + WL +3 D O W N T O 5) ; v a r i a b l e o n e : s f i x e d ( d e l a y _ w l 1 downto 0 ) ; v a r i a b l e M: s f i x e d ( d e l a y _ w l 1 downto 0 ) ; interpolation factor v a r i a b l e v a l u e : s f i x e d ( d e l a y _ w l downto d e l a y _ w l +1) ; f i l e file_pointer : text ; v a r i a b l e l i n e _ c o n t e n t : s t r i n g ( 1 t o (DELAY_WL + COEF_WL + WL+1) ) ; CHANGE WHEN WL OR COEF_WL I S CHANGED (SPE_ARRAY) FROM PACKAGE. v a r i a b l e b i n _ v a l u e : SPE_ARR_32( 0 TO IP_FACTOR 1) ; v a r i a b l e b i n _ v a l u e _ 1 : SFIXED (COEF_WL + WL +3 D O W N T O 5) ; v a r i a b l e line_num : l i n e ; v a r i a b l e i , j , K, v : i n t e g e r : = 0 ; v a r i a b l e char : c h a r a c t e r := 0 ; v a r i a b l e f i r s t t i m e : b o o l e a n := t r u e ; BEGIN r e p o r t " S t a r t i n g p r o c e s s PI " s e v e r i t y n o t e ; i f r i s i n g _ e d g e ( c l k ) then GENERATING Dm VALUES Dm_SIGNED( 0 ) :=TO_SFIXED ( 0 . 5 , Dm_SIGNED( 0 ) ) ; M:= t o _ s f i x e d ( I P _ f a c t o r ,M) ; o n e := t o _ s f i x e d ( 1 , o n e ) ; v a l u e : = ( o n e /M) ; TEMP_IP_FACTOR:=RESIZE(VALUE,TEMP_IP_FACTOR) ; FOR I IN 0 TO IP_FACTOR1 LOOP Dm_SIGNED1( I ) : = (TEMP_IP_FACTOR)+Dm_SIGNED( I ) ; Dm_SIGNED( I +1) :=RESIZE (Dm_SIGNED1( I ) ,Dm_SIGNED( I ) ) ; END LOOP ; CONVERTING THE INTEGER SOUT ,TO FIXED POINT FOR I IN 0 TO F1 LOOP SOUT_TEMP( I ) :=TO_SFIXED(SOUT( I ) ,SOUT_TEMP( I ) ) ; END LOOP ; MULT AND ADDING FOR EVERY INTERPOLATION FACTOR FOR I IN 1 TO IP_FACTOR1 LOOP PROD:=SOUT_TEMP( 0 ) Dm_SIGNED( I ) ; FOR J IN 1 TO F1 LOOP ADD:=PROD + SOUT_TEMP( J ) ; ADD_T:=RESIZE (ADD,ADD_T) ; PROD:=ADD_TDm_SIGNED( I ) ; END LOOP ; IOUT( I )<= ADD; WRITEOUT( I )<= ADD; END LOOP ; FIN<= SOUT ; H0:=TO_SFIXED( H0_SIGN , H0 ) ; c o n v e r t i n g t h e h0 o u t p u t t o s f i x e d . IOUT ( 0 )<=H0 ; WRITEOUT( 0 )<=H0 ; t e s t <= TEMP_IP_FACTOR; end i f ; o p e n i n g a f i l e and w r i t i n g t o o u t p u t . t x t i f f i r s t t i m e then Open t h e f i l e w r i t e . t x t f r o m t h e s p e c i f i e d l o c a t i o n f o r w r i t i n g f i l e _ o p e n ( f i l e _ p o i n t e r , " / edu / v e n d a 5 0 1 / f i r _ f i l t e r / 1 . t x t " ,APPEND_MODE) ; f i r s t t i m e := f a l s e ; end i f ; BIN_VALUE:=WRITEOUT; FOR I IN 0 TO IP_FACTOR1 LOOP BIN_VALUE_1:=BIN_VALUE( I ) ; K := 0 ; V:=WL + COEF_WL+3; FOR J IN V D O W N T O 5 LOOP IF K<(v +6) THEN K:=K+1; IF (BIN_VALUE_1( J ) = 1 ) then LINE_CONTENT(K) := 1 ; ELSIF BIN_VALUE_1( J ) = 0 then LINE_CONTENT(K) := 0 ; ELSE LINE_CONTENT(K) := 0 ; END IF ; END IF ; END LOOP ; i f r i s i n g _ e d g e ( c l k ) then r e p o r t "<! i =" & i n t e g e r i m a g e ( i ) & " >" s e v e r i t y n o t e ; w r i t e ( line_num , l i n e _ c o n t e n t ) ; w r i t e t h e l i n e . w r i t e t h e c o n t e n t s i n t o t h e f i l e . w r i t e l i n e ( f i l e _ p o i n t e r , line_num ) ; end i f ; end l o o p ; end p r o c e s s ; END BEHAV;
33
34
VHDL Implementation
4.4
Wordlength Issues in Interpolator
It is very important to consider the roundo error and sign of the integer bit while converting into a binary value. A sign bit is used to represent the sign of the number and a guard bit is used to reduce the roundo error. we have one sign bit and one guard bit in a 16-bit binary value. The wordlength of coecients for the lter and sublters are 14-bits. The coecient values for the lter H0 (z ) and sublters Gk (z ) are shown in the appendix. The fractional-delay multiplier has three decimal bits and ve fractional bits (2 downto -5) . There are some fractional value which cannot be exactly converted into a binary value. For example, d1 =0.3 for M =5, after conversion the binary value is 000.01001 which is not equal to 0.3. The exact fractional value of 000.01001 is 0.28125.
4.5
VHDL Implementation of the Decimator
To implement a decimator, the rst step is to implement the delay block dk m , the second step is to implement the sublters Gk (z ), and then we make use of the lter H0 (z ) which is designed for the interpolator. The delay block dk m , the sublters Gk (z ), and the lter H0 (z ) are instantiated in one design to form the decimator as shown in Fig. 4.7. The decimator is a (M -1)-input 1-output system, where M is the decimation factor. The block diagram of the decimator is shown in Fig. 4.9.
Figure 4.7. Block diagram for VHDL implementitation of the decimator.
4.5.1
VHDL Implementation of the Delay Block dk m
The delay block consists of M -1 delay multiplier chain blocks and six adders, where M is the decimation factor. The blocks with dotted lines in Fig. 4.9 are the delay multiplier chain blocks. H1 , H2 .........HM 1 are input samples and
4.5 VHDL Implementation of the Decimator
35
Gout(0), Gout(1)....Gout(5) are output ports to the delay block. Every delay multiplier chain block has ve outputs and they are G0 , G1 , G2 , G3 , G4 , G5 . The input Hm , where m=1,2,...M -1 is multiplied by the fractional-delay multiplier value resulting in Gk , where k =1,2...5. The G0 has the same value of Hm as shown in Fig 4.9. A 16-bit delay multiplier chain block is shown in Fig. 4.8. A 16-bit input sample is multiplied by 8-bit fractional-delay multiplier value resulting in 24-bits (18 downto -5). The fractional-delay multipliers have very small values, so when the input samples are multiplied by the dm value they become comparatively very small. Thus we can truncate the unnecessary bits, 8-bits are truncated from 24-bits resulting in 16-bits (15 downto 0).
Figure 4.8. A 16-bit delay multiplier chain block with truncations.
The rst output of every delay multiplier chain block are summed to form Gout(0) and every second output of the delay multiplier chain block are summed to form Gout(1) and so forth. The wordlength of the delay block increases with increase in the decimation factor because of increase in delay multiplier chain blocks. In order to overcome this problem the output of the delay block is xed for 32-bits (31 downto 0). Due to these truncations a 16-bit decimator works for 14-bits. The VHDL code for the delay block is given in the appendix.
4.5.2
VHDL Implementation of Sublters
In the interpolator, the sublters have single input fed to every sublter. But in the decimator, the sum of the rst output of every delay multiplier chain block is fed to the sublter G0 (z ), the sum of second output of every delay multiplier chain block is fed to G1 (z ) and so forth. The sublter block in decimator is transpose
36
VHDL Implementation
Figure 4.9. Block diagram of Decimator.
4.5 VHDL Implementation of the Decimator
37
of the sublter block in interpolator. Hence the output of the sublters block is the sum of sampled outputs of every sublter. The delay block dk m , sublters Gk (z ) and the lter H0 (z ) are instantiated in between lines 69-75 as shown in 4.4.
Listing 4.4. VDL code for the decimator
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 MAIN CODE LIBRARY IEEE ; USE IEEE . STD_LOGIC_1164 . ALL ; USE IEEE . NUMERIC_STD . ALL ; USE W O R K. PKG_SIGNED . ALL ; USER DEFINED PACKAGE u s e IEEE . STD_LOGIC_unsigned . ALL ; USE STD . TEXTIO . ALL ; LIBRARY W O R K; USE W O R K. ALL ; ENTITY ENTITY DECIMATOR_BLOCK I S GENERIC(WL: INTEGER: = 1 6 ; xin_wl : i n t e g e r : = 1 6 ; COEF_WL: INTEGER: = 1 6 ; F : INTEGER: = 6 ; DECIMATOR_FACTOR: INTEGER: = 8 ) ; PORT ( CLK, RST : IN STD_LOGIC ; DECIMATOR_IN : IN SIG_16 ( 0 TO DECIMATOR_FACTOR 1) ; DECIMATOR_OUT: OUT SIGNED (WL + COEF_WL 1 D O W N T O 0) ); END DECIMATOR_BLOCK; ARCHITECTURE ARCHITECTURE BEHAV OF DECIMATOR_BLOCK I S UBLOCK COMPONENT COMPONENT UBLOCK_DECIMATOR I S generic ( decimator_factor : integer ) ; PORT ( CLK, RST : IN STD_LOGIC ; DECIMATOR_IN : IN SIG_16 ( 1 TO DECIMATOR_FACTOR 1) ; GOUT : OUT SIG_16 ( 0 TO F 1) c h a n g e wl i s c h a n g e d ); END COMPONENT; FARROW STRUCTURE COMPONENT FARROW_STRUCTURE_16BIT I S PORT ( CLK, RST : IN STD_LOGIC ; GOUT_IN : IN SIG_16 ( 0 TO F 1) ; CHANGE WHEN WL I S CHANGED FOUT :OUT SIGNED (COEF_WL + WL 1 D O W N T O 0) ); END COMPONENT; H0 FILTER COMPONENT H0_FILTER I S PORT ( CLK, RST : IN STD_LOGIC ; XIN : IN SIGNED ( xin_WL1 D O W N T O 0 ) ; INPUT PORT YOUT: OUT SIGNED ( xin_WL+ COEF_WL 1 D O W N T O 0 ) OUTPUT PORT ); END COMPONENT; SIGNALS SIGNAL FOUT_SIGNAL : SIGNED (WL + COEF_WL 1 D O W N T O 0) ; SIGNAL GOUT_SIGNAL : SIG_16 ( 0 TO F 1) ; SIGNAL FIROUT_SIGNAL : SIGNED ( xin_WL+ COEF_WL 1 D O W N T O 0) ; SIGNAL INPUT_SIGNAL : SIG_16 ( 1 TO DECIMATOR_FACTOR 1) ; s i g n a l w r i t e _ o u t : s i g n e d ( wl+c o e f _ w l 1 downto 0 ) ; BEGIN PROCESS( c l k ) VARIABLE VAR : SIG_16 ( 1 TO DECIMATOR_FACTOR 1) ; BEGIN FOR I IN 1 TO DECIMATOR_FACTOR 1 LOOP VAR( I ) :=DECIMATOR_IN( I ) ; END LOOP ; INPUT_SIGNAL <= VAR; DECIMATOR_OUT <= FIROUT_SIGNAL+FOUT_SIGNAL ; w r i t e _ o u t <=FIROUT_SIGNAL+FOUT_SIGNAL ; END PROCESS ; ublock B1 :UBLOCK_DECIMATOR g e n e r i c map ( d e c i m a t o r _ f a c t o r ) PORT MAP (CLK, RST , INPUT_SIGNAL , GOUT_SIGNAL) ; farrow block FARROW: FARROW_STRUCTURE_16BIT PORT MAP(CLK, RST , GOUT_SIGNAL, FOUT_SIGNAL) ; h0 f i l t e r FILTER : H0_FILTER PORT MAP(CLK, RST , DECIMATOR_IN( 0 ) ,FIROUT_SIGNAL) ; file_writing : process ( clk ) f i l e file_pointer : text ;
38
79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 variable variable variable variable variable variable line_content : s t r i n g (1 to 32) ; w r i t e _ v a l u e : S i g n e d ( wl+c o e f _ w l D O W N T O 1) ; line_num : l i n e ; i , j ,K : i n t e g e r : = 0 ; char : c h a r a c t e r := 0 ; f i r s t t i m e : b o o l e a n := t r u e ;
VHDL Implementation
begin o p e n i n g a f i l e and w r i t i n g t o o u t p u t . t x t i f f i r s t t i m e then Open t h e f i l e w r i t e . t x t f r o m t h e s p e c i f i e d l o c a t i o n f o r w r i t i n g f i l e _ o p e n ( f i l e _ p o i n t e r , " / D e c i m a t o r / o u t p u t f i l e 1 0 . t x t " ,APPEND_MODE) ; f i r s t t i m e := f a l s e ; end i f ; write_VALUE:=WRITE_OUT; k := t o _ i n t e g e r ( w r i t e _ o u t ) ; i f r i s i n g _ e d g e ( c l k ) then r e p o r t "<! i =" & i n t e g e r i m a g e ( i ) & " >" s e v e r i t y n o t e ; w r i t e ( line_num , K) ; w r i t e t h e l i n e . w r i t e l i n e ( f i l e _ p o i n t e r , line_num ) ; end i f ; end p r o c e s s ; END BEHAV;
Chapter 5
Testbench and Simulation Results

5.1 Introduction
Once the design is completed, it has to be tested in order to check whether it performs as desired. The main advantage with VHDL is that a testbench can be designed to apply stimulus to the design that has to be tested and the testbench is portable between VHDL tools from dierent vendors. VHDL is not only a hardware description language but also a stimulus denition language. A VHDL testbench has an empty entity and an architecture with component that has to be tested, internal signals for input and output, system clock process and stimulus process.
5.2
Design Flow for Testing Interpolator
The design ow for testing the interpolator is shown in Fig. 5.1.
5.2.1
Generating a Sine Wave

Xin = sin(n. wT ); n = 0 to 2000 1; wT = /6.
A sine wave is generated in MATLAb with
The generated sine wave is rounded with the input wordlength, in this case the input signal wordlength is 16-bit. Xin_rounded = round(Xin 2(wl) ); The rounded sine wave is written to a text le using Fopen( Input.txt , w ) and Fprintf(d, %d/n , Xin_rounded). 39
40
Figure 5.1. Design ow for testing interpolator.
5.2.2
VHDL Testbench
A testbench is a empty design entity which serves as a host environment for another design entity. The entity under test is called "unit under test", which has to be instantiated in the architecture. The VHDL code for the interpolator testbench is shown below. The system clock and reset are generated in clock process and reset process. The input stimulus is generated using MATLAB, and the samples are written into a text le named "INPUT.TXT". A single sample is given for every clock period. Simulation results are shown in Fig. 5.2. From Fig. 5.2 it is very dicult to verify the output. Therefore, the output of the interpolator is written to a text le as shown in lines 126-155 in the interpolator VHDL code. The output of the interpolator (IOUT) is a 41-bit value, of which 36 are integer bits and 5 fractional bits.
5.2.3
Simulation results
A code is written in MATLAB to read the output text le generated by the interpolator and also to convert the 41-bit binary value to a rational value. The code is shown in 5.1.
Listing 5.1. Code to read the output le from the interpolator
1 2 3 4 5 6 7 8 clc ; close all ; clear all F r a c P a r t = 5 ; D e c P a r t = 36 M = 3 ; ; ; f o r m a t l o n g ; f o r m a t compact B i t s = F r a c P a r t+D e c P a r t+1 ; , r ) ;
f i d = f o p e n ( / edu / v e n d a 5 0 1 / t h e s i s / i n p u t s / i n p u t _ M 2 . t x t f c l o s e ( f i d ) ; f r e q z ( xin )
xin = f s c a n f ( fid ,
%d )
5.2 Design Flow for Testing Interpolator
41
Figure 5.2. output of interpolator in Modelsim.
42
Figure 5.3. Testbench for the Interpolator.
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
r h o = 0 . 0 5 ; [ n , f o , mo , w ] = f i r p m o r d ([1 r h o 1+r h o ] . p i /M, h p e r e f e c t = f i r p m ( n , f o , mo , w) ; x o u t p e r f e c t = c o n v ( u p s a m p l e ( x i n ,M) , h p e r e f e c t ) ; f i d = f o p e n ( / edu / v e n d a 5 0 1 / t h e s i s / o u t p u t _ f i l e s / M_2.txt tmp = f s c a n f ( f i d , %c ) ; f c l o s e ( f i d ) ; ,
[1
0] ,
[ 1 e 5 1 e 5 ] , 2 p i )
%F r a c P a r t = 3 ; D e c P a r t = 5 ; B i t s = F r a c P a r t+D e c P a r t+1 ; tmp = 110110119 f o r k = 0 : l e n g t h ( tmp ) / B i t s 1 i f k==0 xChar ( k + 1 , : ) = tmp ( 1 : B i t s ) ; else xChar ( k + 1 , : ) = tmp ( k B i t s + 1 : ( k +1) B i t s ) ; end f o r m = 1 : F r a c P a r t+D e c P a r t i f xChar ( k +1 ,m) == 0 tmp1 ( k +1 ,m) = 0 ; e l s e i f xChar ( k +1 ,m) == 1 tmp1 ( k +1 ,m) = 1 ; else tmp1 ( k +1 ,m) = 1 0 0 0 0 0 0 ; end end Value = 0 ; f o r m = 1 : F r a c P a r t+D e c P a r t if m >D e c P a r t V a l u e = V a l u e + 2^( m +D e c P a r t ) tmp1 ( k +1 ,m) ;% [m m +D e c P a r t x o u t ( k +1 ,m) ] elseif m ==1 V a l u e = V a l u e ( 2 ^ ( DecPart m) ) tmp1 ( k +1 ,m) ;% [m DecPart m x o u t ( k +1 ,m) ] else V a l u e = V a l u e + ( 2 ^ ( DecPart m) ) tmp1 ( k +1 ,m) ;% [m DecPart m x o u t ( k +1 ,m) ] end end x o u t ( k +1) = V a l u e ; %V a l u e = [ 2 ^ ( DecPart 1) 2 . ^ [ DecPart 2 : 0 ] ] . D e c B i t s + [ 2 . ^ [ 1 : 1 : F r a c P a r t ] ] . FracBits end xout = xout (20 10) ; figure stem ( x o u t ) ;
:end
Ft_Sze =14; figure () subplot (211) ; wT = l i n s p a c e ( 0 , p i , 1 e 3 ) ; p l o t (wT/ p i , db ( a b s ( f r e q z ( x i n , 1 ,wT) ) ) ) ; t i t l e ( Ma gn it ude r e s p o n s e o f i n p u t s i g n a l , F o n t S i z e , Ft_Sze , FontName , t i m e s ) ; y l a b e l ( |H( e ^ { j {\ omega}T} ) | [ dB ] , F o n t S i z e , Ft_Sze , FontName , t i m e s ) ; x l a b e l ( N o r m a l i z e d F r e q u e n c y ( x \ p i r a d / s a m p l e ) , F o n t S i z e , Ft_Sze , FontName , t i m e s ; subplot (212) ;
wT = l i n s p a c e ( 0 , p i , 1 e 3 ) ; p l o t (wT/ p i , db ( a b s ( f r e q z ( xout , 1 ,wT) ) ) , l i n e w i d t h , 2 ) ; t i t l e ( [ ( Ma gn it ud e r e s p o n s e o f i n t e r p o l a t o r ) M = , n u m 2 s t r (M) , ] , F o n t S i z e , Ft_Sze , FontName , t i m e s ) ; y l a b e l ( |H( e ^ { j {\ omega}T} ) | [ dB ] , F o n t S i z e , Ft_Sze , FontName , t i m e s ) ; x l a b e l ( N o r m a l i z e d F r e q u e n c y ( x \ p i r a d / s a m p l e ) , F o n t S i z e , Ft_Sze , FontName , t i m e s ) ; figure () subplot (211) ; wT = l i n s p a c e ( 0 , p i , 1 e 3 ) ; p l o t (wT/ p i , db ( a b s ( f r e q z ( x o u t . b l a c k m a n h a r r i s ( l e n g t h ( x o u t ) ) . , 1 , wT) ) ) , l i n e w i d t h , 2 ) ; t i t l e ( [ ( Ma gn it ud e r e s p o n s e o f i n t e r p o l a t o r ) M = , n u m 2 s t r (M) , ] , F o n t S i z e , Ft_Sze , FontName , t i m e s ) ; y l a b e l ( |H( e ^ { j {\ omega}T} ) | [ dB ] , F o n t S i z e , Ft_Sze , FontName , t i m e s ) ; x l a b e l ( N o r m a l i z e d F r e q u e n c y ( x \ p i r a d / s a m p l e ) , F o n t S i z e , Ft_Sze , FontName , t i m e s )
5.3 Testbench for the Decimator

;
43
71 72 73 74 75 76 77 78
subplot (212) ; wT = l i n s p a c e ( 0 , p i , 1 e 3 ) ; p l o t (wT/ p i , db ( a b s ( f r e q z ( x o u t . b l a c k m a n h a r r i s ( l e n g t h ( x o u t ) ) . , 1 , wT) ) ) , l i n e w i d t h , 2 ) ; h o l d on ; p l o t (wT/ p i , db ( a b s ( f r e q z ( x o u t p e r f e c t . b l a c k m a n h a r r i s ( l e n g t h ( x o u t p e r f e c t ) ) , 1 ,wT) ) ) , r ) ; t i t l e ( [ ( Ma gn it ud e r e s p o n s e o f i n t e r p o l a t o r w i t h p e r f e c t f i l t e r ) M = , n u m 2 s t r (M) , ] , F o n t S i z e , Ft_Sze , FontName , t i m e s ) ; y l a b e l ( |H( e ^ { j {\ omega}T} ) | [ dB ] , F o n t S i z e , Ft_Sze , FontName , t i m e s ) ; x l a b e l ( N o r m a l i z e d F r e q u e n c y ( x \ p i r a d / s a m p l e ) , F o n t S i z e , Ft_Sze , FontName , t i m e s ) ;
Figure 5.4 shows the input signal and the interpolated signal. Observe that for every input sample there are three output samples. The frequency response of the interpolator output is plotted in Fig. 5.5. The interpolator is simulated with dierent interpolation factors (M =3,6,10), and the frequency response is shown in Figs. [5.5-5.7]. The interpolator output is not quantized, so there is no noise in the plots.
x 10 1.5 1 0.5 0 0.5 1 1.5 185 190 195 200 205 210 215 220 225
4
input signal
x 10 2 1 0 1 2
(interpolator output) M=3
700
720
740
760
780
800
820
Figure 5.4. sinusoidal signal and the interpolated sinusoidal signal (M =3).
5.3
Testbench for the Decimator
The process for testing the decimator is the same as testing the interpolator. An upsampled sine wave is given as an input. The output of the decimator (decimator out) is a 32-bit binary value, it has 32 integer bits. The output text le generated by the decimator has integer values, implying that conversion of bits is not required. The frequency response of the decimator output is plotted in Figs. [5.9-5.11].
44
Magnitude response of inputsignal

120 100
|H(ejT)|[dB]
80 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Normalized Frequency (x rad/sample) (Magnitude response of interpolator output) M=3

220 200
|H(ejT)|[dB]
180 160 140 120 100 80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Normalized Frequency (x rad/sample)
Figure 5.5. Frequency response for the interpolator output.
(Magnitude response of interpolator output) M=6

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5.4 Synthesis and Timing Analysis

(Magnitude response of interpolator output) M=10
180 160
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|H(ejT)|[dB]
140 120 100 80 60 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
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0 0
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16-bit Interpolator 16-bit Decimator
LEs 17230 15099
LABs 1283 1099
F max (MHz) 13.95 59.99
System clock 1000 MHz 1000 MHz
Table 5.1. Table for resource utilization and performance.
5.4
Synthesis and Timing Analysis
The report below shows the total use of the logical elements and logical registers by Interpolator. This synthesis is done by selecting the Cyclone IV GX family and EP4CGX30CF23C6 device. Table 5.1 shows the number of logical elements and logical array blocks used for the interpolator and decimator. The interpolation factor is 10 and the decimation factor is 4. Due to the dierence in the factors there is a dierence in the LEs, LABs, and F max. The coecients of the interpolation/decimation lters are stored in the regiters. The output of interpolator/decimators are 32-bits, for the 16-bit interpolator/decimator. In this implementation the 16-bit interpolator output wordlength is 40 bits in which 8 bits are truncated. The performance of the interpolator can be increased by using advanced multiplication techniques.
5.4.1
Synthesis and Time Quest Analyzer Reports
46
Figure 5.8. Output of the decimator in Modelsim.
47

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Figure 5.9. Frequency response for the decimator output.

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48

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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
R e s o u r c e Usage Summary r e p o r t Tue Nov 6 1 4 : 2 2 : 4 0 2012 Q u a r t u s I I V e r s i o n 10 . 1 B u i l d
f o r DELAY_BLOCK_RW_16BIT 197 01/19/2011 Service Pack 1 SJ Full Version
; Table o f Contents ; 1 . Legal Notice 2 . F i t t e r R e s o u r c e Usage Summary
; Legal Notice ; C o p y r i g h t (C) 1991 2011 A l t e r a C o r p o r a t i o n Your u s e o f A l t e r a C o r p o r a t i o n s d e s i g n t o o l s , l o g i c f u n c t i o n s and o t h e r s o f t w a r e and t o o l s , and i t s AMPP p a r t n e r l o g i c f u n c t i o n s , and any o u t p u t f i l e s f r o m any o f t h e f o r e g o i n g ( i n c l u d i n g d e v i c e programming o r s i m u l a t i o n f i l e s ) , and any a s s o c i a t e d documentation or i n f o r m a t i o n are e x p r e s s l y s u b j e c t t o t h e t e r m s and c o n d i t i o n s o f t h e A l t e r a Program L i c e n s e S u b s c r i p t i o n Agreement , A l t e r a MegaCore F u n c t i o n L i c e n s e Agreement , o r o t h e r a p p l i c a b l e l i c e n s e a g r e e m e n t , i n c l u d i n g , without l i m i t a t i o n , t h a t your use i s f o r the s o l e purpose o f programming l o g i c d e v i c e s m a n u f a c t u r e d by A l t e r a and s o l d by Altera or i t s authorized d i s t r i b u t o r s . Please r e f e r to the a p p l i c a b l e agreement f o r f u r t h e r d e t a i l s .
+ + ; F i t t e r R e s o u r c e Usage Summary ; + + + ; Resource ; Usage ; + + + ; Total l o g i c elements ; 1 7 , 2 3 0 / 2 9 , 4 4 0 ( 59 % ) ; ; C o m b i n a t i o n a l w i t h no r e g i s t e r ; 16526 ; ; Register only ; 48 ; ; Combinational with a r e g i s t e r ; 656 ; ; ; ; ; L o g i c e l e m e n t u s a g e by number o f LUT i n p u t s ; ; ; 4 input functions ; 3395 ; ; 3 input functions ; 11228 ; ; <=2 i n p u t f u n c t i o n s ; 2559 ; ; Register only ; 48 ; ; ; ; ; L o g i c e l e m e n t s by mode ; ; ; n o r m a l mode ; 6228 ; ; a r i t h m e t i c mode ; 10954 ;

52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 ; ; ; ; Total r e g i s t e r s ; 704 / 3 0 , 8 7 6 ( 2 % ) ; ; Dedicated l o g i c r e g i s t e r s ; 704 / 2 9 , 4 4 0 ( 2 % ) ; ; I /O r e g i s t e r s ; 0 / 1 ,436 ( 0 % ) ; ; ; ; ; T o t a l LABs : p a r t i a l l y or c o m p l e t e l y used ; 1 , 2 8 3 / 1 , 8 4 0 ( 70 % ) ; ; User i n s e r t e d l o g i c e l e m e n t s ; 0 ; ; Virtual pins ; 0 ; ; I /O p i n s ; 2 1 0 / 3 0 7 ( 68 % ) ; ; Clock p i n s ; 1 / 8 ( 13 % ) ; ; Dedicated input pins ; 0 / 17 ( 0 % ) ; ; Global s i g n a l s ; 2 ; ; M9Ks ; 0 / 120 ( 0 % ) ; ; T o t a l b l o c k memory b i t s ; 0 / 1 ,105 ,920 ( 0 % ) ; ; T o t a l b l o c k memory i m p l e m e n t a t i o n b i t s ; 0 / 1 ,105 ,920 ( 0 % ) ; ; Embedded M u l t i p l i e r 9 b i t e l e m e n t s ; 20 / 1 6 0 ( 13 % ) ; ; PLLs ; 0 / 6 ( 0 % ) ; ; Global c l o c k s ; 2 / 30 ( 7 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; ; CRC b l o c k s ; 0 / 1 ( 0 % ) ; ; ASMI b l o c k s ; 0 / 1 ( 0 % ) ; ; GXB R e c e i v e r c h a n n e l PCSs ; 0 / 4 ( 0 % ) ; ; GXB R e c e i v e r c h a n n e l PMAs ; 0 / 4 ( 0 % ) ; ; GXB T r a n s m i t t e r c h a n n e l PCSs ; 0 / 4 ( 0 % ) ; ; GXB T r a n s m i t t e r c h a n n e l PMAs ; 0 / 4 ( 0 % ) ; ; I mpe da nc e c o n t r o l b l o c k s ; 0 / 3 ( 0 % ) ; ; A v e r a g e i n t e r c o n n e c t u s a g e ( t o t a l /H/V) ; 11% / 10% / 13% ; ; Peak i n t e r c o n n e c t u s a g e ( t o t a l /H/V) ; 49% / 46% / 54% ; ; Maximum f a n o u t node ; CLK~ i n p u t c l k c t r l ; ; Maximum f a n o u t ; 706 ; ; H i g h e s t non g l o b a l f a n o u t s i g n a l ; RST~ i n p u t ; ; H i g h e s t non g l o b a l f a n o u t ; 226 ; ; T o t a l f a n o u t ; 54972 ; ; A v e r a g e f a n o u t ; 2 .99 ; + + + R e g i s t e r c o u n t d o e s n o t i n c l u d e r e g i s t e r s i n s i d e RAM b l o c k s o r DSP b l o c k s .
49
From the time quest timing analysis report of the interpolator the F max=12.44 MHz for the slow 1200 mv 85c model and F max=13.95 MHz for the slow 1200 mv 0c model. For the decimator the F max=53.39 MHz for the slow 1200 mv 85c model and F max=59.99 MHz for the slow 1200 mv 0c model.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 R e s o u r c e Usage Summary r e p o r t Tue Nov 13 1 7 : 1 6 : 5 6 2 0 1 2 Q u a r t u s I I V e r s i o n 10 . 1 B u i l d for 197 Decimator_block 01/19/2011 Service Pack 1 SJ Full Version
; Table o f Contents ; 1 . Legal Notice 2 . F i t t e r R e s o u r c e Usage Summary
; Legal Notice ; C o p y r i g h t (C) 1991 2011 A l t e r a C o r p o r a t i o n Your u s e o f A l t e r a C o r p o r a t i o n s d e s i g n t o o l s , l o g i c f u n c t i o n s and o t h e r s o f t w a r e and t o o l s , and i t s AMPP p a r t n e r l o g i c f u n c t i o n s , and any o u t p u t f i l e s f r o m any o f t h e f o r e g o i n g ( i n c l u d i n g d e v i c e programming o r s i m u l a t i o n f i l e s ) , and any a s s o c i a t e d documentation or i n f o r m a t i o n are e x p r e s s l y s u b j e c t t o t h e t e r m s and c o n d i t i o n s o f t h e A l t e r a Program L i c e n s e S u b s c r i p t i o n Agreement , A l t e r a MegaCore F u n c t i o n L i c e n s e Agreement , o r o t h e r a p p l i c a b l e l i c e n s e a g r e e m e n t , i n c l u d i n g , without l i m i t a t i o n , t h a t your use i s f o r the s o l e purpose o f programming l o g i c d e v i c e s m a n u f a c t u r e d by A l t e r a and s o l d by Altera or i t s authorized d i s t r i b u t o r s . Please r e f e r to the a p p l i c a b l e agreement f o r f u r t h e r d e t a i l s .
+ + ; F i t t e r R e s o u r c e Usage Summary ; + + + ; Resource ; Usage ; + + + ; Total l o g i c elements ; 1 5 , 0 9 9 / 2 9 , 4 4 0 ( 51 % ) ; ; C o m b i n a t i o n a l w i t h no r e g i s t e r ; 12731 ; ; Register only ; 112 ; ; Combinational with a r e g i s t e r ; 2256 ; ; ; ; ; L o g i c e l e m e n t u s a g e by number o f LUT i n p u t s ; ;
50
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87
; 4 input functions ; 3901 ; ; 3 input functions ; 9249 ; ; <=2 i n p u t f u n c t i o n s ; 1837 ; ; Register only ; 112 ; ; ; ; ; L o g i c e l e m e n t s by mode ; ; ; n o r m a l mode ; 5811 ; ; a r i t h m e t i c mode ; 9176 ; ; ; ; ; Total r e g i s t e r s ; 2 ,368 / 30 ,191 ( 8 % ) ; ; Dedicated l o g i c r e g i s t e r s ; 2 ,368 / 29 ,440 ( 8 % ) ; ; I /O r e g i s t e r s ; 0 / 751 ( 0 % ) ; ; ; ; ; T o t a l LABs : p a r t i a l l y or c o m p l e t e l y used ; 1 , 0 9 9 / 1 , 8 4 0 ( 60 % ) ; ; User i n s e r t e d l o g i c e l e m e n t s ; 0 ; ; Virtual pins ; 0 ; ; I /O p i n s ; 98 / 1 6 7 ( 59 % ) ; ; Clock p i n s ; 4 / 6 ( 67 % ) ; ; Dedicated input pins ; 0 / 16 ( 0 % ) ; ; Global s i g n a l s ; 2 ; ; M9Ks ; 0 / 120 ( 0 % ) ; ; T o t a l b l o c k memory b i t s ; 0 / 1 ,105 ,920 ( 0 % ) ; ; T o t a l b l o c k memory i m p l e m e n t a t i o n b i t s ; 0 / 1 ,105 ,920 ( 0 % ) ; ; Embedded M u l t i p l i e r 9 b i t e l e m e n t s ; 0 / 160 ( 0 % ) ; ; PLLs ; 0 / 4 ( 0 % ) ; ; Global c l o c k s ; 2 / 20 ( 10 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; ; CRC b l o c k s ; 0 / 1 ( 0 % ) ; ; ASMI b l o c k s ; 0 / 1 ( 0 % ) ; ; GXB R e c e i v e r c h a n n e l PCSs ; 0 / 4 ( 0 % ) ; ; GXB R e c e i v e r c h a n n e l PMAs ; 0 / 4 ( 0 % ) ; ; GXB T r a n s m i t t e r c h a n n e l PCSs ; 0 / 4 ( 0 % ) ; ; GXB T r a n s m i t t e r c h a n n e l PMAs ; 0 / 4 ( 0 % ) ; ; I mpe da nc e c o n t r o l b l o c k s ; 0 / 3 ( 0 % ) ; ; A v e r a g e i n t e r c o n n e c t u s a g e ( t o t a l /H/V) ; 18% / 16% / 21% ; ; Peak i n t e r c o n n e c t u s a g e ( t o t a l /H/V) ; 31% / 26% / 39% ; ; Maximum f a n o u t node ; CLK~ i n p u t c l k c t r l ; ; Maximum f a n o u t ; 2368 ; ; H i g h e s t non g l o b a l f a n o u t s i g n a l ; RST~ i n p u t ; ; H i g h e s t non g l o b a l f a n o u t ; 320 ; ; T o t a l f a n o u t ; 54115 ; ; A v e r a g e f a n o u t ; 3 .07 ; + + + R e g i s t e r c o u n t d o e s n o t i n c l u d e r e g i s t e r s i n s i d e RAM b l o c k s o r DSP b l o c k s .
Chapter 6
Conclusion and Future Work

6.1 Conclusion
In this thesis work, the interpolators and decimators work eciently up to a conversion factor of 20. For larger factors new sublters have to be designed. This design gives the exibility to implement the dierent wordlength interpolators and decimators. This implementation proves that the design proposed in [8] works well for conversions by prime numbers and is exible for the conversion factors. The xed point package made the design more exible and easier. By instantiating the delay block, several sampling rate converters can be implemented simultaneously, with the same set of lters. The only additional cost to obtain another converter is to add another delay block. Hence, several sampling rate converters can be implemented simultaneously at low cost. The interpolator and decimator cannot be implemented on the FPGA board, because the FPGA board cannot read or write the text les given in the code. The program Teraterm or Hyperterminal can be used to transfer a text le with large amount of binary data.
6.2
Future Work
One can implement the design without using the xed point package and verify the performance and registers usage. More advanced techniques can be used for truncation of bits. To implement the design on the FPGA board one can use the teraterm program. By using this program the entire text le can be transferred to the FPGA board via a PC serial port. Another way to implement the design on the FPGA board is by using the SDRAM. The input sequence is saved in the SDRAM and the output of the interpolator or decimator has to be pointed to the remaining memory address in the SDRAM. The SDRAM on FPGA board is small, so we cannot give many input samples. 51
Appendix A
Appendix
A.1
A.1.1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
VHDL Code
VHDL Code for Sublter
FIR FILTER T h i s FIR f i l t e r i n s t a n c e s a r e u s e d i n t h e Farrow s t r u c t u r e MAIN CODE LIBRARY IEEE ; USE IEEE . STD_LOGIC_1164 . ALL ; USE IEEE . NUMERIC_STD . ALL ; u s e IEEE . STD_LOGIC_unsigned . ALL ; USE W O R K. PKG_SIGNED . ALL ; USER DEFINED PACKAGE LIBRARY W O R K; USE W O R K. ALL ; ENTITY ENTITY FIR_FILTER_16BIT I S GENERIC (ORDER : INTEGER: = 1 7 ;WL: INTEGER: = 1 6 ;COEF_WL: INTEGER: = 1 6 ) ; WL I S WORDLENGTH OF XIN (INPUT SIGNAL ) COEF_WL I S WORDLENGTH OF COEFFICIENTS OR TAPS PORT ( CLK, RST : IN STD_LOGIC ; XIN : IN SIGNED (WL 1 D O W N T O 0) ; THE PORT TYPE HAS TO BE CHANGED IF COEF_WL CHANGES COEF : IN SIG_16 ( 0 TO ORDER) ; YOUT: OUT SIGNED (COEF_WL + WL 1 D O W N T O 0) ); END FIR_FILTER_16BIT ; ARCHITECTURE ARCHITECTURE BEHAVIOURAL OF FIR_FILTER_16BIT I S TYPE SIG_ARR I S ARRAY (ORDER 1 D O W N T O 0 ) OF SIGNED (WL 1 D O W N T O 0) ; SIGNALS SIGNAL DFF : SIG_ARR ; BEGIN INTAL : PROCESS(CLK, RST) VARIABLE M_OUT,ADD_OUT: SIGNED (COEF_WL + WL 1 D O W N T O 0 ) : = (OTHERS= > 0 ) ; BEGIN IF (RST= 1 ) THEN FOR I IN ORDER 1 D O W N T O 0 LOOP f o r j i n WL 1 downto 0 l o o p DFF( I ) ( j ) <= 0 ; end l o o p ; END LOOP ; ELSIF ( r i s i n g _ e d g e ( c l k ) ) t h e n ADD_OUT:= COEF( 0 ) XIN ; FOR I IN 1 TO ORDER 1 LOOP M_OUT:=COEF( I ) DFF(ORDER 1 I ) ; ADD_OUT:=ADD_OUT + M_OUT; END LOOP ;
53
54
52 53 54 55 56 DFF <= XIN & DFF(ORDER 1 D O W N T O 1) ; end i f ; YOUT <= ADD_OUT; END PROCESS ; END BEHAVIOURAL ;
Appendix
A.1.2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
VHDL Code for Delay Block of Decimator
Delay Block o f Decimator MAIN CODE LIBRARY IEEE ; USE IEEE . STD_LOGIC_1164 . ALL ; USE IEEE . NUMERIC_STD . ALL ; USE IEEE . STD_LOGIC_unsigned . ALL ; l i b r a r y ieee_proposed ; u s e i e e e _ p r o p o s e d . f i x e d _ p k g . a l l ; f i x e d p o i n t p a c k a g e s USE W O R K. PKG_SIGNED . ALL ; USER DEFINED PACKAGE use std . t e x t i o . a l l ; LIBRARY W O R K; USE W O R K. ALL ; ENTITY ENTITY UBLOCK_DECIMATOR I S GENERIC(XIN_WL : INTEGER: = 1 6 ; F : INTEGER: = 6 ; DECIMATOR_FACTOR: INTEGER: = 6 ;Dm_WL: INTEGER: = 8 ) ; PORT ( CLK, RST : IN STD_LOGIC ; DECIMATOR_IN : IN SIG_16 ( 1 TO DECIMATOR_FACTOR 1) ; GOUT : OUT SIG_16 ( 0 TO F 1) c h a n g e wl i s ); END UBLOCK_DECIMATOR;
changed
ARCHITECTURE BEHAV OF UBLOCK_DECIMATOR I S ARRAYS TYPE Dm_VAR_ARRAY I S ARRAY( 0 TO DECIMATOR_FACTOR 1) OF SFIXED ( 1 D O W N T O Dm_WL+2) ; ( 0 TO 7) TYPE Dm_TEMP_ARRAY I S ARRAY( 1 TO DECIMATOR_FACTOR 1) OF SFIXED ( 2 D O W N T O Dm_WL+2) ; ( 1 TO 7) TYPE G_VAR_ARRAY I S ARRAY ( 0 TO F 1) OF SFIXED (XIN_WL 1 D O W N T O 0 ) ; ( 1 5 D O W N T O 0) TYPE G_TEMP_ARRAY I S ARRAY( 1 TO F 1) OF SFIXED (XIN_WL D O W N T O Dm_WL+1) ; BEGIN PROCESS(CLK, RST) VARIABLE Dm_VAR:Dm_VAR_ARRAY; ( 0 TO 7) VARIABLE Dm_TEMP:Dm_TEMP_ARRAY; ( 1 TO 7) VARIABLE G_VAR:G_VAR_ARRAY; ( 1 5 D O W N T O 0) VARIABLE G_TEMP:G_TEMP_ARRAY; WL=16(16 D O W N T O 7) VARIABLE GOUT_VAR: SIG_16 ( 0 TO F 1) ; c h a n g e when wl i c h a n g e d VARIABLE TEMP1 : SFIXED ( 1 D O W N T O Dm_WL+2) ; VARIABLE TEMP2 : SIGNED (XIN_WL 1 D O W N T O 0) ; v a r i a b l e o n c e : s f i x e d (XIN_WL 1 downto 0 ) ; v a r i a b l e d : s f i x e d ( XIN_wl1 downto 0 ) ; v a r i a b l e v a l u e : s f i x e d ( XIN_wl downto XIN_wl+1) ; BEGIN IF (RST= 1 ) THEN FOR I IN 0 TO F1 LOOP FOR J IN 0 TO 15 LOOP GOUT_VAR( I ) ( J ) : = 0 ; END LOOP ; END LOOP ; ELSif ( r i s i n g _ e d g e ( c l k ) ) then o n c e := t o _ s f i x e d ( 1 , o n c e ) ; d := t o _ s f i x e d ( d e c i m a t o r _ f a c t o r , d ) ; v a l u e := o n c e / d ; temp1 := r e s i z e ( v a l u e , temp1 ) ; Dm_VAR( 0 ) :=TO_SFIXED ( 0 . 5 ,Dm_VAR( 0 ) ) ; FOR I IN 1 TO DECIMATOR_FACTOR 1 LOOP Dm_TEMP( I ) :=TEMP1+ Dm_VAR( I 1) ; (1 D O W N T O 7) Dm_VAR( I ) :=RESIZE (Dm_TEMP( I ) ,Dm_VAR( I ) ) ; ( 0 D O W N T O 7) CONVERTING SIGNED (WL 1 D O W N T O 0 ) TO SFIXED ( 1 5 D O W N T O 0) G_VAR( 0 ) :=TO_SFIXED(DECIMATOR_IN( I ) ,G_VAR( 0 ) ) ; FOR J IN 1 TO F1 LOOP G_TEMP( J ) :=Dm_VAR( I ) G_VAR( J 1) ; ( 1 6 D O W N T O 7) G_VAR( J ) :=RESIZE (G_TEMP( J ) ,G_VAR( 0 ) ) ; ( 1 5 D O W N T O 0) END LOOP ; FOR J IN 0 TO F1 LOOP TEMP2:=TO_SIGNED(G_VAR( J ) ,XIN_WL) ; GOUT_VAR( J ) :=TEMP2+ GOUT_VAR( J ) ;
A.1 VHDL Code

77 78 79 80 81 82 END LOOP ; END LOOP ; GOUT <= GOUT_VAR; END IF ; END PROCESS ; END BEHAV;
55
A.1.3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
VHDL Code for Farrow Structure of Decimator
Farrow s t r u c t u r e f o r D e c i m a t o r MAIN CODE LIBRARY IEEE ; USE IEEE . STD_LOGIC_1164 . ALL ; USE IEEE . NUMERIC_STD . ALL ; USE W O R K. PKG_SIGNED . ALL ; USER DEFINED PACKAGE u s e IEEE . STD_LOGIC_unsigned . ALL ; USE STD . TEXTIO . ALL ; LIBRARY W O R K; USE W O R K. ALL ; ENTITY ENTITY ublk_FARROW_STRUCTURE I S GENERIC( F : INTEGER: = 6 ;WL: INTEGER: = 1 6 ;COEF_WL: INTEGER: = 1 6 ;ORDER: INTEGER: = 1 7 ; DECIMATOR_FACTOR: INTEGER: = 6 ; XIN_WL : INTEGER: = 1 6 ) ; PORT( CLK, RST : IN STD_LOGIC ; DECIMATOR_IN : IN SIG_16 ( 1 TO DECIMATOR_FACTOR 1) ; GOUT_IN :OUT SIG_16 ( 0 TO F 1) ; CHANGE WHEN WL I S CHANGED FOUT :OUT SIGNED (COEF_WL + WL 1 D O W N T O 0) ); END ublk_FARROW_STRUCTURE ; ARCHITECTURE ARCHITECTURE BEHAV OF ublk_FARROW_STRUCTURE I S COMPONENT DECLARATION H0_FILTER COMPONENT H0_FILTER I S PORT ( CLK, RST : IN STD_LOGIC ; XIN : IN SIGNED (XIN_WL 1 D O W N T O 0 ) ; INPUT PORT YOUT: OUT SIGNED ( (XIN_WL + COEF_WL 1) D O W N T O 0 ) OUTPUT PORT ); END COMPONENT; UBLOCK COMPONENT UBLOCK_DECIMATOR I S PORT ( CLK, RST : IN STD_LOGIC ; DECIMATOR_IN : IN SIG_16 ( 1 TO DECIMATOR_FACTOR 1) ; GOUT : OUT SIG_16 ( 0 TO F 1) c h a n g e wl i s c h a n g e d ); END COMPONENT; FIR_FILTER COMPONENT FIR_FILTER I S GENERIC (WL: INTEGER) ; PORT( CLK, RST : IN STD_LOGIC ; XIN : IN SIGNED (WL 1 D O W N T O 0) ; PORT TYPE HAS TO BE CHANGED IF COEF_WL CHANGES COEF : IN SIG_16 ( 0 TO ORDER) ; YOUT: OUT SIGNED (COEF_WL + WL 1 D O W N T O 0) ); END COMPONENT; ARRAY DECLARATION type c o e f f i c i e n t s i s array (0 to order ) o f i n t e g e r ; TYPE FIR_OUT_ARRAY I S ARRAY ( 0 TO F 1) OF SIGNED (COEF_WL + WL 1 D O W N T O 0) ; c o n s t a n t coef_1 : c o e f f i c i e n t s :=(33 , 69 ,164 , 323 ,582 , 989 ,1699 , 3230 ,10348 , 10348 , 3230 ,1699 , 989 ,582 , 323 ,164 , 69 ,33) ; c o n s t a n t coef_2 : c o e f f i c i e n t s :=( 254 ,462 , 711 ,1058 , 1510 ,1978 , 2706 ,4361 , 23066 ,23066 , 4361 ,2706 , 1978 ,1510 , 1058 ,711 , 462 ,254) ; c o n s t a n t coef_3 : c o e f f i c i e n t s :=( 101 ,110 , 636 ,1410 , 2635 ,4605 , 7911 ,14322 , 9288 , 9288 ,14322 , 7911 ,4605 , 2635 ,1410 , 636 ,110 , 101) ; c o n s t a n t coef_4 : c o e f f i c i e n t s :=(62 , 973 ,1276 , 1983 ,3213 , 4208 ,6917 , 13282 , 23043 , 23043 ,13282 , 6917 ,4208 , 3213 ,1983 , 1276 ,973 , 62) ; c o n s t a n t coef_5 : c o e f f i c i e n t s :=( 388 , 259 ,801 , 1357 ,2033 , 3390 ,5255 , 6306 , 3064 ,3064 , 6306 ,5255 , 3390 ,2033 , 1357 ,801 , 259 , 388) ;
56
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
Appendix
c o n s t a n t coef_6 : c o e f f i c i e n t s :=(44 , 139 , 43 ,99 , 157 ,347 , 1143 ,3033 , 4898 ,4898 , 3033 ,1143 , 347 ,157 , 99 ,43 ,139 , 44) ; SIGNALS DECLERATION SIGNAL GOUT_SIGNAL : SIG_16 ( 0 TO F 1) ; SIGNAL FIR_OUT : s i g _ 3 2 ( 1 t o f ) ; CHANGE COEF_WL CHANGES SIGNAL H0_OUT : SIGNED (XIN_WL + COEF_WL 1 D O W N T O 0) ; SIGNAL INPUT_SIGNAL : SIG_16 ( 1 TO DECIMATOR_FACTOR 1) ; SIGNAL COEF_SIGNAL_1 : SIG_16 ( 0 TO ORDER) ; CHANGE COEF_WL CHANGES SIGNAL COEF_SIGNAL_2 : SIG_16 ( 0 TO ORDER) ; CHANGE COEF_WL CHANGES SIGNAL COEF_SIGNAL_3 : SIG_16 ( 0 TO ORDER) ; CHANGE COEF_WL CHANGES SIGNAL COEF_SIGNAL_4 : SIG_16 ( 0 TO ORDER) ; CHANGE COEF_WL CHANGES SIGNAL COEF_SIGNAL_5 : SIG_16 ( 0 TO ORDER) ; CHANGE COEF_WL CHANGES SIGNAL COEF_SIGNAL_6 : SIG_16 ( 0 TO ORDER) ; CHANGE COEF_WL CHANGES SIGNAL TEST : ; BEGIN PROCESS( c l k ) VARIABLE COEF_VAR_1 : SIG_16 ( 0 TO ORDER) ; CHANGE COEF_WL VARIABLE COEF_VAR_2 : SIG_16 ( 0 TO ORDER) ; CHANGE COEF_WL VARIABLE COEF_VAR_3 : SIG_16 ( 0 TO ORDER) ; CHANGE COEF_WL VARIABLE COEF_VAR_4 : SIG_16 ( 0 TO ORDER) ; CHANGE COEF_WL VARIABLE COEF_VAR_5 : SIG_16 ( 0 TO ORDER) ; CHANGE COEF_WL VARIABLE COEF_VAR_6 : SIG_16 ( 0 TO ORDER) ; CHANGE COEF_WL VARIABLE INPUT_VAR : SIG_16 ( 1 TO DECIMATOR_FACTOR 1) ; begin if rst = 1 then f o r i in 0 to order loop COEF_VAR_1( I ) :=TO_SIGNED(COEF_1( I ) COEF_VAR_2( I ) :=TO_SIGNED(COEF_2( I ) COEF_VAR_3( I ) :=TO_SIGNED(COEF_3( I ) COEF_VAR_4( I ) :=TO_SIGNED(COEF_4( I ) COEF_VAR_5( I ) :=TO_SIGNED(COEF_5( I ) COEF_VAR_6( I ) :=TO_SIGNED(COEF_6( I ) END LOOP ; COEF_SIGNAL_1 <= COEF_VAR_1 ; COEF_SIGNAL_2 <= COEF_VAR_2 ; COEF_SIGNAL_3 <= COEF_VAR_3 ; COEF_SIGNAL_4 <= COEF_VAR_4 ; COEF_SIGNAL_5 <= COEF_VAR_5 ; COEF_SIGNAL_6 <= COEF_VAR_6 ; end i f ; CHANGES CHANGES CHANGES CHANGES CHANGES CHANGES
,COEF_WL) ,COEF_WL) ,COEF_WL) ,COEF_WL) ,COEF_WL) ,COEF_WL)
; ; ; ; ; ;
END PROCESS ; process2 : process ( clk ) VARIABLE INPUT_VAR : SIG_16 ( 1 TO DECIMATOR_FACTOR 1) ; begin i f r i s i n g _ e d g e ( c l k ) then f o r i i n 1 t o d e c i m a t o r _ f a c t o r 1 l o o p i n p u t _ v a r ( i ) := d e c i m a t o r _ i n ( i ) ; end l o o p ; i n p u t _ s i g n a l <=i n p u t _ v a r ; end i f ; end p r o c e s s ; COMPONENT DELECERATION H0_FILTER H0FILTER : H0_FILTER PORT MAP(CLK, RST , DECIMATOR_IN( 0 ) ,H0_OUT) ; DELAY BLOCK UBLOCK:UBLOCK_DECIMATOR PORT MAP(CLK, RST , i n p u t _ s i g n a l , GOUT_SIGNAL) ; GOUT_IN <= GOUT_SIGNAL ; FIRFILTER FIR1 : FIR_FILTER GENERIC MAP(WL) PORT MAP(CLK, RST , GOUT_SIGNAL( 5 ) , COEF_SIGNAL_6, FIR_OUT ( 1 ) ) ; FIR2 : FIR_FILTER GENERIC MAP(WL) PORT MAP(CLK, RST , GOUT_SIGNAL( 4 ) , COEF_SIGNAL_5, FIR_OUT ( 2 ) ) ; FIR3 : FIR_FILTER GENERIC MAP(WL) PORT MAP(CLK, RST , GOUT_SIGNAL( 3 ) , COEF_SIGNAL_4, FIR_OUT ( 3 ) ) ; FIR4 : FIR_FILTER GENERIC MAP(WL) PORT MAP(CLK, RST , GOUT_SIGNAL( 2 ) , COEF_SIGNAL_3, FIR_OUT ( 4 ) ) ; FIR5 : FIR_FILTER GENERIC MAP(WL) PORT MAP(CLK, RST , GOUT_SIGNAL( 1 ) , COEF_SIGNAL_2, FIR_OUT ( 5 ) ) ; FIR6 : FIR_FILTER GENERIC MAP(WL) PORT MAP(CLK, RST , GOUT_SIGNAL( 0 ) , COEF_SIGNAL_1, FIR_OUT ( 6 ) ) ; FOUT <= FIR_OUT ( 1 )+FIR_OUT ( 2 )+FIR_OUT ( 3 )+FIR_OUT ( 4 )+FIR_OUT ( 5 )+FIR_OUT ( 6 ) ; END BEHAV;
A.1.4
User Package
A.1 VHDL Code

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
57
PACKAGE : LIBRARY IEEE ; LIBRARY IEEE_PROPOSED ; USE IEEE . STD_LOGIC_1164 . ALL ; USE IEEE . NUMERIC_STD . ALL ; u s e IEEE . STD_LOGIC_unsigned . ALL ; use ieee_proposed . fixed_pkg . a l l ; PACKAGE PKG_SIGNED I S TYPE SIG_8 I S ARRAY (NATURAL RANGE <>) OF S i g n e d ( 7 D O W N T O 0) ; TYPE SIG_12 I S ARRAY (NATURAL RANGE <>) OF S i g n e d ( 1 1 D O W N T O 0) ; TYPE SIG_16 I S ARRAY (NATURAL RANGE <>) OF S i g n e d ( 1 5 D O W N T O 0) ; TYPE SIG_20 I S ARRAY (NATURAL RANGE <>) OF S i g n e d ( 1 9 D O W N T O 0) ; TYPE SIG_24 I S ARRAY (NATURAL RANGE <>) OF S i g n e d ( 2 3 D O W N T O 0) ; TYPE SIG_28 I S ARRAY (NATURAL RANGE <>) OF S i g n e d ( 2 7 D O W N T O 0) ; TYPE SIG_32 I S ARRAY (NATURAL RANGE <>) OF S i g n e d ( 3 1 D O W N T O 0) ; s i g n e d f i x e d p o i n t a r r a y s TYPE SIGS_32 I S ARRAY (NATURAL RANGE <>) OF SFIXED ( 3 1 D O W N T O 0) ; TYPE SIGS_28 I S ARRAY (NATURAL RANGE <>) OF SFIXED ( 2 7 D O W N T O 0) ; TYPE SIGS_24 I S ARRAY (NATURAL RANGE <>) OF SFIXED ( 2 3 D O W N T O 0) ; TYPE SIGS_20 I S ARRAY (NATURAL RANGE <>) OF SFIXED ( 1 9 D O W N T O 0) ; TYPE SIGS_16 I S ARRAY (NATURAL RANGE <>) OF SFIXED ( 1 5 D O W N T O 0) ; TYPE SIGS_12 I S ARRAY (NATURAL RANGE <>) OF SFIXED ( 1 1 D O W N T O 0) ; TYPE SIGS_8 I S ARRAY (NATURAL RANGE <>) OF SFIXED ( 7 D O W N T O 0) ; s p e c i a l a r r a y s TYPE SPE_ARR I S ARRAY (NATURAL RANGE <>) OF SFIXED ( 1 9 D O W N T O 5) ; x i n wl=8 b i t TYPE SPE_ARR_12 I S ARRAY (NATURAL RANGE <>) OF SFIXED ( 2 3 D O W N T O 5) ; x i n wl =12 bit TYPE SPE_ARR_24 I S ARRAY (NATURAL RANGE <>) OF SFIXED ( 2 7 D O W N T O 5) ; xin_wl =12 , c o e f _ w l =12 , t o t a l =33 b i t s TYPE SPE_ARR_32 I S ARRAY (NATURAL RANGE <>) OF SFIXED ( 3 5 D O W N T O 5) ; xin_wl =16 , c o e f _ w l =16 , t o t a l =41 b i t s TYPE SPE_ARR_40 I S ARRAY (NATURAL RANGE <>) OF SFIXED ( 4 3 D O W N T O 5) ; xin_wl =20 , c o e f _ w l =20 , t o t a l =49 b i t s END PKG_SIGNED ;
Bibliography
[1] D. Bishop, Fixed point package users guide, [2] J. Bajramovic, FPGA implementation of an interpolator for PWM applications, 2007. [3] P. P. Vaidyanathan, Multirate Systems and Filter banks. Prentice Hall, 1993. [4] S. Mitra, Digital Signal Processing: A Computer-Based Approach. McGrawHill, 2010. [5] L. Wanhammar and H. Johansson, Digital Filters using MATLAB. [6] R. A. Losada, Digital lter with MATLAB. May 2008. [7] A. Eghbali, Contributions to Recongurable Filter Banks and Transmultiplexers. PhD thesis, Linkping UniversityLinkping University, Electronics System, The Institute of Technology, 2010. [8] H. Johansson and O. Gustafsson, Linear-phase FIR interpolation, decimation, and mth-band lters utilizing the Farrow structure, IEEE Trans. Circuits and Syst. I, vol. 52, pp. 21972207, oct. 2005. [9] A. S. SINGH, NAVJOT. SAPPAL, Design and implementation of optimum interpolation lter using Farrow structures, no. 66135090, 2011. [10] M. Abbas, On the Implementation of Integer and Non-Integer Sampling Rate Conversion. PhD thesis, Linkping UniversityLinkping University, Electronics System, The Institute of Technology, 2012. [11] A. Eghbali, H. Johansson, and P. Lwenborg, A Farrow-structure-based multi-mode transmultiplexer, in IEEE Int. Symp. Circuits and Syst, ISCAS 2008., pp. 31143117, may 2008. [12] H. Johansson, Farrow-structure-based recongurable bandpass linear-phase FIR lters for integer sampling rate conversion, IEEE Trans. Circuits and Syst. II, vol. 58, pp. 4650, jan. 2011. [13] H. Johansson and P. Lwenborg, On the design of adjustable fractional delay FIR lters, IEEE Trans. Circuits and Syst. II, vol. 50, pp. 164169, apr 2003. [14] V. Pedroni, Circuit Design with VHDL. Mit Press, 2004. 58

FPGA Implementation of Flexible Interpolators and Decimators

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Institutionen fr systemteknik

Department of Electrical Engineering

FPGA Implementation of Flexible Interpolators and Decimators

Department of Electrical Engineering Linkpings universitet SE-581 83 Linkping, Sweden

Linkpings tekniska hgskola Linkpings universitet 581 83 Linkping

FPGA Implementation of Flexible Interpolators and Decimators

Examensarbete utfrt i Elektroniksystem vid Tekniska hgskolan i Linkping av

Linkping, 21 February, 2013

LiTH-ISY-EX--13/4654--SE Serietitel och serienummer ISSN Title of series, numbering

URL fr elektronisk version

Svensk titel FPGA Implementation of Flexible Interpolators and Decimators

Frfattare Venkatavikram Dabbugottu Author

Purpose of the Thesis

Interpolation and Decimation

Interpolation and Decimation

The Fourier transform of x1 (m) can be expressed as [5]

In the z -domain, we have [5] X1 (z ) = X (z L ). (2.3)

Figure 2.1. Interpolation by a factor of L.

X1 (ej (T1 2k/M ) ).

2.4 Sampling Rate Conversion by a Rational Factor

Figure 2.2. Original sequence and the upsampled sequence by a factor of 3.

Sampling Rate Conversion by a Rational Factor

Interpolation and Decimation

Figure 2.3. Spectra of the original, intermediate, and output sequences.

Figure 2.4. Decimation by a factor of M .

2.4 Sampling Rate Conversion by a Rational Factor

Interpolation and Decimation

Polyphase Interpolation and Decimation Structures

n hi ( M ) for n = 0, L, 2L.. 0 otherwise. (M )

Third, summing all the shifted versions of hi

The polyphase representation of a signal h(n) in the z -domain is [5]

2.5 Polyphase Interpolation and Decimation Structures

Interpolation and Decimation

Converters with Time-Varying Coecients

2.6 Converters with Time-Varying Coecients

Figure 2.9. Noble identities.

Figure 2.10. Polyphase interpolator.

Figure 2.11. Polyphase decimator.

Interpolation and Decimation

Flexible Interpolators and Decimators

Flexible Interpolators and Decimators

Figure 3.1. Farrow structure.

Farrow Structure for SRC

Linear-Phase FIR Interpolation and Decimation Utilizing the Farrow Structure

Figure 3.2. Modied Farrow structure

Flexible Interpolators and Decimators

where dm possess anti-symmetric according to dm = dM m .

Interpolator and Decimator structures

(3.8) (3.9) (3.10)

Figure 3.4. Flexible intepolator structure.

Figure 3.5. Flexible decimator structure.

Table 3.1. Impulse response of The lter H0 (z ) .

The specication of the overall lowpass lter is T [s T, ] (3.12)

3.5 Filter Design

Table 3.2. Impulse response of sublters G0 (z ), G1 (z ), G2 (z ) .

Table 3.3. Impulse response of sublters G3 (z ), G4 (z ), G5 (z ) .

Fixed Point Package

24 Simulation tool H0 (z )alinear phaseF IRf ilter Gk (z ) sublters L=5

Table 4.1. Table of specication.

Operation A+B A-B A*B A rem B

VHDL Implementation of the Interpolator

VHDL Implementation of the Filter H0 (z )

The transfer function of an FIR lter is [4] H (z ) =

In the time domain, we have