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Automotive DCDC Bidirectional Converter Made With Many Interleaved Buck Stages
Oscar Garca, Member, IEEE, Pablo Zumel, Angel de Castro, and Jos A. Cobos, Member, IEEE
AbstractInterleaving technique is used in some applications due to its advantages regarding lter reduction, dynamic response, and power management. In dual battery system vehicles, the bidirectional dcdc converter takes advantage of this technique using three-to-ve paralleled buck stages. In this paper, we propose the use of a much higher number of phases in parallel together with digital control. It will be shown that this approach opens new possibilities since changes in the technology are possible. Thus, two 1000-W prototypes have been designed using surface mount technology devices (SO-8 transistors). An additional important feature is that due to the accuracy of the digital device [eld-programmable gate array (FPGA)], current loops have been eliminated, greatly simplifying the implementation of the control stage. Index TermsDigital control, eld-programmable gate array (FPGA), surface mount technology (SMT).

I. INTRODUCTION

UTOMOTIVE electronics are one eld of power electronics that has been growing rapidly in recent years. Some good examples of this are the electronics involved in the dual battery system vehicles that use 14-V and 42-V batteries. One of the specic converters for these vehicles is the bidirectional module placed in between those batteries that is in charge of the power ow. Typically, the power of this converter ranges from 500 to 1000 W. Due to the relative high current of this application, some approaches use the interleaving technique [1]. The main advantages of using this technique in this application are the lters reduction and efciency. State of the art engineering for this application proposes the use of three to ve paralleled buck stages (phases) to build the converter [2][5]. A comparison between this multiphase converter with a single buck converter is carried out in [2], where the advantage of this technique for this application can be seen. Reference [3] proposes a CAD tool to calculate the number of phases to optimize cost, size, and weight. A similar analysis, but more oriented to calculate power losses, can be found in [4]. A magnetic component to couple all the phases is introduced in [5], obtaining a size reduction compared with inductors for the same power losses. A quite different solution is presented in [6], where the authors propose a multilevel converter to

decrease the voltage stress in the transistors and to eliminate the inductor. Finally, a procedure to design this type of power converter based on models implemented in Matlab is shown in [7]. References [2] and [3] are deeply analyzed and compared in Table II. Using interleaving, the power stage of a converter is divided into several and smaller power stages. Therefore, the size of each component is reduced. With a very high number of interleaved phases, the current stress is greatly reduced and using a different technology becomes a possibility. This change of technology may bring several advantages: power converter is made of surface mount technology (SMT) components; automatic assembly; absence of heatsinks (usually heatsinks require manual assembly); magnetic components can be planar or SMT. Repetitivity is greatly increased; very small input and output lters. However, there are some challenges to face a many-phases converter. General purpose integrated circuits (ICs) cannot be used because there are many phases. Specic digital control is required. Introducing a current loop per phase will not be cost-effective. Passive current equalization should be considered. In this paper, two multiphase dc/dc converters made of many interleaved phases (16 and 36) for automotive application are proposed. Apart from the aforementioned advantages, the measures in the prototypes show a very good efciency (94%95%) at full load (1000 W). II. POWER STAGE DESIGN The converter will be implemented using the synchronous buck conguration because it is suitable for this specication and it is used for most of the authors [2][5]. It has bidirectional capability and efciency is quite good. No isolation is needed between both batteries and therefore, topologies with transformers are unnecessary. Fig. 1 shows a multiphase synchronous buck dc/dc converter. The design has been guided by the compromise of using SMT components. The number of phases has been selected to reduce the dc current enough to use small transistors. Thus, two designs have been considered as shown in Table I. In the rst one, with 16 phases, each metal-oxide-semiconductor eld-effect transistor (MOSFET) needs a SO-8 case while the second, with 36 phases, has its two MOSFETs of each phase in the same SO-8 case.

Manuscript received March 9, 2005; revised October 26, 2005. This work was presented in part at PESC04 and APEC05. Recommended by Associate Editor J. Shen. O. Garca, A. de Castro, and J. A. Cobos are with the Divisin de Ingeniera Electrnica, Universidad Politcnica de Madrid, Madrid 28006, Madrid. (e-mail: o.garcia@upm.es). P. Zumel is with the Departamento de Tecnologa Electrnica, Universidad Carlos III de Madrid, Madrid, Spain. Digital Object Identier 10.1109/TPEL.2006.872379

0885-8993/$20.00 2006 IEEE

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Fig. 2. PCB windings of the RM7 inductor and phase layout.

Fig. 1. Multiphase synchronous buck dc/dc converter.

TABLE I BRIEF OVERVIEW OF THE TWO PROPOSED DESIGNS

The key design parameter is the number of phases and the phase current ripple. It is not easy to determine it since many calculations should be done and many technologies should be taken into account. A guideline can be found in [8]. Note that the effect of increasing the number of phases in each particular component (transistors, inductors, capacitors) is different. Here is a brief summary. Transistors: there are three types of power losses in the MOSFETs. Both conduction and capacitive losses are relatively easy to calculate being proportional to the on-resistance and capacitances, respectively. However, switching losses are much more complex because they depend on a higher number of parameters, some of them out of the switch itself (leakage inductance, driver output current, ). In a rst approximation, these losses are calculated using the constant switching time of the device given in the datasheet. However, in the real world, these switching times (rise and fall times) are load dependent. is conFor a given MOSFET technology (product stant) there is no advantage in increasing the number of phases if the total area of silicon is the same: a higher number of phases will use smaller transistors. Therefore, each transistor has a higher on-resistance but handles less current keeping the conduction losses constant. The same

can be said about the capacitive losses because each transistor has a smaller capacitance but the addition of all of them is constant. Switching losses are also constant if rise and fall times are considered independent of the number of phases. In the case of using discrete semiconductors, the calculations should be done for each particular design since the technology is different for each manufacturer. At least, the advantage of using a high number of phases is that due to ripple cancellation the switching frequency can be reduced and, therefore, the switching and capacitive losses are reduced. Inductors: the optimum number of phases from the point of view of the magnetic component is hard to determine. From the point of view of inductors, high current ripple is preferred for the same averaged current, since it implies lower losses in the inductor. However, several phases are required in order to obtain a high cancellation of phase current ripple and then a small output capacitance. Each time a phase is added, the average current of it is divided; if inductance is increased in the same way, the total energy in the inductors is kept constant. Thus, size is not drastically affected. However, a size reduction can be obtained if inductance is kept constant when a new phase is added and then the phase current ripple ratio is increased. But nally, for a high number of phases, inductance should be increased to avoid a very high current ripple with a very small dc current. This will produce a poor efciency. Anyway, a high number of phases allows the use of small magnetic components, and packaging may be improved quite a bit, especially the height. In this case, the use of 16 phases allows an easy implementation of the inductor using a RM7 core. Six turns are required and windings are embedded in the printed circuit board (PCB) as shown in Fig. 2. Capacitors: a high degree of interleaving produces a ripple cancellation that reduces the lter needs. As a result, the designer can take advantage of ceramic capacitors. Both capacitors are reduced although, in practice, the minimum input capacitance is limited by the pulsating input current of each phase. For a high number of phases, nonideal effects must be taken into account. Inductor tolerances produce different values in the current ripple per phase, and then the output capacitance for the same output voltage ripple is higher than in the ideal case.

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TABLE II COMPARISON OF SEVERAL DC/DC CONVERTERS FOR THE SAME APPLICATION BUT WITH DIFFERENT NUMBER OF INTERLEAVED PHASES

Another advantage of interleaving is ripple cancellation [9]. With a very high number of phases, the current ripple at the output is nearly negligible at every input voltage. Therefore, the output capacitor is really small. Table II shows a comparison among several designs for the automotive 42/14-V bidirectional converter. All of them have been designed for 1000 W. Single phase design is theoretical; state of the art columns are taken from [2] and [3] (data between brackets are estimations); nally, the last two columns with the proposed designs have been included. Other examples [4], [5] designed for smaller amounts of power (400500 W) also use a small number of phases such as 3 or 4. Regarding this table, some comments can be made. The higher the number of phases, the smaller the MOSFET size. A high number of phases allows the use of SMT transistors. Moreover, with a proper design heatsinks can be avoided.

The same can be said about the inductors, obtaining a small size for Design II. Even with 36 phases, the total inductor volume is smaller compared with the others designs. Output capacitance: with 16 interleaved phases, there is a very high ripple cancellation for every duty cycle. However, the tolerances in the inductance forces one to use a relatively large output capacitor (the authors do not know if previous works have considered this phenomenon). This effect is much smaller in the 36-phase converter where a small lter is obtained. Two differential features are common to these two designs: rst, they do not use commercial ICs to control, but specic circuits using digital devices; second, no heatsinks are used in them. This is one of the most important differences because it simplies the constructive process and reduces the cost. Efciency in the proposed designs is very high.

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Fig. 3. Simplied control scheme implemented in a FPGA to control the converter. Fig. 4. Addition and comparison of (a) hardware structure and (b) its workings.

The main conclusion obtained from the previous table is that in using many phases, a change of technology is possible obtaining very good results from the point of view of efciency and size. From the point of view of cost, the present approach has one differential advantage compared with other solutions of the state of the art: all the components are SMD including inductors and, therefore, the converter can be mounted automatically. This drastically reduces the cost when compared with manual assembly. Moreover, the absence of heatsinks signicantly simplies the mechanical issues. On the other hand, these designs require more components. III. CONTROL STAGE DESIGN The control circuit is in charge of generating the driving signals for the 16 phases, that is, 32 transistors in Design I and 36 (72 transistors) in Design II. Since the converter is bidirectional, input and output voltages should be measured to generate pulses. Interleaved converters proposed in the state of the art do require a current loop in each phase to control the dc current per phase. Using a digital control, the accuracy of these pulses is so high that the present phases current are not measured. Therefore, the control circuit is quite simple. Although there are other factors that affect current unbalance, this is the main factor responsable. The control stage is digital and has been implemented in a eld-programmable gate array (FPGA). A general scheme is shown in Fig. 3. The digital circuit is composed of ve parts. ADC interface and lter: control of analog to digital converters and lter to remove noise from samples. Regulator: it calculates duty cycle. Its control algorithm has been designed using the root-locus technique and calculated directly in the digital domain for obtaining better results. MCD generator: generates the pulse for the free-wheeling transistor. Thus, the converter changes automatically to DCM when possible (usually at low load). Phase shifter: this block generates shifted signals form the duty cycle [10]. Protections: some basic protections are included. The advantage is that they are included without additional cost. The control circuit has been implemented in a Xilinx XCV200E FPGA. The nal control circuit is quite small using

10 085 equivalent gates (3.4% of the device), so a smaller and cheaper FPGA could also be used. Thanks to the FPGA concurrency (all its logic is executed in parallel) a high number of driving signals can be generated without any drawback in the performance of the rest of the controller. Furthermore, its high processing speed allows a very accurate signal generation, which is the key for passive current sharing in continuous conduction mode (CCM). This controller can work at frequencies above 50 MHz, allowing a high duty cycle resolution (over 400 different duty cycles are possible). In order to implement the phase-shifter block, two different digital hardware structures are proposed. Both are considered for implementation using custom hardware. A. Addition and Comparison Phase-Shifter The rst possibility is to add some constants to the main counter, with the results translated to the range of the counter in case of overow, and then compare each sum to the duty cycle [see Fig. 4(a)]. These sums are in fact equivalent to phaseshifted counters [see Fig. 4(b)], being the delay between them proportional to the constant that has been added. In order to obtain homogeneous distribution along the switching cycle, the constants to be added are

(1) being the phase number, the number of phases, and the resolution of the duty cycle, which is equal to the range of the counter. Other equivalent hardware structure would be substituting the additions by counters, assuring that these counters were delayed according to expression (1). B. Shift-Register Phase-Shifter The second possibility is to introduce the driving signal of the rst phase into a shift-register [see Fig. 5(a)]. In this way, a delay is obtained which is equal to the length of the shiftregister multiplied by the clock cycle. The total length of the , while each driving signal shift-register is at most equal to is extracted from the position obtained by expression (1). These

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Fig. 5. (a) Shift-register hardware structure and (b) its workings.

Fig. 6. Equivalent dc circuit of the multiphase buck converter working in CCM.

delays are equivalent to the desired phase-shifting operation [see Fig. 5(b)]. C. Phase-Shifters Comparison Three comparison criteria can be used to distinguish between these two solutions. Duty cycle resolution. The shift-register method leads to shorter critical paths. Therefore, higher clock frequency can be achieved and, as a consequence, duty cycle resolution can be increased. Closed-loop dynamics. Using addition and comparison phase-shifters, duty cycle changes start affecting all driving signals immediately, while for shift-register phase-shifters these changes only affect the rst phase immediately. The rest of the phases are affected only after a time equal to their delay. Therefore, somewhat higher closed-loop dynamics is achieved with the addition and comparison method. Area. The addition and comparison phase-shifter is very sensitive to the number of phases, as each phase needs its own adder and comparator. The shift-register phase-shifter is not sensitive to the number of phases, as including more phases needs is just extracting more driving signals from the already available shift-register. However, it is sensitive to the duty cycle resolution, as the length of the shift-register is proportional to it. IV. CURRENT SHARING One of the concerns of the interleaved converters is current sharing. Commercial integrated circuits solve this problem by including an additional current loop [11], [12]. As a consequence, the cost of the IC is quite high. Also, the additional circuitry grows, increasing size and decreasing reliability. Therefore, although the aforementioned IC controllers have been designed with the capability of paralleling some of them, in practice, a high number of phases is not feasible. The purpose of this paper is to use a high number of phases but without any current loop. The dc current depends strongly on the conduction mode of the converter. A. Continuous Conduction Mode (CCM) Fig. 6 shows the equivalent dc circuit of a multiphase buck converter when it operates in CCM. Each phase is characterized ; the voltage applied to this reby a dc parasitic resistance

multiplied by the actual duty sistance is the input voltage cycle of this phase . , the output voltage of the conIn case of passive load can be calculated from the aforementioned paramverter , , and ) with the following expression: eters (

(2)

Note that if the load is a battery, the output voltage is just is known, the the battery voltage and (2) is not used. Once current through each phase is easily calculated

(3) The worst-case for a single phase takes place when this phase has the maximum duty cycle and the minimum resistance while the rest have minimum duty cycle and maximum resistance. In such a case, the phase current is maximum while the other phases will handle a current below the average value . In order to determine which of both factors (differences in duty cycle or in resistance) is the most important, we can analyze each one independently. This analysis can be found in detail in [13], but the main results are the following ones. The differences caused by resistance unbalance when only one resistance is different from the others can be calculated as shown in

(4) being the common resistance for the rest of the phases and the difference in the unbalanced resistance. On the other hand, the differences caused by duty cycle unbalance when only one duty cycle is different from the others can be calculated as shown in

(5) being the common duty cycle for the rest of the phases, the difference in the unbalanced duty cycle, and the power efciency due to losses on the resistance exclusively.

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TABLE III DC CURRENT VALUES IN DCM AND CCM FOR 1% AND 5% DUTY CYCLE INEQUALITIES

Fig. 7. Inductor current in DCM.

In order to compare both factors, a numerical example is analyzed. For a 16-phases converter with 98% efciency due to resistance (2% losses in the resistance), a 10% difference in one of the resistances causes less than a 10% difference in the current of that phase. However, for the same converter a minimum 1% difference in one of the duty cycles causes a 47% unbalance in the current of the unbalanced phase. As it can be seen, duty cycle is responsible for the main current unbalance unless the resistance causes very high losses (over 10%), which is avoided by design. Regarding the inductor value, its differences cause only unbalanced current ripples (peak to peak), but the dc current per phase is unaffected in CCM. However, it affects dc current in discontinuous conduction mode (DCM), as explained in the next point. Therefore, it can be stated that duty cycle is the main cause of current unbalance in CCM. However, the use of digital control drastically reduces unbalances caused by duty cycle, because the driving signal is generated with great accuracy (differences below 1 ns). Differences in duty cycle of the phases will be produced by drivers and MOSFETs variations (so they should be chosen taking this into account). Thus, in many cases, it is possible to eliminate current sensing circuits, current loops, and all the associated circuitry. In conclusion, the control stage is composed of a single voltage loop and driving signals generator, making it feasible to build a multiphase converter with many phases (more than the classical three or four) at a reasonable cost. In the experimental results section, the converter has been designed without current loops trusting in the digital control for current equalization. It will be seen that it is not necessary to include this current loop. B. Discontinuous Conduction Mode (DCM) DCM is a very interesting option for multiphase converters because the equalization of the currents is much better. Inductor current of a single phase in a switching cycle is shown in Fig. 7. The average value of the inductor current (output current of a phase) can be calculated from Fig. 7 and is dened in

and even a 5% difference in duty cycle causes just a 10% current unbalance. Regarding the inductor value, a 10% difference causes a 9% current unbalance, and even a 20% difference in inductance causes just a 17% current unbalance. C. Comparison Between CCM and DCM Table III shows a numerical comparison between these two conduction modes in terms of current unbalance. The calculations have been carried out for the following specications and data. Sixteen-phases synchronous buck converter (to test DCM, free-wheeling MOSFETs is turned-off when current reaches 0). One phase has 1% (or 5%) higher duty cycle than the other 15 phases. . Input voltage: 42 . Output voltage: 14 Output power: 1000 W. Inductance: 5.4 H. Parasitic resistance: 35 m MOSFET inductor . Switching frequency: 120 kHz. With a relative small duty cycle deviation such as 1%, CCM shows an unacceptable current unbalance (current is 1.84 the nominal) while DCM current unbalance is kept below 2%. Therefore, if CCM mode is preferred the duty cycle should be very precise or the designer is forced to include one current loop per phase. Table II shows the benets of operating in DCM even if the duty cycle is not very accurate. With a 5% deviation, the current is only 10% over the average. Therefore, a conservative criterion is to select DCM as an operation mode. Thus, current loops can be removed obtaining a very good current balance. However, due to the accuracy of the digital control, the dc currents are very similar in CCM as will be shown in the next section. This operation mode is interesting because root-mean-square (RMS) currents are smaller at full load, and therefore the converter efciency is higher. V. EXPERIMENTAL RESULTS

(6) In DCM, the differences in phase current are caused by duty cycle and inductance and not parasitic resistance (in a rst approximation). However, since each phase current starts from zero every switching cycle, the average values are quite similar even having relatively different duty cycles. For example, a 1% difference in duty cycle causes a 2% current unbalance,

The converters have been designed according to the following specications. High voltage side: 42 V. Low voltage side: 14 V. Output power: 1000 W. No current loops.

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Fig. 10. Prototype made with 16 phases: (a) single phase power stage and (b) whole power stage.

Fig. 8. Current ripple per phase in Design I.

The efciency of the converter is shown in Fig. 9. Maximum value is 95% at full load. No heatsink is used at room temperature. Finally, Fig. 10 shows two pictures of the power stage of the converter. The main characteristic is that it has been possible to use low prole components obtaining a 10-mm height and 1000-W converter (tallest component is an RM7 core embebbed in the PCB). B. Design II The main characteristics of this prototype are as follows. Number of phases: 36. Power per phase: 27.7 W. Phase switching frequency: 100 kHz. Inductor per phase: 47 H (WE PD-47). MOSFETs: IRF7341 (two transistors in a SO-8 package). Driver: IR2181S (two drivers in a SO-8 package). Compared with the previously presented prototype, the main difference is that this design runs in CCM but with positive current (current ripple is small compared to the dc current value). In these conditions, the dc current through each phase is only dened by the parasitic resistances and duty cycle inequalities [see (3)]. Measured current waveforms in steady-state conditions are shown in Fig. 11(a) and (c). Although no current loops have been used, dc currents through each phase are quite similar even during transients as shown in Fig. 12 (only four phase currents are shown). All of them are in the range 10% at full load. Fig. 11(b) and (d) shows the dc phase current values. Design II has a maximum efciency of 94% with 50 A and 93.5% at full load as shown in Fig. 13. A converter with 36 phases is shown in Fig. 14. The converter is composed of two stacked PCBs with a pair of connectors between. The rst PCB contains the power transistors (on the top side) and the drivers (bottom side); the second PCB includes the inductors and the output capacitors. VI. CONCLUSION The interleaving technique has several advantages such as lters reduction, better dynamic response, and better thermal management. Besides the classical approach, using a high number of phases brings other advantages. In particular, power components can be SMD and/or inductors can be integrated in the PCB. Thus, the converter is repetitivity increased, the assembly can be automatic, and even heatsinks can be removed. In this paper, two multiphase 1000-W dcdc converters made of many interleaved buck phases (16 and 36) are proposed.

Fig. 9. Measured efciency of Design I as a function of the output current.

Digital control, implemented in an FPGA. Two designs have been carried out. Design I with 16 phases and Design II with 36. A. Design I Main characteristics of this prototype are as follows. Number of phases: 16. Power per phase: 62.5 W. Phase switching frequency: 150 kHz. Inductor per phase: 5.4 H (RM7). MOSFETs: SI4450DY (SO-8 package). Driver: IR2181S (2 drivers in a SO-8 package). The current per phase at full load is shown in Fig. 8. It can be seen that the current ripple is high enough to achieve zerovoltage switcing (ZVS) in both transitions. In these conditions, the efciency is maximum (it has been experimentally checked [14]) and a good current balance is achieved. This prototype has been tested in CCM and DCM to see the performance about current unbalance [15]. The main conclusion is that DCM is much better than CCM but, thanks to the accuracy of the digital control, the equilibrium in CCM is quite good.

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Fig. 11. (a) Measured current waveforms and (b) dc value in the 36-phases prototype at half-load; same in (c) and (d) but at full load.

Fig. 13. Efciency of the converter with 36 phases as a function of the output current. Fig. 12. Evolution of four phase currents of the converter during a transient.

These converters have been designed with automotive specications. The main feature is that they have been implemented using surface mounting devices (SMD), keeping a very good efciency (94%95%), and avoiding the use of heatsinks. Thus, the look of these dc/dc converters is rather different than others of the state of the art in the same power range, mainly because their low prole. The two main problems associated with many power stages have been overcome in this proposal.

The converter can be designed avoiding the use of current loops that would not be feasible with a very high number of phases. Although DCM is preferred, it is possible also in CCM as shown in the prototypes. DC currents are in the 10% range without any active compensation mechanism. A specic digital control has been built. There are many signals to generate but all of them are simple. Thanks to the accuracy and concurrency, an FPGA is the suitable device that contributes to equalize the dc currents of the converters.

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Fig. 14. Prototype made with 36 phases: (a) MOSFETs and drivers PCB and (b) inductors and capacitors PCB.

Oscar Garca (M99) was born in Madrid, Spain, in 1968. He received the M.S. and Ph.D. degrees in electronic engineering from the Universidad Politcnica de Madrid (UPM), Madrid, Spain, in 1992 and 1999, respectively. He is an Associate Professor with UPM. He has been involved in more than 25 research projects, holds three patents, and he has published nearly 100 papers in IEEE conferences and journals. His research interests are switching mode power supplies, power factor correction, power architectures, and digital control applied to power electronics. Dr. Garcia is a member of the IEEE-PELS-IES Spanish Chapter.

The feasibility of building a medium power converter using very small power transistors and magnetic components and using low power techniques has been demonstrated.

REFERENCES
[1] B. A. Miwa, D. M. Otten, M. E. Schlecht, and , High efciency power factor correction using interleaving techniques, in Proc. IEEE Appl. Power Electron. Conf. Expo (APEC92), 1992, pp. 55756. [2] A. Consoli, G. Scarcella, G. Giannetto, and A. Testa, A multiphase DC/DC converter for automotive dual voltage power systems, IEEE Ind. Applicat. Mag., vol. , pp. 3542, Nov./Dec. 2004. [3] T. C. Neugebauer and D. J. Perrault, Computer aided optimization of DC/DC converters for automotive applications, in Proc. IEEE Power Electron. Spec. Conf. (PESC00), 2000, vol. 2, pp. 689695. [4] M. Gerber, J. A. Ferreira, I. W. Hofsaer, and N. Seliger, Interleaving optimization in synchronous rectied DC/DC converters, in Proc. IEEE Power Electron. Spec. Conf. (PESC04), 2004, pp. 46554661. [5] J. Czogalla, J. Li, and C. R. Sullivan, Automotive application of multi-phase coupled-inductor DC-DC converter, in Proc. Ind. Applicat. Conf., 2003, vol. 3, pp. 15241529. [6] F. Z. Peng, F. Zhang, and Z. Quian, A magnetic-less dc-dc converter for dual voltage automotive systems, IEEE Trans. Ind. Applicat., vol. 39, no. 2, pp. 511518, Mar./Apr. 2003. [7] L. Jourdan, J. L. Schanen, J. Roudet, M. Bensaeid, and K. Segueni, Design methodology for non insulated DC-DC converter: application to 42 V14 V Powernet, in Proc. IEEE Power Electron. Spec. Conf. (PESC02), 2002, vol. 4, pp. 16791684. [8] J. A. Oliver, P. Zumel, O. Garca, J. A. Cobos, and J. Uceda, Passive component analysis in interleaved buck converters, in Proc. IEEE Appl. Power Electron. Conf. (APEC04), 2004, vol. 1, pp. 623628. [9] High Efciency High Density Polyphase Converters for High Current Applications, Application note 77, Linear Technology Inc., Sep. 1999. [10] A. de Castro, T. Riesgo, O. Garcia, and J. Uceda, A methodology to design custom hardware digital controllers for switching power converters, in Proc. IEEE Power Electron. Spec. Conf. (PESC04), 2004, vol. 6, pp. 46764681. [11] High-frequency multiphase controller, Tech. Rep. TPS40090, Texas Instrument Datasheet, Oct. 2003. [12] Polyphase, high efciency, synchronous step-down switching regulators, Tech. Rep. LTC1629, Linear Technology Datasheet, 1999. [13] A. V. Peterchev, J. Xiao, and S. R. Sanders, Architecture and IC implementation of a digital VRM controller, IEEE Trans. Power Electron., vol. 18, no. 1, pp. 356364, Jan. 2003. [14] O. Garcia, P. Zumel, A. de Castro, and J. A. Cobos, High current dcdc converter with SMT components, in Proc. IEEE Appl. Power Electron. Conf. (APEC05), Mar. 2005, vol. , pp. 14011406. [15] O. Garcia, P. Zumel, A. de Castro, J. A. Cobos, and J. Uceda, An automotive 16 phases DC/DC converter, in Proc. IEEE Power Electron. Spec. Conf. (PESC04), 2004, vol. 1, pp. 350355.

Pablo Zumel received the B.S degree in electrical engineering from the University of Burgos, Burgos, Spain, in 1995, the M.S. from the Ecole Centrale Paris, Paris, France, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from the Universidad Politcnica de Madrid (UPM), Madrid, Spain, in 1999 and 2005, respectively. From 1999 to 2003, he was a Researcher in the Divisin de Ingeniera Electrnica, UPM. Since 2003, he has been with the Departamento de Tecnologa Electrnica, Universidad Carlos III de Madrid, where he is currently an Assistant Professor. His current research interests include multiphase dcdc converters, magnetic integration, digital control in power electronics and educational issues on power electronics.

Angel de Castro was born in Madrid, Spain, in 1975. He received the M.Sc. and the Ph.D. degrees in electrical engineering from the Universidad Politcnica de Madrid (UPM), Madrid, Spain, in 1999 and 2004, respectively. He has been an Assistant Professor with UPM since 2003. His research interests include digital control of switching mode power supplies, digital circuits design, sensor networking, and smart transducers.

Jos A. Cobos (M92) received the M.S. and Ph.D. degrees in electrical engineering from the Universidad Politcnica de Madrid (UPM), Madrid, Spain, in 1989 and 1994, respectively. He has been a Professor with UPM since 2001. He is Vice Dean for Research and Doctoral studies of the ETS Ingenieros Industriales of the UPM. His contributions are focused in the eld of power supply systems for telecom, aerospace, automotive and medical applications. His research interests include low output voltage, magnetic components, piezoelectric transformers, transcutaneous energy transfer, and dynamic power management. He has published over 150 technical papers and holds three patents. He has been actively involved in over 40 R&D projects for companies in Europe, USA, and Australia. Dr. Cobos received several awards, including the UPM Research and Development Award for faculty less than 35 years of age and the Richard Bass Outstanding Young Power Electronics Award of the IEEE in 2000. He is an Associate Editor of the IEEE POWER ELECTRONICS LETTERSand the IEEE TRANSACTIONS ON POWER ELECTRONICS. He is an AdCom member of the IEEE Power Electronics Society (PELS), and Chair of the Technical Committee on dc Power Systems.