Draft copy for adoption: LABORATORY MANUAL

ELECTRONIC CIRCUITS ANALYSIS B.Tech II nd yr ECE

Prepared at siddarth institute o en!ineerin! and techno"o!y

Design and review by.

A.#ARUNA#AR M.Tech.$ Assistant pro essor. s.%ARI PRASA& B.Tech$ Assistant pro essor. &epart'ent o E.C.E

LIST O( E)PERIMENTS

*.Co''on e'itter a'p"i ier +. Co''on source a'p"i ier ,.A t-o sta!e RC coup"ed a'p"i ier ..Current shunt and /o"ta!e series eed0ac1 a'p"i ier 2.Cascade a'p"i ier 3.4ien 0rid!e osci""ator usin! transistors 5.RC phase shi t osci""ator usin! transistors 6.C"ass A po-er a'p"i ier 7.C"ass B co'p"i'entary sy''etry a'p"i ier *8.%i!h re9uency co''on 0ase :B;T<=co''on !ate :;(ET< a'p"i ier

ELECTRONIC CIRCUITS LAB

E)P . NO. *. T4O STA>E RC?COUPLE& AMPLI(IER *. AIM@ To Design and study the response of a two stage RC-coupled amplifier and calculation of gain and band width. +. EAUIPMENTS AN& COMPONENTS@ i.APPARATUS 1. CRO (Dual channel DC-!" #$% !. 'read 'oard ). Regulated power supply- "-)"* 1 +, -. D## ) . Digit /CD hand held 0. 1unction generator ( #h2 ii.COMPONENTS@ 1. 3!45 Resistor 6 ! &o. !. -.745 Resistor 6 ) &o. ). 1.05 Resistor 6 ! &o -. ))45 Resistor 6 ! &o 0. 145 Resistor 6 ! &o 3. 1" 8 19 13 : ;lectrolytic Capacitor 6 ) &o. 7. ".1 81913 : ;lectrolytic Capacitor 6 ! &o <. Transistors 6 'C1"7 6 ! &o. +ll resistors are carbon 9 metal film = > 0? unless otherwise specified. 1 &o ( &o. . 1 &o. 1&o 1 &o.

,. T%EORY@ +s the gain pro*ided by a single stage amplifier is usually not sufficient to dri*e the load, so to achie*e e@tra gain multi-stage amplifier are used. An multi-stage amplifiers output of one-stage is coupled to the input of the ne@t stage. The coupling of one stage to another is done with the help of some coupling de*ices. Af it is coupled by RC then the amplifier is called RC-coupled amplifier. 1reBuency response of an amplifier is defined as the *ariation of gain with respecti*e freBuency. The gain of the amplifier increases as the freBuency increases from %ero till it becomes ma@imum at lower cut-off freBuency and remains constant till higher cut-off freBuency and then it falls again as the freBuency increases.

+t low freBuencies the reactance of coupling capacitor CC is Buite high and hence *ery small part of signal will pass through from one stage to the ne@t stage. +t high freBuencies the reactance of inter electrode capacitance is *ery small and beha*es as a short circuit. This increases the loading effect on ne@t stage and ser*ice to reduce the *oltage gain due to these reasons the *oltage gain drops at high freBuencies. +t mid freBuencies the effect of coupling capacitors is negligible and acts li4e short circuit, where as inter electrode capacitors acts li4e open circuit. Co, the circuit becomes resisti*e at mid freBuencies and the *oltage gain remains constant during this range. .. CIRCUIT &IA>RAM@

Vcc 12.0

62 .0k

33 .0k

100.0n 1.0k T1 !NPN

245mv

33 .0k

62 .0k

6.63v

4.7k

100.0n
842mv

6.63v

10.0u

842mv

T2 !NPN
245mv

Vout+ 1.0 k

4.7 k

Vin

1.5 k

1.5 k

10 .0u

10 .0u

4.7 k

ALTERNATE CIRCUIT @
V cc 12.0

47 .0k

2.2 k

47 .0k

10.0u

10.0k 10.0u
2.05v

10 .0u

8.94v

10.0k

2.2 k

8.94v

10.0u

T1 !NPN 10 .0k
1.4v

2.05v

T2 !NP N 2.2 k
1.4v

Vout+ 10 0.0 u

10 .0k

Vin

1.0 k

10 0.0 u

2. PROCE&URE@ i.. Connect the circuit on bread board as shown in the circuit diagram.

ii. #easure base ,emitter and collector D.C *oltages of both stages and compare against estimated *alues. ;stimated *oltages :b1 ,:c1, :e1 :b!, :c!, :e! iii. 'y 4eeping the amplitude of the input signal constant, *ary the freBuency from %ero to 1 #$%. i*. &ote down the amplitude of the output signal for corresponding *alues of input freBuencies. *. *i. Calculate the *oltage gain in decibels. Dlot in semi-log graph between gain *s freBuency and calculate the band width. Obser*ed *oltages

10 .0k

1.0 k

3. OBSERBATIONS@
C.&O

1R;EF;&CG

:OFT

H+A&I :OFT 9:A&

H+A& in d'

5. CALCULATIONS@ i. ii. Determine lower cut-off freBuency and upper cut-off freBuency from the graph. Calculate 'and width.

6. >RAP%@

7. RESULT@ i. ii. /ower cut-off freBuency I Fpper cut-off freBuency I

iii. 'and width I *8. IN(ERENCES@ This circuit is useful for amplification by pro*iding higher gain in the range JJJJJJJJJJ **. PRECAUTIONS@
i. ii. Test Transistors be ore assemb!in" t#e circuits $ark %o!arities o e!ectro!&tic ca%acitors an' connect.

iii. (%%!& vo!ta"e rom t#e %o)er su%%!& an' %rocee' urt#er on!& a ter obtainin" e*%ecte' +, vo!ta"es at base emitter co!!ector o t#e transistors.

iv. - above are correct &ou can a%%!& si"na! rom unction "enerator an' monitor t#e out%ut on ,./ an' a'0ust si"na! am%!itu'e suc# t#at out%ut seen in ,./ is ree rom roun'in" an' c!i%%in" o t#e si"na!s. v. - &ou ace an& %rob!em )it# si"na! on ,./ 'ue to )ron" settin"s o t#e contro!s c#eck u% connections to ,./

*i Resistors should be connected properly with out interchanging the *alues. *ii .Chec4 the continuity of the connecting wires. *+. APPLICATIONS@ 1. +udio amplifiers !. Radio Transmitters and Recei*ers. *,. E)TENSIONS@

An general multi-stage amplifiers are used to pro*ide high o*erall gain for the applied input signal. An this e@periment, we *erified this with two stages coupled with resistors and capacitors. >e can e@tend the circuit diagram with one or more stages cascading with the gi*en two stages RC coupled amplifier. >e can e@tend low freBuency range by increasing coupling and bypass capacitors. 'y employing negati*e feedbac4, we can ensure constant gain against de*ice parameters. This e@periment is carried on with two stages of amplifiers operating with low current. RC coupling can be made between amplifiers with any type of biasing methods instead of *oltage di*ider bias as shown. +n alternate circuit is shown to enlarge this scope of study of RC amplifier (1 study effect of indi*idual /1 cutoff on the o*erall cutoff. (! #easure input impedance of amplifier () Ctudy effect on o*erall /1 cutoff due to indi*idual RC couplings at the input and emitter by capacitors. (- +pply small sBuare wa*e and measure rise times on indi*idual stages and *erify formula on rise times. (0 Cince high freBuency cutoff is determined by output capacitance of transistors 1:1 probes used on CRO can lower $1 cutoff. An order to a*oid this effect intentionally a large capacitors of ".1 microfarad or the li4e is connected such that high freBuency cutoff falls well below 1 megahert%. *.. TROUBLE S%OOTIN>@ S.NO 1. !. ). (AULT Af there is no output Af the output is distorted Af DC *oltages differ *ery much &IA>NOSIS Chec4 :cc and all DC *oltages. Chec4 function generator. Chec4 CRO connections. Chec4 :cc and all DC *oltages Chec4 amplitude of input signal. Chec4 entire circuit for connections, resistance *alues and placements Chec4 Transistors.

10. Cpecial tip to measure 'andwidth without graph. graph. &ote amplitude at mid band and *ary freBuency towards low freBuency till amplitude falls by )"? ./et this be f1. Repeat this step towards high freBuency end until amplitude falls by )"?./et this be f!. 'and width is f!-f1.

*2. AUESTIONS@ i. ii. iii. i*. *. *i. *ii. *iii. i@. @. >hat are the ad*antages and disad*antages of multi-stage amplifiersK >hy gain falls at $1 and /1K >hy the gain remains constant at #1K ;@plain the function of emitter bypass capacitor, CeK $ow the band width will effect as more number of stages are cascadedK Define freBuency responseK Hi*e the formula for effecti*e lower cut-off freBuency, when &-number of stages are cascaded. ;@plain the effect of coupling capacitors and inter-electrode capacitances on o*erall gain. 'y how many times effecti*e upper cut-off freBuency will be reduced, if three identical stages are cascadedK #ention the applications of two-stage RC-coupled amplifiers. E)P.NO.+ SERIES BOLTA>E RE>ULATOR *. AIM@ To design a transistori%ed series *oltage regulator and study the regulation action for i. ii Different *alues of input *oltages Different *alues of load resistors and also to find percentage regulation.

+. EAUIPMENTS AN& COMPONENTS@ i.APPARATUS 1. !. ). -. CRO (Dual channel DC-!" #$% 'read 'oard Regulated power supply- "-)"* 1 +, D## ) . Digit /CD hand held 1 &o ( &o. . 1 &o. 1&o

ii. COMPONENTS@ 1. 145 Resistor 6 1 &o. !. 03"5 Resistor 6 1 &o. ). 14 , !4 , -.74, 1"4 (load resistors 6 1 &o each. -. 2ener diode 6 1 &o. 0. Transistor 6 C/1"" 6 1 &o. +ll resistors are carbon 9 metal film = > 0? unless otherwise specified.

,. T%EORY@ :oltage regulator is a de*ice designed to maintain the output *oltage as nearly constant as possible. At monitors the output *oltage and generates feed bac4 that automatically increases are decreases the supply *oltage to compensate for any changes in output *oltage that might occur because of change in load are changes in load *oltages. An transistori%ed series *oltage regulator the control element is a transistor which is in series with load. must be operated in re*erse brea4 down region, where it pro*ides constant *oltage irrespecti*e of changes in applied *oltages.The output *oltage of the series *oltage regulator is :o I :% 6 :be. Cince, :% is constant, any change in :o must cause a change in :be in order to maintain the abo*e eBuation. Co, when :o decreases :be increases, which causes the transistor to conduct more and to produce more load current, this increase in load causes an increase in :o and ma4es :o as constant. Cimilarly, the regulation action happens when :o increases also. .. CIRCUIT &IA>RAM@

560.0 1.0k

T1 !NPN

11 21+27 3,5 V1

Vout + 1.0k

10 30v Vin 1.0

2. PROCE&URE@ i. ii. iii. Connect the circuit as shown in the circuit diagram. +pply the input *oltage from power supply. #easure base ,emitter and collector D.C *oltages and compare against estimated *alues. ;stimated *oltages :b1 ,:c1, :e1 :% i*. *. *i. *ii. 1or a specific *alue of load resistor, *ary the input *oltage from 1" to a ma@imum of !" *olts and not the *alues of output *oltage. Change the load resistor and repeat steps ! and ). Remo*e the load resistor and note down the *oltage at no load. 1ind percentage regulation. V NL V FL x1"" Dercentage regulation I V FL Dlot the graph for load regulation and line regulation. Obser*ed *oltages

*iii.

3. OBSERBATIONS@

S.no

Bin RLC

Output /o"ta!e RLC RLC

5. CALCULATIONS@ Dercentage load regulation I V NL V FL x1"" I V FL

Dercentage /ine Regulation I (change in output 9 (change in input L 1""

6. >RAP%@

7. RESULT@ 1or R/ I ----------------, Regulating range isJJJJJJJJJJJJ 1or R/ I ----------------, Regulating range isJJJJJJJJJJJJ 1or R/ I ----------------, Regulating range isJJJJJJJJJJJJ *8. IN(ERENCES@ This Ceries Regulator is useful for the input *oltage range JJJJJJJJJJJJJJ

**. PRECAUTIONS@
i. Test Transistors4 5ener 'io'e be ore assemb!in" in t#e circuits.

ii.

(%%!& vo!ta"e rom 15 V an' ensure t#e +, vo!ta"es as s#o)n t#e circuit are obtaine'. ,#eck circuit connections an' com%onents i e*%ecte' vo!ta"es are not obtaine'. ,#eck resistor va!ues %ro%er!& ot#er)ise %o)er su%%!& ma& be over !oa'e' 'ue to sma!! va!ues. - 1ener is reverse' no 'ama"e )i!! occur but out%ut vo!ta"e )i!! a!! 'o)n to 0 V. +on6t s#ort t#e out%ut as t#is )ou!' resu!t in !ar"e current t#rou"# t#e series transistor )#ic# )i!! !ea' to burnin" o t#e same 'ue to over#eat.

iii.

iv. v.

*+. APPLICATIONS@ 1. !. ). /ow current applications. 1i@ed *oltage applications ;@tention of %ener regulator for higher currents.

*,. E)TENSIONS@ The main function of *oltage regulator is to regulate the changes in output *oltage for the changes occur either in input *oltage *ariations or output load *ariations. An this e@periment we ha*e *erified for one particular *alue of output *oltage. >e can obtain *oltage regulation at higher *oltages with the help of more number of 2ener diode operating in brea4 down region, must be connected in series. 1or e@ample, to obtain *oltage regulation at <.! *olts, we can use the same circuit with two 2ener diodes of *alues ).1 *olts and 0.1 *olts respecti*ely. 'y employing a series regulator with error amplifier , *ariable regulated *oltage can be obtained from circuit gi*en below. The e@periment is conducted is of simplest type to demonstrate use of %ener and series pass transistor without any unregulated *oltage power supply. An real application regulated power supply used at the input of this e@periment will be replaced by a full wa*e or bridge rectifier with capacitor input filter suitable to the load and ripple *oltages e@pected. The series transistor would be a power transistor with high current capacity and would be mounted to heat sin4. Ripple can be simulated by change in input and the corresponding change in output at a constant load current. One can obtain different fi@ed *oltages by suitably changing the %ener diode. One can obtain higher current ratings by employing suitable series power transistor and heat sin4s.

*.. TROUBLE S%OOTIN>@

S.NO 1. . !.

(AULT Af there is no output

&IA>NOSIS Chec4 :i and all DC *oltages. Chec4 CRO connections.

Af DC *oltages differ *ery much

Chec4 entire circuit for connections, resistance *alues and placements Chec4 Transistors.

*2. AUESTIONS@ i. ii. iii.. i*. *. *i. *ii. *iii. i@. @. Define *oltage regulator. Hi*e the ad*antages of series *oltage regulator. . ;@plain the feed bac4 mechanism in series *oltage regulator. An series *oltage regulator which is control element and e@plain its function. Define load and line regulation. >hat is ideal *alue K. >hich element determines output ripple K >hat determines ma@imum load current allowed in this circuit K #ention the applications of series *oltage regulator. Define no load *oltage and full load *oltage. ;@plain the term percentage regulation.

E)P .NO. , S%UNT BOLTA>E RE>ULATOR *. AIM@ To design a transistori%ed shunt *oltage regulator and obser*ing the regulation action for i. ii Different *alues of input *oltages Different *alues of load resistors and also to find percentage regulation.

+. EAUIPMENTS AN& COMPONENTS@ i.APPARATUS 1. !. ). -. CRO (Dual channel DC-!" #$% 'read 'oard Regulated power supply- "-)"* 1 +, D## ) . Digit /CD hand held 1 &o ( &o. . 1 &o. 1&o

ii.COMPONENTS@ 1. 145 Resistor 6 1 &o. !. 03"5 Resistor 6 1 &o. ). 14 , !4 , -.74, 1"4 (load resistors -. 2ener diode 6 A& -""7 - 1&o. 0. Transistor 6 C/1"" 6 !&o.

6 1 &o each.

+ll resistors are carbon 9 metal film = > 0? unless otherwise specified.

,. T%EORY@ + *oltage regulator is a de*ice or a combination of de*ices, design to maintain the output *oltage of a power supply as nearly constant as possible e*en if there are changes in load or in input *oltage. An shunt *oltage regulator transistor E1 acts as control element, which is in shunt with load *oltage. The output *oltage is gi*en as :o I :% M :R1 I :% M :be1 M :be! The regulation action of the circuit is e@plained below : Cince :% is constant, any changes in output *oltage reflects a propositional change in R1. Af the output *oltage decreases, *oltage across R1 decreases which in turn decreases the base *oltage of E!. +s a result the base current of E1 decreases which allows the load

*oltage to rise and ma4es it constant the same regulation action follows e*en if the output *oltage increases. .. CIRCUIT &IA>RAM@

. 7 5 6

9 7 0 : + + 1 V . 0 0+ 8 5

U S

n r e ! u " a t e d u p p " y

P
; 9 8

o 2 1 0 0+

e r
9

; 8

1 1

V b e 2

V b e 1

. 1

1 k

ALTERNATE CIRCUIT @

180.0 1N3 78 5
V5 < 6.3v

V'c 2 0.0

T1 !NPN

. 8 < 1k42k 4 4.7k 410k

1.0 k

1.0 k

2. PROCE&URE@ i. ii. iii. Connect the circuit as shown in the circuit diagram. +pply the input *oltage from power supply. #easure base ,emitter and collector D.C *oltages and compare against estimated *alues. ;stimated *oltages :b1 ,:c1, :e1 :b! ,:c!, :e! :% i*. i*. *. *i. 1or a specific *alue of load resistor, *ary the input *oltage from %ero to a ma@imum of !" *olts and note the *alues of output *oltage. Change the load resistor and repeat steps ! and ). Remo*e the load resistor and note down the *oltage at no load. 1ind percentage regulation. Dercentage regulation I *ii. V NL V FL x1"" V FL Dlot the graph for load regulation and line regulation. Obser*ed *oltages

3. OBSERBATIONS@ :O/T+H; +T &O-/O+D I S.no Bin RLC Output /o"ta!e RLC RLC

5. CALCULATIONS@ Dercentage regulation I 6. >RAP%@ V NL V FL x1"" V FL

7. RESULT@ 1or R/ I ----------------, Regulating range isJJJJJJJJJJJJ 1or R/ I ----------------, Regulating range isJJJJJJJJJJJJ 1or R/ I ----------------, Regulating range isJJJJJJJJJJJJ

*8. IN(ERENCES@ This Chunt Regulator is useful for the input *oltage range JJJJJJJJJJJJJJ **. PRECAUTIONS@
i. Procee' on t#e e*%eriment on!& a ter obtainin" e*%ecte' +, vo!ta"es 'o not a%%!& more t#an 20 V )it#out connectin" !oa' on t#e out%ut as t#is )ou!' resu!t in ma*imum current in s#unt transistors. 9#ortin" t#e out%ut )i!! resu!t in over#eatin" series resistors )#ic# ma& burn at #i"# vo!ta"e. .eversin" t#e 5ener ma& not 'ama"e t#e circuit but resu!t in out%ut vo!ta"e to 'ro% 2 V or !ess.

ii.

iii.

*+. APPLICATIONS@ 1. !. /ow current applications. 1i@ed *oltage applications

*,. E)TENSIONS@ The main function of *oltage regulator is to regulate the changes in output *oltage for the changes occur either in input *oltage *ariations or output load *ariations. An this e@periment we ha*e *erified for one particular *alue of output *oltage. >e can obtain *oltage regulation at higher *oltages with the help of more number of 2ener diode operating in brea4 down region, must be connected in series. 1or e@ample, to obtain *oltage regulation at <.! *olts, we can use the same circuit with two 2ener diodes of *alues ).1 *olts and 0.1 *olts respecti*ely.

T#e e*%eriment is con'ucte' is o sim%!est t&%e to 'emonstrate use o 5ener an' series %ass transistor )it#out an& unre"u!ate' vo!ta"e %o)er su%%!&. -n rea! a%%!ication re"u!ate' %o)er su%%!& use' at t#e in%ut o t#is e*%eriment )i!! be re%!ace' b& a u!! )ave or bri'"e recti ier )it# ca%acitor in%ut i!ter suitab!e to t#e !oa' an' re%u!e vo!ta"es e*%ecte'. T#e series transistor )ou!' be a %o)er transistor )it# #i"# current ca%acit& an' )ou!' be mounte' to #eat sink..i%%!e can be simu!ate' b& c#an"e in in%ut an' t#e corres%on'in" c#an"e in out%ut at a constant !oa' current. /ne can obtain 'i erent i*e' vo!ta"es b& suitab!& c#an"in" t#e 5ener 'io'e. /ne can obtain #i"#er current ratin"s b& em%!o&in" suitab!e series %o)er transistor an' #eat sinks.

*.. TROUBLE S%OOTIN>@ S.NO (AULT 1. . !. Af there is no output

&IA>NOSIS Chec4 :i and all DC *oltages. Chec4 CRO connections.

Af DC *oltages differ *ery much

Chec4 entire circuit for connections, resistance *alues and placements Chec4 Transistors.

*2. AUESTIONS@ i. ii. iii. i*. *.. *i. *ii. *iii. i@. . @. #ention the differences between shunt and series *oltage regulators. >hat is the function of E1 and E! in the shunt regulator .circuit K Define the line regulation. +nd load regulation. >hat is current through %ener in this circuit K >hen is dissipation ma@imum in this circuit K An the circuit of shunt *oltage regulator which element is considered control element and e@plain its function. Can you do the e@periment without E! K. $ow can you increase current range of regulator K Af output is 1.- * for input of !"* what was the wrongly connected K #ention the applications of shunt *oltage regulator.

E)P. NO. . SERIES (E& CLASS?A PO4ER AMPLI(IER

*. AIM@ To design a series fed class-+ power amplifier in order to achie*e ma@ out put ac power and efficiency. +. EAUIPMENTS AN& COMPONENTS@ i.APPARATUS 1. !. ). -. 0. CRO (Dual channel DC-!" #$% 'read 'oard Regulated power supply- "-)"* 1 +, D## ) . Digit /CD hand held 1unction generator ( #h2 1 &o ( &o. . 1 &o. 1&o 1 &o.

ii. COMPONENTS@ 1. !"45 Resistor 6 1 &o. !. 145 Resistor 6 ! &o. ). ".1 81913 : ;lectrolytic Capacitor 6 ! &o. -. Transistor 6 C/1"" 6 1&o. +ll resistors are carbon 9 metal film = > 0? unless otherwise specified.

,. T%EORY@ The abo*e circuit is called as Nseries fedO because the load R/ is connected in series with transistor output. At is also called as direct coupled amplifier. ACE I 2ero signal collector current :C;E I 2ero signal collector to emitter *oltage Dower amplifiers are mainly used to deli*er more power to the load. To deli*er more power it reBuires large input signals, so generally power amplifiers are preceded by a series of *oltage amplifiers. An class-+ power amplifiers, E-point is located in the middle of DC-load line. Co output current flows for complete cycle of input signal. Fnder %ero signal condition, ma@imum power dissipation occurs across the transistor. +s the input signal amplitude increases power dissipation reduces. The ma@imum theoretical efficiency is !0?.

..CIRCUIT &IA>RAM@

20 .0k

1.0 k

Vcc 5.0

2.83v

100.0n +

100.0n T1 !NPN
666mv

A
1.0 k

i8

V
Vout

Vin

2. PROCE&URE@ i. #a4e the connections as per the circuit diagram.

ii. #easure base ,emitter and collector D.C *oltages of both stages and compare against estimated *alues. ;stimated *oltages :b1 ,:c1, :e1 iii. i*. *. i. +pply the input at input terminals of the circuit from the function generator. Peep the input signal at constant freBuency under mid freBuency region and adQust the amplitude such that output *oltage undistorted. Calculate the power efficiency and compare it with theoretical efficiency. Obser*ed *oltages

3. OBSERBATIONS@ ;fficiency is defined as the ratio of +C output power to DC input power DC input power I :cc @ ACE

+C output power I :D-D! 9 <R/ 5. CALCULATIONS@ Fnder %ero signal condition: :cc I A'R' M :'; A'E I( :cc - :'; 9 R' ACE I R @ A'E :C; I :cc - ACRC 6. >RAP%@

7. RESULT@ The ma@imum input signal amplitude which produces undistorted output signal is JJJJJJJJJ The practical efficiency of the circuit is JJJJJJJJ *8. IN(ERENCES@ The efficiency obser*ed is JJJJJJJJJJJ against theoretical ma@imum of !0?, since JJJJJJJJJJJJJJJJJJJ **. PRECUATIONS@
i. -t is a necessar& to in' a suitab!e .2 re=uire' or biasin" t#e am%!i ier co!!ector at t#e centre o vo!ta"e V,,>2 i.e. 6 V. t#is s#a!! be 'one b& tria! an' error or usin" a 'eca'e resistance bo*. ?#i!e observin" on ,./ at co!!ector o t#e transistor &ou can veri & )#et#er &ou are "ettin" un'istorte' %eak to %eak si"na! o at !east 10 to 11 V 9ince (, an' +, !oa' !ines are 'i erent %eak to %eak si"na! )it#out connectin" ca%acitor an' !oa' on t#e co!!ector o transistor )i!! be 'i erent t#an t#e rea'in" )it# above connecte'.

ii.

iii.

*+. APPLICATIONS@ This is used for low power linear applications in audio and wideband R1 range, where high efficiency is not reBuired. *,. E)TENSIONS@ An series fed class-+ power amplifier we ha*e calculated the efficiency i.e. how efficiently DC-power is con*erted into +C-power depending on the magnitude of input signal Once we design a power amplifier for a particular efficiency, the circuit will not gi*e that efficiency to all its input signals of different amplitudes. $ence, depending on the input signal we ha*e to choose :cc to obtain a particular efficiency. . 'y employing Transformer coupling, efficiency can be impro*ed to 0"?.

T#e e*%eriment is con'ucte' usin" !o) %o)er transistors !ike 2,1074 98100 on!& to "et ami!iarit& in biasin" an' measurement. (ctua! %o)er am%!i iers o%erate at 1 )att to 100 )atts. T#is )i!! ca!! or o%eratin" transistors #i"# current an' sma!! va!ue resistors o "reater t#an 1>4 to 1 )att )#ic# are use' in t#e !aborator&. (ctua! %o)er am%!i iers use #eat sinks on t#e transistors.

*.. TROUBLE S%OOTIN>@ S.NO 1. !. ). (AULT Af there is no output Af the output is distorted Af DC *oltages differ *ery much &IA>NOSIS Chec4 :cc and all DC *oltages. Chec4 function generator. Chec4 CRO connections. Chec4 :cc and all DC *oltages Chec4 amplitude of input signal. Chec4 entire circuit for connections, resistance *alues and placements Chec4 Transistors.

*2. AUESTIONS@ i. ii. iii. i*. *. *i. *ii. *iii. i@. @. Differentiate between *oltage amplifier and power amplifier >hy power amplifiers are considered as large signal amplifierK >hen does ma@imum power dissipation happen in this circuit K. >hat is the ma@imum theoretical efficiencyK C4etch wa*e form of output current with respecti*e input signal. >hat are the different types of class-+ power amplifiers a*ailableK >hat is the theoretical efficiency of the transformer coupled class-+ power amplifierK >hat is difference in +C, DC load lineK. $ow do you locate the E-point K >hat are the applications of class-+ power amplifierK E)P. NO. 2 TRANS(ORMER COUPLE& CLASS?A PO4ER AMPLI(IER

*.AIM@ To design a transformer coupled class-+ power amplifier in order to achie*e ma@imum out put +C power and efficiency. +. EAUIPMENTS AN& COMPONENTS@ i.APPARATUS 1. !. ). -. 0. CRO (Dual channel DC-!" #$% 'read 'oard Regulated power supply- "-)"* 1 +, D## ) . Digit /CD hand held 1unction generator ( #h2 1 &o ( &o. . 1 &o. 1&o 1 &o.

ii. COMPONENTS @ 1. 145 Resistor 6 1&o. !. 1"45 Resistor 6 1&o. ). 1""P5 Resistor 6 1&o. -. ".1 81913 : ;lectrolytic Capacitor 6 1 &o. 0. Ampedance matching Transformer 6 1 &o. 3. Transistor 6 C/1"" 6 1&o. +ll resistors are carbon 9 metal film = > 0? unless otherwise specified.

,. T%EORY@ An direct coupled class-+ power amplifier, power is wasted in load resistance which leads to decrease in efficiency. To achie*e ma@imum efficiency we can use transformer to couple the load. Cince transformer is used for impudence matching which facilitates the coupling between lower resistance and source impudenceK Due to +C coupling no DC power is wasted in the load resistor. The load DC resistance of transformer primary allows any desired le*el of collector current, while transferring only *ariations to R/. 'y this way the efficiency is increased. The ma@imum theoretical efficiency of transformer coupled power amplifier is 0"?. ;fficiency is defined as the ratio of +C output power to DC input power

DC input power I :cc @ ACE +C output power I :D-D! 9 <R/ .. CIRCUIT &IA>RAM@

+ Vcc 12.0 10 0.0 k

-c T> @

1.0 k

Vout +

100.0n 10 .0k

11.49v

626m v

T1 !NPN

Vin

2. PROCE&URE: i. ii. #a4e the connections as per the circuit diagram. #easure base, emitter and collector D.C *oltages and compare against estimated *alues. ;stimated *oltages :b1 ,:c1, :e1 iii. i*. +pply the input at input terminals of the circuit from the function generator. Peep the input signal at constant freBuency under mid freBuency region and adQust the amplitude such that output *oltage undistorted. Obser*ed *oltages

*.

Calculate the power efficiency and compare it with theoretical efficiency.

3. OBSERBATIONS@ ;fficiency is defined as the ratio of +C output power to DC input power DC input power I :cc @ ACE +C output power I :D-D! 9 <R/ 5. CALCULATIONS@ Anput DC power I :cc @ ACE Output +C power I :rms @ Arms I :DD! 9 <R/ SI 6. >RAP%@ OutputACpower InputDCpower

7. RESULT@ a b The ma@imum input signal amplitude which produces undistorted output The practical efficiency of the circuit is JJJJJJJJ

signal is JJJJJJJJJ

*8. IN(ERENCES@ The efficiency obser*ed is JJJJJJJJJJJ against theoretical ma@imum of 0"?, since JJJJJJJJJJJJJJJJJJJ **. PRECUATIONS@ i. ii. iii. i*. *. *i. Chec4 the circuit connections before switching on the power supply. Chec4 the continuity of the connecting wires. Dower handling capacity of resistor should be 4ept in mind Control wires must be chec4ed before use #a@imum forward current should not e@ceed *alue gi*en in data sheet Resistors should be connected properly with out interchanging the *alues.

*+. APPLICATIONS@ This circuit is used for Ampedance matching and DC isolation. *,. E)TENSIONS@ An Transformer coupled class-+ power amplifier we ha*e calculated the efficiency i.e. how efficiently DC-power is con*erted into +C-power depending on the magnitude of input signal. Once we design a power amplifier for a particular efficiency, the circuit will not gi*e that efficiency to all its input signals of different amplitudes. $ence, depending on the input signal we ha*e to choose :cc to obtain a particular efficiency. 'y employing Transformer coupling, efficiency can be impro*ed to 0"?. The e@periment is conducted using low power transistors li4e 'C1"7, C/1"" only to get famimiliarity in biasing and measurement. +ctual power amplifiers operate at 1 watt to

1"" watts. This will call for operating transistors high current and small *alue resistors of greater than 19- to 1 watt which are used in the laboratory. +ctual power amplifiers use heat sin4s on the transsistors. This concept can be applied for R1 and Ampedance matching. *.. TROUBLE S%OOTIN>@ S.NO 1. (AULT Af there is no output &IA>NOSIS Chec4 :cc and all DC *oltages. Chec4 function generator. Chec4 CRO connections. Chec4 transformer. Chec4 :cc and all DC *oltages Chec4 amplitude of input signal. Chec4 entire circuit for connections, resistance *alues and placements. Chec4 transistors.

!. ).

Af the output is distorted Af DC *oltages differ *ery much

*2. AUESTIONS@ i. ii. iii . i*. *. *i.. *ii. *iii. i@. Differentiate between *oltage amplifier and power amplifier ;@plain impedance matching pro*ided by transformerK $ow do you determine ratings for transistor in this circuit K. >hat is the ma@imum theoretical efficiency of this amplifier K >hat is the range of conduction angle of output current with respecti*e input signalK C4etch DC load line and +C load line for this amplifier. >hat is collector *oltage of transistor with no and ma@imum signalK $ow is DC and +C power measured in this circuitK 1or class-+ operation how did you locate the E-point.

@.

>hat are the applications of class-+ power amplifierK

E)P. NO. 3 COMPLEMENTARY?SYMMETRY CLASS?B PO4ER AMPLI(IER *. AIM@ To design a complementary-symmetry class-' push-pull power amplifier in order to achie*e ma@imum out put +C power and efficiency. +. EAUIPMENTS AN& COMPONENTS@ i.APPARATUS 1. !. ). -. 0. CRO (Dual channel DC-!" #$% 'read 'oard Regulated power supply- "-)"* 1 +, D## ) . Digit /CD hand held 1unction generator ( #h2 1 &o ( &o. . 1 &o. 1&o 1 &o.

ii.COMPONENTS@

1. <5 = > 0? C1 Resistor 6 1 &o. !. 1 8 1 913 : ;lectrolytic Capacitor 6 1 &o. ). Transistors - C/1"" 6 1 &o. -. Transistor 6 CP 1"" 6 1 &o. ,. T%EORY@ Dower amplifiers are designed using different circuit configuration with the sole purpose of deli*ering ma@imum undistorted output power to load. Dush-pull amplifiers operating either in class-' are class-+' are used in high power audio system with high efficiency. An complementary-symmetry class-' power amplifier two types of transistors, &D& and D&D are used. These transistors acts as emitter follower with both emitters connected together. An class-' power amplifier E-point is located either in cut-off region or in saturation region. Co, that only 1<"o of the input signal is flowing in the output. An complementary-symmetry power amplifier, during the positi*e half cycle of input signal &D& transistor conducts and during the negati*e half cycle D&D transistor conducts. Cince, the two transistors are complement of each other and they are connected symmetrically so, the name complementary symmetry has come Theoretically efficiency of complementary symmetry power amplifier is 7<.0?.

..CIRCUIT &IA>RAM@

V cc 5.0 9 8100 !NP N 1.0u V in 9 A 100 !P NP V ee 5.0

0v

V out

8.0

ALTERNATE CIRCUIT @

Vcc 12.0

10.0u

22 0.0k

658mv

98100 !NPN 4.3 4.3 Vout 1.0k +

1.0k

18 .0 k

Vin

18 .0 k

10.0u

3658mv

9A100 !PNP

22 0.0k

Vee 12.0

2. PROCE&URE@ i. Connect the circuit has shown in the circuit diagram.

ii. #easure base ,emitter and collector D.C *oltages of both transistors and compare against estimated *alues.

;stimated *oltages :b1 ,:c1, :e1 :b!, :c!, :e!

Obser*ed *oltages

iii. +pply the input at input terminals of the circuit from the function generator.

i*. Peep the input signal at constant freBuency under mid freBuency region and adQust the amplitude such that output *oltage undistorted. *. Calculate the power efficiency and compare it with theoretical efficiency.

3. OBSERBATIONS@ ;fficiency is defined as the ratio of +C output power to DC input power DC input power I :cc @ ACE +C output power I :D-D! 9 <R/ 5. CALCULATIONS@ Anput DC power I :cc @ ACE Output +C power I :rms @ Arms I :DD! 9 <R/ SI OutputACpower InputDCpower

6. >RAP%@

7. RESULT@ The ma@imum input signal amplitude which produces undistorted output signal is JJJJJJJJJ The practical efficiency of the circuit is JJJJJJJJ *8. IN(ERENCES@ The practical efficiency of the circuit is JJJJJJJJ, because of JJJJJJJJJJJJJJ.

**. PRECUATIONS@ i.
ii. Bse matc#e' %air NPN C PNP transistors or t#is e*%eriments. $atc#in" can be 'one b& observin" # e o t#e transistor usin" +$$. Transistors recommen'e' are 981004 9A100.

iii. iv. v. vi.

Transistors #eat u% at !ar"e si"na! )#ic# is necessar& to obtain #i"# e icienc&. +o not s#ort t#e out%ut )#ic# )i!! resu!t in burnin" o t#e transistors. -n t#e absence o si"na! +, vo!ta"e at emitters is 0 V. ?#en a!ternate circuit uses series resistors to com%ensate an& 'i erence in V2: o transistors4 ensure obtainin" e*%ecte' +, vo!ta"es an' %rocee's a ter t#at.

*+. APPLICATIONS@ This circuit is used to dri*e low impedance without Transformer. This circuit is used to dri*e low impedance from DC onwards. *,. E)TENSIONS@
T#is e*%eriment is 'esi"ne' )it# !o) %o)er an' !o) !oa' current on!& to 'emonstrate basic %rinci%!es o ma*imum e icienc&4 crossover 'istortion an' 'rivin" sma!! !oa's )it#out trans ormer. (ctua! am%!i ier circuits o above t&%e can be oun' in au'io s&stems4 ra'io out%ut sta"es o mo'ern 'esi"ns. T#ese 'rive !ou' s%eakers 'irect!& )it#out an& trans ormers. Present au'io s&stems #ave %o)er ratin"s as muc# as 1000 )atts an' ra'ios #ave above 10 )atts. T#ese use com%!ementar& c!ass 2 %o)er am%!i iers in t#e basic are mo'i ie' orms. -n vie) o !ar"e %o)er invo!ve' s%ecia! -,s4 Transistors )it# #eat sinks are common.

*.. TROUBLE S%OOTIN>@ S.NO 1. !. ). (AULT Af there is no output Af the output is distorted Af DC *oltages differ *ery much &IA>NOSIS Chec4 M and 6 *e DC *oltages. Chec4 function generator. Chec4 CRO connections. Chec4 :cc and all DC *oltages Chec4 amplitude of input signal. Chec4 entire circuit for connections, resistance *alues and placements Chec4 Transistors.

*2. AUESTIONS@ i. ii. Aii . i*. *. *i. *ii. *iii. i@. @. Differentiate between *oltage amplifier and power amplifier ;@plain impedance matching pro*ided by transformerK Fnder what condition power dissipation is ma@imum for transistor in this circuitK >hat is the ma@imum theoretical efficiencyK C4etch current wa*eform in each transistor with respecti*e input signalK $ow do you test matched transistors reBuired for this circuit with D##K. >hat is the theoretical efficiency of the complementary stage amplifier. $ow do you measure DC and +C out put of this amplifierK As this amplifier wor4ing in class + or '. K $ow can you reduce cross o*er distortionK

E)P. NO. 5 CLASS?C TUNE& PO4ER AMPLI(IER *. AIM@ To design class-C tuned power amplifier and to study the class-c tuned power amplifier. +. EAUIPMENTS AN& COMPONENTS@ i.APPARATUS 1. !. ). -. 0. CRO (Dual channel DC-!" #$% 'read 'oard Regulated power supply- "-)"* 1 +, D## ) . Digit /CD hand held 1unction generator ( #h2 1 &o ( &o. . 1 &o. 1&o 1 &o.

ii.COMPONENTS @ 1. -.745 Resistor 6 1 &o. !. 1"45 Resistor 6 1 &o. ). ".1 81913 : ;lectrolytic Capacitor 6 1 &o. -.1" n1913 : ;lectrolytic Capacitor 6 1 &o. 0. 1" m$ Anductor 6 1 &o 3. Transistor 6 C/1"" 6 1&o. +ll resistors are carbon 9 metal film = > 0? unless otherwise specified.

,. T%EORY@ The efficiency of output circuit of an amplifier increases as the operation is shifted from class-+ to ' and then to C. An class-C amplifiers efficiency approaches 1""?. 'ut the difficulty with class-C operation is harmonic distortion is more. At is tuned amplifier and only one freBuency fo is to be amplified and power to be handled Do is large. Cince efficiency is high and harmonic distortion will not be a problem since only one freBuency is to be amplified and the tuned circuit will reQect the other freBuencies. The function of resonant circuits are: 1. To pro*ide correct load impedance to the amplifier. !. To reQect unwanted harmonics. ). To couple the power to load The resonant circuits in tuned power amplifier are called tan4 circuits.

.. CIRCUIT &IA>RAM@

Vcc<75V

10n@ 10k

98 100 +, -NPBT V/8T(E:

Vin

2. PROCE&URE@ i. ii. iii. i*. Connect the circuit as shown in diagram. The input terminals are connected to function generator and output terminals are connected to CRO. +pply the DC *oltage (:cc from regulated power supply. +dQust the input freBuency such that output *oltage is a perfect since sinusoidal wa*eform at a fi@ed freBuency..

4.7k

7 Vout

100n@

10 m D

*. *i. *ii.

&ote down corresponding output *oltages at different freBuencies. Dlot the wa*eforms of both input and output The freBuency at which the *oltage is ma@ and the freBuency should be compared with theoretical *alues.

3. OBSERBATIONS@ The *alue of Resonant freBuency at which ma@imum gain occurred is JJJJJJJJJ. 5. CALCULATIONS@ Theoretical *alue of resonant freBuency IJJJJJJJJJJJJJJJJJJJJ

6. >RAP%@

7. RESULT@ The freBuency at which the ma@imum amplification possible is JJJJJJJJJ. *8. IN(ERENCES@ This circuit can be used as class 6 C tuned power amplifier at the resonant freBuency possible is JJJJJJJJJJJJJJJJJ **. PRECUATIONS@ i. ii. Chec4 the circuit connections before switching on the power supply. Chec4 the continuity of the connecting wires.

iii. i*. *. *i. *ii. *iii.

Dower handling capacity of resistor should be 4ept in mind Control wires must be chec4ed before use #a@imum forward current should not e@ceed *alue gi*en in data sheet Resistors should be connected properly with out interchanging the *alues. chec4 all diodes transistors, coils ,with multi meter before putting in circuits. donot proceed unless you get e@pected dc *oltages.

*+. APPLICATIONS@ This is mainly used An radio transmitters and radio recei*ers *,. E)TENSIONS@
T#is e*%eriment is con'ucte' )it# sim%!est circuit to 'emonstrate c!ass , o%eration an' sma!! %o)er. To make measurements sim%!e t#e resonant re=uenc& is c#osen aroun' 10 to 20 A#5. -n rea! a%%!ication c!ass , am%!i iers are use' at #i"#er %o)er an' re=uencies o .@ ran"e )#ic# )i!! ca!! or !o) va!ues o in'uctance an' #i"# =ua!it& ca%acitors an' transistors. 2& c#an"in" va!ue o t#e !oa' one can obtain 'i erent ban' )i't# as em%!o&e' in t#e circuit use'. 2ut rea! a%%!ication !oa' is a %art o resonant circuit to re !ect !oa' on tank circuit to 'etermine ; o t#e circuit. .ea! circuits em%!o&in" c!ass , o%erations are oun' in ra'io transmitters4 u!trasonic c!eaners. .a'io transmitters o%erate at 10 to 30 A)atts em%!o&in" vaccum tubes.

*.. TROUBLE S%OOTIN>@ S.NO 1. (AULT Af no output &IA>NOSIS Chec4 whether C.R.O . Chec4 if signal around resonance freB !. Cmall output Chec4 function generator output.

*2. AUESTIONS@

i. >hat are the different types of tuned circuits K ii. $ow do you measure DC and +C power in the class C amplifier K iii. >hat is E of Tuned circuit employed in circuit K i*. $ow is class C operation obtained in this circuit K *. Ctate relation between resonant freBuency and bandwidth of a Tuned amplifier. *i. Differentiate between &arrow band and >ideband tuned amplifiers K *ii. $ow is harmonic distortion is reduced in class-C Tuned amplifiersK *iii. C4etch current wa*eform in the transistor..

i@. Calculate bandwidth of a Tuned amplifier whose resonant freBuency is 10P$% and E-factor is 1"". @. Cpecify the applications of Tuned amplifiers.

E)P.NO.6 BARIABLE SERIES BOLTA>E RE>ULATOR

*. AIM@ To design a transistori%ed *ariable series *oltage regulator and study the regulation action for i. Different *alues of input *oltages ii Different *alues of load resistors

+nd also to find percentage regulation. +. EAUIPMENTS AN& COMPONENTS@ i.APPARATUS 1. !. ). -. CRO (Dual channel DC-!" #$% 'read 'oard Regulated power supply- "-)"* 1 +, D## ) . Digit /CD hand held 1 &o ( &o. . 1 &o. 1&o

ii. COMPONENTS@ 1. 1.<45 Resistor 6 1 &o. !. -.745 Resistor 6 1 &o. ). 1"45 Resistor 6 1&o -. 1"45 *ariable Resistor 6 1 &o 0. 14 , !4 , -.74, 1"4 (load resistors 6 1 &o each. 3. 2ener diode 6 A& 0!0) 6 1 &o. 7. Transistor 6 C/1"" 6 ! &o. +ll resistors are carbon 9 metal film = > 0? unless otherwise specified.

,. T%EORY@ :oltage regulator is a de*ice designed to maintain the output *oltage as nearly constant as possible. At monitors the output *oltage and generates feed bac4 that automatically increases are decreases the supply *oltage to compensate for any changes in output *oltage that might occur because of change in load are changes in load *oltages. An transistori%ed series *oltage regulator the control element is a transistor which is in series with load. The main element used for regulation of output *oltage is 2ener diode, which must be operated in re*erse brea4 down region, where it pro*ides constant *oltage irrespecti*e of changes in applied *oltages. The output *oltage of the series *oltage regulator is :o I :% 6 :be.

Cince, :% is constant, any change in :o must cause a change in :be in order to maintain the abo*e eBuation. Co, when :o decreases :be increases, which causes the transistor to conduct more and to produce more load current, this increase in load causes an increase in :o and ma4es :o as constant. Cimilarly, the regulation action happens when :o increases also. .. CIRCUIT &IA>RAM@
98100

4.7k 1.8k 10.0k

10.0k
5.1V

2. PROCE&URE@ i. ii. iii. Connect the circuit as shown in the circuit diagram. +pply the input *oltage from power supply. #easure base ,emitter and collector D.C *oltages and compare against estimated *alues. ;stimated *oltages :b1 ,:c1, :e1 :% iii. i*. *. *i. 1or a specific *alue of load resistor, *ary the input *oltage from 1" to a ma@imum of !" *olts and not the *alues of output *oltage. Change the load resistor and repeat steps ! and ). Remo*e the load resistor and note down the *oltage at no load. 1ind percentage regulation. V NL V FL x1"" Dercentage regulation I V FL Dlot the graph for load regulation and line regulation. Obser*ed *oltages

*ii.

V ou t

15330V

98100

.8 0.0

3. OBSERBATIONS@ S.no Bin RLC Output /o"ta!e RLC RLC

5. CALCULATIONS@ Dercentage load regulation I V NL V FL x1"" I V FL

Dercentage /ine Regulation I (change in output 9 (change in input L 1""

6. >RAP%@

7. RESULT@ 1or R/ I ----------------, Regulating range isJJJJJJJJJJJJ 1or R/ I ----------------, Regulating range isJJJJJJJJJJJJ 1or R/ I ----------------, Regulating range isJJJJJJJJJJJJ *8. IN(ERENCES@ This Ceries Regulator is useful for the input *oltage range JJJJJJJJJJJJJJ

**. PRECAUTIONS@

i. ii.

Test Transistors4 5ener 'io'e be ore assemb!in" in t#e circuits. (%%!& vo!ta"e rom 15 V an' ensure t#e +, vo!ta"es as s#o)n t#e circuit are obtaine'. ,#eck circuit connections an' com%onents i e*%ecte' vo!ta"es are not obtaine'. ,#eck resistor va!ues %ro%er!& ot#er)ise %o)er su%%!& ma& be over !oa'e' 'ue to sma!! va!ues. - 1ener is reverse' no 'ama"e )i!! occur but out%ut vo!ta"e )i!! a!! 'o)n to 0 V. +on6t s#ort t#e out%ut as t#is )ou!' resu!t in !ar"e current t#rou"# t#e series transistor )#ic# )i!! !ea' to burnin" o t#e same 'ue to over#eat.

iii.

iv. v.

*+. APPLICATIONS@ 1. !. ). /ow current applications. 1i@ed *oltage applications ;@tension of %ener regulator for higher currents.

*,. E)TENSIONS@ The main function of *oltage regulator is to regulate the changes in output *oltage for the changes occur either in input *oltage *ariations or output load *ariations. An this e@periment we ha*e *erified for one particular *alue of output *oltage. >e can obtain *oltage regulation at higher *oltages with the help of more number of 2ener diode operating in brea4 down region, must be connected in series. 1or e@ample, to obtain *oltage regulation at <.! *olts, we can use the same circuit with two 2ener diodes of *alues ).1 *olts and 0.1 *olts respecti*ely. 'y employing a series regulator with error amplifier , *ariable regulated *olatage can be obtained from circuit gi*en below.
T#e e*%eriment is con'ucte' is o sim%!est t&%e to 'emonstrate use o 5ener an' series %ass transistor )it#out an& unre"u!ate' vo!ta"e %o)er su%%!&. -n rea! a%%!ication re"u!ate' %o)er su%%!& use' at t#e in%ut o t#is e*%eriment )i!! be re%!ace' b& a u!! )ave or bri'"e recti ier )it# ca%acitor in%ut i!ter suitab!e to t#e !oa' an' re%u!e vo!ta"es e*%ecte'. T#e series transistor )ou!' be a %o)er transistor )it# #i"# current ca%acit& an' )ou!' be mounte' to #eat sink..i%%!e can be simu!ate' b& c#an"e in in%ut an' t#e corres%on'in" c#an"e in out%ut at a constant !oa' current. /ne can obtain 'i erent i*e' vo!ta"es b& suitab!& c#an"in" t#e 5ener 'io'e. /ne can obtain #i"#er current ratin"s b& em%!o&in" suitab!e series %o)er transistor an' #eat sinks.

*.. TROUBLE S%OOTIN>@ S.NO 1. !.. (AULT Af there is no output Af DC *oltages differ *ery much &IA>NOSIS Chec4 :cc and all DC *oltages. . Chec4 entire circuit for connections, resistance *alues and placements Chec4 Transistors.

*2. AUESTIONS@ i. ii. iii.. i*. *. *i. *ii. *iii. i@. @. Define *oltage regulator. Hi*e the ad*antages of series *oltage regulator. . ;@plain the feed bac4 mechanism in series *oltage regulator. An series *oltage regulator which is control element and e@plain its function. Define load and line regulation. >hat is ideal *alue K. >hich element determines output ripple K >hat determines ma@imum load current allowed in this circuit K #ention the applications of series *oltage regulator. Define no load *oltage and full load *oltage. ;@plain the term percentage regulation.

APPEN&I) ? I @ INTRO&UCTION TO INSTRUMENTS USE& *. T%E MULTIMETER STRUCTURE

(i!. * 1. LC& &isp"ay@ + ) . digit display (ma@imum reading 1TTT indicates measured *alues, and features symbols indicating ranges, /ow battery. !. (unction Se"ector@ To select +C:, DC:, +C+, DC+, Resistance, Diode, Continuity U Transistor test. ). Input ;ac1s :BD$ 'A$ A and COM<@ Test leads are inserted into these Qac4s for :oltage, Resistance, Current measurements, Continuity U Diode chec4s. -. Input Soc1et or Transistor Test@ &D& or D&D transistors are inserted in the soc4ets pro*ided to measure their ratings. (unctiona" Buttons@ 'elow table indicates the functional button operations

Buttons DO>;R (Gellow Cwitch

Operation Per or'ed Turn the #eter O& and O11

 Rotate the C>ATC$ to turn O& the #eter Rotate the C>ATC$ to O11 position to turn O11 the #eter &isp"ay Sy'0o"s@

(i!. + SYMBOL V
? E

MEANIN> Andicates negati*e reading The battery is low. >arning:

F
To a*oid false readings, which could lead to possible electric shoc4 or personal inQury, replace the battery as soon as the battery indicator appears. Andicates the range in which the switch position is placed.

+. (UNCTION >ENERATOR (RONT PANEL CONTROLS

1. Dower: Dush button switch for supplying power to instrument. !. Digital Display: (7-segment /;D : --digit freBuency 9 amplitude meter, /;D indicators for $%, P$%, m: U :. ). 1R;E9+#D: Celects display of freBuency or amplitude. -. +#D (adQusting 4nob : Continuous adQustment of the output amplitude from " 6 !" d' when terminated with 0"W. 0. 6!"d', -!"d' (Dush button : Two fi@ed attenuators, -!"d' each. They can be used separately. >hen both push buttons are acti*ated, a total attenuation of 6-" d' results. Ancluding the amplitude control for the ma@. attenuation amounts to 3" d' (factor 1""" . 3. Output ('&C connector : Chort-circuit-proof signal output of the generator. The output impedance is 0"W switch selectable. #a@ output amplitude is )" :pp (o.c. or 10 :pp when terminated with 0"W. (AttentionF Do not apply any DC *oltage to the output soc4et 7. 0" W 9 3"" W: Dush button when pressed selects 3"" W else 0"W in released position. <. DC (On , Offset (adQusting 4nob : +dQustment of the positi*e or negati*e offset *oltage. This DC *oltage can be superimposed on the output signal. The ma@ offset *oltage is X 1!.0 : (o.c. or X 3.!0 : respecti*ely when terminated with 0"W. This *oltage is also a*ailable in DC mode. T. 1unction: #ode selection DC- sine triangle 6 sBuare desired function selection indicated by glowing /;Ds. 1". O*er dri*e (/;Ds : >hen wor4ing in the offset mode, and the output amplifier is o*erdri*en either in positi*e or in negati*e direction, the corresponding /;D lit up. 11. 1:+R (adQusting 4nob : Continuous and linear freBuency adQustment from 1 $% to 1 #$% in steps, selected with freBuency range. 1!. 1reBuency: 1reBuency coarse adQustment from 1 $% to 1 #$% in 7 decade steps. Desired freBuency selection indicated by glowing /;Ds. 1). :+R: >hen trigger output is selected in C#OC output can be set with :+R, to appro@. 10 :pp.

1-. Trig output ('&C connector : This short-circuit-proof output supplies sBuare wa*es signal in synchronous with the output signal. At is switch selectable TT/9C#OC and has a duty-factor or appro@ 0"?. -@-

10. TT/9C#OC: Cwitch selects trigger output TT/ or C#OC. 13. 1# in ('&C connector : +pplying a DC *oltage to this input will *ary the oscillator freBuency linearly to ma@. 1:1"". The ma@imum allowable input *oltage is M)":. 17. +#D/ (adQusting 4nob : +ttenuation of input *oltage for 1#-input. This permits the user to change the sweep width. TEC%NICAL SPECI(ICATIONS Operatin! Modes@ Cine 6 CBuare 6 Triangle 6 DC, 1ree running or e@ternal freBuency modulated, with or without DC offset. (re9uency Ran!e@ ".1 $% 6 1 #$% in 7 decade steps *ariable control between steps. 4a/e or' Characteristics Sine -a/e distortion@ ".1 $% to 1"" P$% : ma@. ".0? 1"" P$% to 0"" P$% : ma@. 1.0? 0"" P$% to 1 #$% : ma@. )? S9uare -a/e rise ti'e@ #a@. 7"ns (1" to T"? O/ershoot@ Y0? (when output is terminated with 0" W Trian!"e Non?"inearity@ Y1? (upto 1"" 4$% appro@. &isp"ay@ Display switch able for freBuency and amplitude, with automatically positioned decimal point /;D indicator for $%, P$%, m: and :. (re9uency@ - digit 7 segment /;D up to 1"" P$% : X 1? X/CD up to 1 #$% : X )? X/CD A'p"itude@ ) digit 7 segment /;D

Accuracy@ ):pp-)":pp : X )? )""m:pp 6 ):pp : X 0? )"m:pp 6 )""m:pp : X 0? A'p"itude@ ) digit 7 Cegment /;D Accuracy@ ):pp 6 )":pp : X )? )""m:pp 6 ):pp : X 0? )"m:pp 6 )""m:pp : X 0? O/erdri/e@ Andicates with two /;Ds -@i-

Outputs@ Cignal output : short-circuit proof Ampedance : 0" W 9 3"" W switch able Output *oltage: ma@. 10 :pp into 0"W, )" :pp open circuit +ttenuation : ! steps: !"d' X ".!d' each. :ariable attenuation: " to !" d' total of 3"d' +mplitude 1latness: (sine9triangle with 0" W termination. ".1 $% to 1"" P$% ma@. ".! d' 1"" P$% to 1 #$% ma@. ".0 d' DC offset : Continuously *ariable (switch able Offset range : ma@. X 3.!0 : into 0"W #a@. X 1!.0 : open circuit Trigger output: Cwitch selectable TT/9C#OC TT/ more than -: C#OC le*el adQustable up to 1-: (appro@. (M input = EGterna" S-eep@ 1reBuency change : appro@. 1 : 1"" Anput Ampedance : 1""4W ZZ !0p1 Anput *oltage : ma@ X )" :pp >enera" In or'ation@ Cupply Dower Consumption Operating Conditions Dimensions (mm >eight : !!" : +C X 1"?, 0" $% : !" :+ (appro@. : "-0"[C, T0? R$ : >1T3 @ $<" @ D !3! : !.0 4g (appro@.

-@ii-

,. CAT%O&E RAY OSCILLOSCOPE TEC%NICAL SPECI(ICATIONS Operatin! 'odes@ Channel A, Channel AA, Channel A U AA alternate 9 chopped (appro@. 0"" P$% L 6 G (Ratio 1:1 input *ia C$ AA , +dd9Cub, An*ert C$ AA. :ertical deflection (y : (Adentical channels Band-idth@ DC-!" #$% (-) d' DC-!< #$% (-3d' Rise Ti'e@ 17.0 ns (appro@. &e "ection coe icients@ 1! calibrated steps !m:9cm 6 1":9cm (1-!-0 seBuence Accuracy@ X )? Input I'pedance@ 1 #W ZZ !0 p1. Input coup"in!@ DC-+C-H&D Input /o"ta!e@ #a@. -"": (DC M Dea4 +C . Ti'e 0ase@ Ti'e coe icients@ 1< calibrated steps. ".0 s9cm 6 ".!s9cm (1-!-0 seBuence with magnifier @ 0 to 1""ns9cm. >ith *ariable control to -" ns9cm. Accuracy@ X )? (in cal position Ra'p output@ 0 :pp (appro@. %o"d?O @ :ariable control for stable trigger. Tri!!er Syste'@ Modes@ automatic or *ariable trigger le*el Source@ Ch A, Ch AA, +/T Ch A 9 Ch AA, /ine, ;@t. S"ope@ Dositi*e or &egati*e Coup"in!@ +C Sensiti/ity@ Ant. 0mm, ;@t ".< : (appro@. Tri!!er Band-idth@ -" #$% %oriHonta" &e "ection :G<@ Band-idth@ DC 6 !.) #$% (-) d' . ) I Y 'ode@ Dhase shift \ )[ at 3" P$%. &e "ection coe icients@ 1! calibrated steps !m:9cm-1":9cm(1-!-0 seBuence Input I'pedance@ 1 # W ZZ !0 p1. Co'ponent Tester@ Test Bo"ta!e@ #a@ <.3 :rms (Open Test Current@ #a@ < m+ rms (Chorted Test (re9uency@ 0"$%, Test circuit grounded to chassis.

Continuity Tester@ 'eeper sounds \ 70W (appro@. >enera" In or'ation@ Cathode Ray Tu0e@ Rectangular medium short persistence (D-)1 Acce"eratin! potentia"@ !""" :DC (appro@. &isp"ay@ < @ 1" cm Trace rotation@ +dQustable on front panel Ca"i0rator@ CBuare wa*e generator 1P$% (appro@. . ".!: X1? for probe compensation. J Modu"ation@ TT/ le*el Sta0i"iHed Po-er Supp"y@ +ll operating *oltages including the ;$T Mains Bo"ta!e@ !!" :, 0"$% Mains "uctuations@ X1"? (ma@. Po-er Consu'ption@ )) :+ (appro@. 4ei!ht :approG<@ 7.0 4g. &i'ensions :''<@ >!<0 @ $1-0 @ D)<" Operatin! Te'perature@ "--"[, T0? R$ (inish@ Off white with handle and tilt stand. SPECI(ICATION (OR LO>IC SCOPE @ Lo!ic Inputs@ < &os. (TT/ timing diagrams Output@ To oscilloscope.

PANEL CONTROLS

1 ! ) 0 3 7 <

Po-er On=O )2 )Y C%?I=C%?II Tri! I=Tri! II Mono=&ua" ALT=C%OP=A&& Ti'e=&i/ AT=Nor'

T 1" 11

Le/e" Tri!. Input Ca" out

Dush buttons switch for supplying power to instrument. Cwitch when pushed inwards gi*es 0 times magnification of the L signal. Cwitch when pressed cuts off the time base U allows access the e@t. hori%ontal signal to be fed through C$ AA (used for L-G display Cwitch when out selects U triggers C$ A and when pressed, selects U triggers C$ AA. Cwitch selects the dual operation Cwitch selects alternate or chopped in DF+/ mode. Af mono is selected then this switch enables addition or subtraction of channel i.e. C$A X C$AA Cwitch selects time base speeds Cwitch selects +uto9&ormal position. +uto is used to get trace when no signal is fed at the input. An &OR# the trigger le*el can be *aried from the positi*e pea4 to negati*e pea4 with /;:;/ control Controls the trigger le*el from pea4 to pea4 amplitude of signal Coc4et pro*ided to feed e@ternal trigger signal in ;LT. mode Coc4et pro*ided for sBuare wa*e output !"" m :] used for probe compensation and chec4ing *ertical

1! 1) 1-

%o"d O )?POS EGt.

sensiti*ity, etc. Controls hold of time between sweeps. &ormal position I full ccw Controls $ori%ontal position of the trace Cwitch when pressed allows e@ternal triggering signal to be fed from the soc4et mar4ed TRAH. A&D.

-@*-

10

Baria0"e

Controls the time speed in between two steps of TA#;9DA: switch. 1or calibration put this fully anticloc4wise. (+t C+/ pos Cwitch when pressed displayed signal gets synchroni%ed with mains line freBuency Celects alternate trigger mode from C$ A U C$ AA Cwitch selects the slope of triggering, whether positi*e going or negati*e going Cwitch when pressed in*erts the C$ AA Controls the brightness of the trace Controls the alignment of the trace with gratitude (Ccrew dri*er adQustment Controls the sharpness of the trace Cwitch when pressed starts CT operation Anput coupling switch for each channel. An +C the signal is coupled through ".1 #1D capacitor. '&C connectors ser*e as input connection for C$ A U C$ AA Channel AA input connector also ser*es as $ori%ontal e@ternal signal. To test any components in the CT mode, put one test probe in this soc4et and connect the other test probe in ground soc4et. Cwitches select the sensiti*ity of each channel Controls pro*ided for *ertical deflection of trace for each channel. Terminals pro*ided for feeding logic le*els (Timing Diagram use 1 mm patch cords (bunch of < Connect output to C$ A or C$ AA of oscilloscope by using 1 mm patch cord )0" m+ fuse is pro*ided at the bac4 panel. Cpare fuses are pro*ided inside the instrument 'anana soc4et pro*ided for modulating signal input i.e. 2-modulation.

13 17 1< 1T !" !1 !! !) !!0 !3 !7 !<

Line A"t E=? In/ Ch. II Intensity TR (ocus CT &C=AC=>& Ch. I:Y< K Ch. II:)< CT?IN Bo"ts=&i/ Y POS I K II

LO>IC SCOPE !T Inputs )" Output

Bac1 Pane" Contro"s )1 (use )! J 'od

.. RE>ULATE& PO4ER SUPPLY

*. PO4ER@ Dush button switch for supplying power to instrument. +. OUTPUT ON@ Dush button for switching On 9 Off all the three output *oltages. , K 3 B='A :Push 0utton<@ 1or switching the display from *oltage to current reading or *ice *ersa. >hen pushbuttons are pressed, the current supplied from the terminals 1! U 17 is displayed with a resolution of 1m+. An released position *oltages across the terminals 1! U 17 are displayed with a resolution of ".1 :. . K 5 &I>ITAL &ISPLAYS :5?Se!'ent LE&<@ Dual display with two )-digit readout for output *oltage and current. On the left side of the instrument the *oltage and current readings for terminals ) is indicated. The corresponding *alues for the terminals - are indicated on the right side of the display. 2 K 6 B K 'A IN&ICATORS@ Two /;Ds indicate the unit of the display. The m+ /;D flashes when the " 6 )":DC output is used in constant current mode, or output current reBuired is in e@cess of specified *alue, in C: mode. 7 OUTPUT E 2 B : iGed< :.'' 0anana soc1ets<@ Output terminals for -mm banana plugs or cable connection for the fi@ed M0: output. The output *oltage is short circuit protected.

&C Output@ ! @ " 6 )":, 0"" m+ 1 @ 0: fi@ed, 1+ Output Bo"ta!e Ran!e@ "-)":, continuously *ariable by means of coarse and fine controls Reso"ution@ Y ".1? Interna" resistance@ Y 10mW (typical 7mW Sta0i"ity@ Y !.0m: (ma@.: ! @ !""m+ at line *oltage *ariations of up to 1"? Reco/ery ti'e@ Y <"s Load re!u"ation@ Y "."0? Te'perature coe icient@ Y ".1?9[C Ripp"e and noise@ Y 1m:rms Output current@ ma@. 0"" m+ Current "i'it@ 1"m+ to 0""m+ continuously adQustable Reso"ution@ Y1? E2B (iGed Output To"erance@ X ".!: Interna" resistance@ Y "."3W Sta0i"ity@ Y 0m: at line *oltage *ariations of up to 1"? Reco/ery ti'e@ Y 1"" s Te'perature coe icient@ Y ".1?9[C Ripp"e and noise@ Y 0m:rms Output current@ ma@. 1+ &isp"ay ! @ )-digit 7-segment /;D display for :oltage U Current. Two /;D (for : and m+ indicate the unit of display.

>enera" In or'ation +ll outputs are floating. Outputs are switch able from front panel. 'uilt-in o*erheat protection. Supp"y@ !)" : +C X 1"?, 0" $% Operatin! Conditions@ "--"[C, T0? R$ &i'ension :''<@ > 1T3, $<", D!3! 4ei!ht@ ).T Pgs

APPEN&I) II >ENERAL PRECAUTIONS IN ASSEMBLIN> CIRCUITS @ i. ii. iii. i*. 1"" percent 4nowledge about color code of Resistors is reBuired. 1ull 4nowledge about bread board and contact information is reBuired. 1"" percent 4nowledge about transistor lead connections i.e. base , emitter and collector connections. 1"" percent 4nowledge about diode and %ener lead connections i.e. anode and cathode connections. Dolarity mar4ing of the electrolytic capacitors must be obser*ed , while connecting. At will be a good practice to test diodes and transistors with D## before using . Test connecting leads and probes before using. +fter completing assembly 6 before connecting RDC , ensure that supply and ground leads of the circuit are not shorted . This can be *erified by multi meter .

*. *i. *ii. *iii.

APPEN&I) III @ >ENERAL PRECAUTIONS IN USIN> INSTRUMENTS @ Re!u"ated Po-er supp"y @ i. ii. iii. 'efore connecting RDC , ensure that supply and ground leads of the circuit are not shorted . This can be *erified by multi meter . Cet *oltage controls to %ero reading , before connecting to the circuit. Cet current setting to mid or less than the mid position.

CRO @ i. Obtain trace on channel and set position control to get the trace to the middle . ii. Cee to which channel you are applying input . iii. Touch the probe with hand to 4now whether it is responding. This will detect bro4en probes , wrong setting of channels . Cet *olts9di* and time9di* as reBuired. +C and DC coupling of input , positi*e 9 negati*e le*el settings must be understood. Henerally CRO must in +FTO mode of sweep. /earn how to trigger the CRO and set controls to get stable trace and full control with le*el and slope . One should also 4now component tester mode of CRO.

i*. *.

*i. *ii.

*iii.

(UNCTION >ENERATOR @ i. ii. Cet the output controls to minimum before connecting to circuit. Celect sine 9 sBuare 9 triangular wa*eform with desired freBuency .

iii.

One should 4now attenuator , DC offset settings and output terminals properly.

MOBIN> COIL AMMETERS AN& BOLTMETERS @ i. ii. polarity of connections to abo*e must be perfectly correct, otherwise meters will be damaged due to wrong connections. The proper ( 1ull Ccale reading rated meters must be used , otherwise meters will be damaged by o*er currents 9 *oltages.

&I>ITAL MULTIMETERS @ i. ii. iii. i*. 'efore connecting and switching on , set to proper function i.e. :-+-R ac or dc and range . +pplying *oltages in resistance mode will damage D##^s. Turning 4nobs with *oltages 9 currents O& will damage D##^s. C;T T$; R+&H; +&D +DD/G :O/T+H; OR CFRR;&T.

APPEN&I) I IB @

Speci ications o BC *85@ Collector 6base *oltage (open emitter , :C'O ma@ I 3": Collector 6 emitter *oltage (open base , :C;O ma@. I -0: ;mitter base *oltage (open collector Collector current (d.c. Total Dower dissipation , #a@. _unction temperature at !0 oC 1orward Current Hain Speci ications o SL*88 @ Collector 6base *oltage (open emitter Collector 6 emitter *oltage (open base ;mitter base *oltage (open collector Collector current (d.c. , Total Dower dissipation, #a@. _unction temperature at !0 oC 1orward Current Hain :C'O ma@ I 3": :C;O ma@. I -0: :;'O ma@ I 0 : AC ma@ I 1+ !> 10" oC !" :;'O ma@ I AC ma@ 0:

I !""m+

Dtot ma@ I !0" m> I I 10" oC 10"

Dtot ma@ I I I

SPECI(ICATIONS O( JENER &IO&E IN2+2, @ >or4ing 2ener *oltage range, #a@imum power consumption at room temp. #a@imum _unction temp. :% I D ma@ I T ma@ I -.7 to )) *olts )""m> 10""C

APPEN&I) IB @

SPICE PRO>RAMS O( ECA LAB E)PERIMENTS @ *. T4O STA>E RC COUPLE& CE AMPLI(IER @ `` two stage RC coupled amplifier *cc - " dc 1!* *in 1 " ac 0"m* rb1 1 ! -.74 cb1 ! ) 1"u r11 ) - 3!4 r1! ) " -.74 rc1 - 0 ))4 re1 3 " 03" ce1 3 " 1"u B1 0 ) 3 bc1"7 .model bc1"7 npn (bfI1"" cc1 0 7 ".1u rb! 7 < 14 r!1 < - 3!4 r!! < " -.74 rc! T - ))4 re! 1" " 03" ce! 1" " 1"u cc! T 11 1"u B! T < 1" bc1"7a .model bc1"7a npn (bfI1"" rl 11 " 14 csh 11 " 0n .ac dec 1" 0"h% 1""4h% .print ac *(11 .plot ac :(11 .probe .end

*.B. ALTERNATE T4O STA>E RC COUPLE& AMPLI(IER ``alternate circuit for two stage RC coupled C; amplifier *in " 1! ac 1"m* sin(" 1"m* 104h% rb 1! 1 1"4 cb1 1 ! 1"u *cc 0 " dc 1!* r11 ! 0 -74 r1! ! " 1"4 rc1 ) 0 !.!4 re1 - " 14 ce1 - " 1""u B1 ) ! - bc1"7 .model bc1"7 npn (bfI1"" cc1 ) 3 1"u rb! 3 " 1"4 cb! 7 < 1"u rb1 3 7 1"4 r!1 < 0 -74 r!! < " 1"4 rc! T 0 !.!4 re! 1" " 14 ce! 1" " 1""u B! T < 1" bc1"7a .model bc1"7a npn (bfI1"" cc) T 11 1"u rl 11 " !.!4 csh 11 " !n .ac dec 1" 1"h% 1""4h% .print ac *(11 .plot ac :(11 .probe .end

+. SIMPLE SERIES BOLTA>E RE>ULATOR @ ``C;RA;C :O/T+H; R;HF/+TOR *in 1 " dc !"* r1 1 ! 03" r! ! ) 14 B1 ! ) - sl1"" .model sl1"" npn ( bfI!" d1 " ) dname .model dname d(b*I0.1* rl - " 14 .dc *in " )"* 1* .plot dc *(- *(1 .print dc *(- *(1 .probe .end

,.S%UNT BOLTA>E RE>ULATOR @ ``C$F&T :O/T+H; R;HF/+TOR :A& 1 " !": R1 1 ! 03" E1 ! - ) C/1""+ .#OD;/ C/1""+ &D& ('1I!" E! ! ) " C/1""' .#OD;/ C/1""' &D& ('1I!" D1 - ! D&+#; .#OD;/ D&+#; D(':I3.<: R! - " 1P R/ ! " 1P .dc *in " )"* 1* .plot dc *(! *(1 .print dc *(! *(1 .probe .end

,A . SIMPLE S%UNT BOLTA>E RE>ULATOR ``simple shunt *oltage regulator *in 1 " !"* r1 1 ! 1<" d1 ) ! dname .model dname d(b*I3.<* B1 ! ) " sl1"" .model sl1"" npn (bfI!" r! ) " 14 rl ! " !4 .dc *in " )"* 1* .plot dc *(! *(1 .print dc *(! *(1 .probe .end

.. SERIES (E& CLASS I A PO4ER AMPLI(IER @ ``series fed class-+ power amplifier *cc ) " dc 0* *in 1 " sin(" 1"m* 14h% rb ) ! !"4 c1 1 ! ".1u rc ) - 14 B1 - ! " sl1"" .model sl1"" npn (bfI!" c! - 0 ".1u rl 0 " 14 .tran 1"us 1"ms 1"us .print dc i(rc .probe .end

2. COMPLIMENTARY I SYMMETRY CLASS I B PO4ER AMPLI(IER @ `` complimentary symmetry class-' power amplifier *in 1 " sin(" !* 14h% B1 ) ! - sl1"" .model sl1"" npn (bfI!" B! 0 ! - s41"" .model s41"" pnp (bfI!" c1 1 ! 1u rl - " < *cc ) " 0* *ee " 0 0* .tran 1"us !ms 1"us .probe .end 3. ALTERNATE CIRCUIT (OR CLASS?B COMPLIMENTARY SYMMETRY PO4ER AMPLI(IER ``alternate circuit for class-' com-sym power amplifier *in 1 " sin(" !* 1"4h% r1 1 ! 14 c1 ! ) ".1u c! ! - ".1u r! ) 0 !!"4 r) ) " 1<4 r- - " 1<4 r0 - T !!"4 *ee " T dc 1!* *cc 0 " dc 1!* B1 0 ) 3 sl1"" .model sl1"" npn (bfI!" B! T - < s41"" .model s41"" pnp (bfI!" r3 3 7 -.) r7 < 7 -.) rl 7 " 14 .tran 1"us !ms 1"us .probe .end

5. CLASS I C TUNE& PO4ER AMPLI(IER @ ``class - C tuned power amplifier *in 1 " ac !* sin(" !* 10.T4h% *cc - " dc 0* c1 1 ! ".1u r1 ! " -.74 B1 ) ! " sl1"" .model sl1"" npn (bfI!" l1 - ) 1"mh c! - ) 1"n rl ) " 1"4 .ac dec 1"" 14h% 1""4h% .tran 1"us !ms 1"us .probe .end 6. BARIABLE SERIES BOLTA>E RE>ULATOR @ `` *ariable series *oltage regulator *in 1 " dc !"* r1 1 ! -.74 r! 1 - 1.<4 r) ) 0 1"4 r- 0 " 1"4 rl ) " !4 B1 1 ! ) sl1""a .model sl1""a npn (bfI!" B! ! 0 - sl1""b .model sl1""b npn (bfI!" d1 " - dname .model dname d(b*I0.1* .dc *in " )"* 1* .print dc *(1 *() .plot dc *(1 *() .probe .end