ECE 341 Lecture # 6

Instructor: Zeshan Chishti zeshan@ece.pdx.edu

Lecture Topics
Multiplication of Unsigned Numbers
Sequential Circuit Multiplier

Multiplication of Signed Numbers

Booth Algorithm

Fast Multiplication
Bit-pair Recording of Multipliers Carry-Save Addition of Summands CSA Tree using 3-2 Reducers

April 19, 2012 Portland State University

Reference:
Chapter 9: Sections 9.3.2, 9.4, 9.5.1, 9.5.2 and 9.5.3

Recap of Array Multipliers

Array multipliers are highly inefficient:
Need n n-bit adders => number of gate counts is proportional to Impractical for large numbers such as 32-bit or 64-bit numbers typically used in computers Perform only one function, namely, unsigned integer product n2

Sequential Multiplication
Recall the rule for generating partial products:
If the ith bit of the multiplier is 1, add the appropriately shifted multiplicand to the current partial product. Multiplicand is shifted left when being added to the partial product

Solution: Improve gate efficiency by using a mixture of combinatorial array techniques and sequential techniques
Instead of n n-bit adders, use one n-bit adder Use a register to hold the accumulated partial product This is called a sequential multiplier

Key Observation: Adding a left-shifted multiplicand to an unshifted partial product is equivalent to adding an unshifted multiplicand to a right-shifted partial product

Sequential Circuit Multiplier

Register A (initially 0) Shift right
C a
n - 1

Sequential Multiplication Algorithm

Initialization:
Load multiplicand in M register, multiplier in Q register Initialize C and A registers to all zeroes

q
n - 1

q
0

Multiplier Q Add/Noadd control

Repeat the following steps n times, where n is the number of bits in the multiplier
If (LSB of Q register == 1)
A = A + M (carry-out goes to C register)

n-bit Adder
MUX

Control sequencer
0

Treat the C, A and Q registers as one contiguous register and shift that registers contents right by one bit position

0 m
n - 1

After the completion of n steps

m
0

Multiplicand M

Register A contains high-order half of product Register Q contains low-order half of product

Sequential Multiplication Example

M 1 1 0 1 Initial configuration 0 C 0 0 0 0 A 1 0 1 1 Q

Sequential Multiplication Example

M 1 1 0 1 Initial configuration 0 C 0 0 0 0 0 0 A 1 1 0 1 0 1 1 0 1 0 1 1 Q 1 0 1 1 1 1 0 1 A += M Shift First cycle

Sequential Multiplication Example

M 1 1 0 1 Initial configuration 0 C 0 0 1 0 0 0 0 0 A 1 1 0 1 0 1 1 0 0 0 1 1 1 0 0 1 1 0 1 1 Q 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 0 A += M Shift A += M Shift First cycle

Sequential Multiplication Example

M 1 1 0 1 Initial configuration 0 C 0 0 1 0 0 0 0 0 0 0 A 1 1 0 1 0 1 1 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 1 Q 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 A += M Shift A += M Shift No add Shift First cycle

Second cycle

Second cycle

Third cycle

Sequential Multiplication Example

M 1 1 0 1 Initial configuration 0 C 0 0 1 0 0 0 1 0 0 0 0 0 A 1 1 0 1 0 1 1 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 1 Q 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 A += M Shift A += M Shift No add Shift A += M Shift First cycle

Signed Multiplication

Second cycle

Third cycle

Fourth cycle

Product

Signed Multiplication
Considering 2s-complement signed operands, what will happen to (-13)(+11) if following the same method of unsigned multiplication?
1 0 1 1 1 0 1 0 1 1 1 0 1 0 0 1 1 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 0 1 ( - 143) 0 1 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 1 ( - 13) ( + 11)

Signed Multiplication (cont.)

If the multiplier is +ve:
The unsigned multiplication hardware works fine as long as it is augmented to provide for sign extension of partial products

If the multiplier is ve:

Form the 2s-complement of both the multiplier and the multiplicand and proceed as in the case of a +ve multiplier This is possible because complementation of both operands does not change the value or the sign of the product

Sign extension is shown in blue

1 0 1 0 1

A technique that works equally well for both negative and positive multipliers Booth algorithm

We must extend sign-bit value of multiplicand to left as far as product will extend

Booth Algorithm
Booth algorithm treats both positive and negative 2s complement operands uniformly To understand Booth algorithm:
Consider a multiplication scenario, where the multiplier has a single block of 1s, for example, 0011110. How many appropriately shifted versions of the multiplicand are typically added to derive the product?
0 0 0 0 1 0 1 1 0 0 1 0 1 1 0 1 0 +1 +1 + 1 +1 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 1 1 0 1 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0

Booth Algorithm (cont.)

Since 0011110 = 0100000 0000010, if we use the expression to the right, what will happen?
0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0

0 +1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1

0 -1 0 1 0 0 1

2's complement of the multiplicand

We need as many additions as the number of 1s

0 0 0

0 0 1 0 0 0 0 0 0 0 1 0

0 1 0 0 0

0 1 0 1 0 0

We need only 2 additions

0 0 1 1 0

1 0 1 0

Booth Algorithm (cont.)

In general, in the Booth scheme, -1 times the shifted multiplicand is selected when moving from 0 to 1, and +1 times the shifted multiplicand is selected when moving from 1 to 0, as the multiplier is scanned from right to left
0 0 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 0

Booth Algorithm Example for Negative Multiplier

0 1 1 0 1 X1 1 0 1 0 ( + 13) (- 6 ) 0 1 1 0 1 0 - 1 +1 - 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 1

0 +1 - 1 + 1 0 - 1 0 +1 0 0 - 1 +1 - 1 + 1 0 - 1 0 0

Works fine as long as we do appropriate sign extension for the negative summands (versions of the multiplicand)

1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 0 ( - 78)

Booth recoding of a multiplier

Booth Multiplier Recording Table

Multiplier Bit i 0 0 1 1 Bit i -1 0 1 0 1 Version of multiplicand selected by bit 0 XM +1 XM 1 XM 0 XM

Booth Algorithm Efficiency

Worst case: 0s and 1s are alternating => n summands Best case: a few long strings of 1s (skipping over 1s) => small no. of summands
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Worst-case multiplier + 1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1

1 1 0 0 0 1 0 1 1 0 1 1 1 1 0 0 Ordinary multiplier 0 -1 0 0 +1 -1 +1 0 -1 +1 0 0 0 -1 0 0

0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 Good multiplier 0 0 0 +1 0 0 0 0 -1 0 0 0 +1 0 0 -1

Bit-Pair Recoding of Multipliers

For each pair of bits in the multiplier, we require at most one summand to be added to the partial product For n-bit operands, it is guaranteed that the max. number of summands to be added is n/2

Fast Multiplication

Sign extension 1 1 1 0 1 0 0

Implied 0 to right of LSB

0 1 +1 1

Booth Recording Bit-pair Recording

Example of bit-pair recoding derived from Booth recoding

Bit-Pair Recoding of Multipliers (cont.)

Multiplier bit-pair i +1 0 0 0 0 1 1 1 1 i 0 0 1 1 0 0 1 1 Multiplier bit on the right i 1 0 1 0 1 0 1 0 1 Multiplicand selected at position i 0 X M +1 X M +1 X M +2 X M 2 X M 1 X M 1 X M 0 X M
0 1 1 0 1 (+13) 1 1 0 1 0 (- 6)

Example
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 1 0 0 1 0 1 1 0 1 -1 0 -1 + 0 0 0 0 0 0 1 1 1 0 1 1 1 0 1 0 0 1 1 0 0

Booth Recording results in 3 summands

0 (- 78)

Bit-Pair Recording results in 2 summands

Table of multiplicand selection decisions

1 1 0 1

1 1 0 1

1 1 0 1

1 1 0 0

1 0 0 1

0 0 0 0 0 1

1 1 0 1 -1 - 2 0 1 1 0 1 1 0 0 1 0

Carry-Save Addition of Summands

Consider the 4-bit array multiplier shown in figure Since carries ripple along each row of the array, this is called a ripplecarry array

Carry-Save Addition of Summands (cont.)

Carry-save Adder (CSA) saves carries and introduces them into the next row, at the correct weighted positions
Avoids the rippling of carries within rows (except for the last row)

Less delay than a ripple-carry array

CSA Tree using 3-2 Reducers

Consider the addition of many summands. We can:
Group the summands in threes and perform carry-save addition on each of these groups in parallel to generate a set of S and C vectors in one full-adder delay Group all of the S and C vectors into threes, and perform carry-save addition on them, generating a further set of S and C vectors in one more full-adder delay Continue with this process until there are only two vectors remaining

CSA Tree with 3-2 Reduction Example

1 X 1 0 1 0 1 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 1 0 1 1 1 1 (45) (63) A B C D E F 1 0 0 1 1 (2,835) Product M Q

Summands grouped in threes

1 1 1 0 1 1 0 1 1 0

1 1 0 1 1 0 0 0 1 1 0 1 0

The final two vectors can be added in a CLA to produce the desired product

1 1 0

0 1

The adder at each bit position of the three summands is called a 3-2 reducer The tree structure that reducers the no. of summands to 2 is called a CSA tree

1 x 1

0 1 0 1 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1

1 1 1 1 0 0 1 1

1 1 1 0 1 0 0

0 1 0 1 1 0

1 1 1

M Q A B C S 1 C 1 D E F S 2 C 2 S1 C 1 S2 S 3 C3 C2 S4 C 4

1 x 1 1 0 1 0 1 1

0 1 0 1 1 0 1 0

1 1 1 1 0 0 1 1

1 1 1 0 1 0 0

0 1 0 1 1 0

1 1 1

M Q A B C S 1 C 1 D E F S 2 C 2 S1 C 1 S2 S 3 C3 C2 S4 C 4

Two CSAs done in parallel Outputs: S1, C1, S2 and C2

1 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 1 1 1 0 0

0 1 0 1 0 1

1 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 1 0

1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0

S1, C1 and C2 grouped into three and added by a CSA

0 1

1 1 0 0

1 0 1 1 1

1 0 1 0

Outputs: S3 1 0 1 1 0 1 and C3 1 0 1 1 0 1
0 1 0 1 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1

0 0 0 + 0 1

1 1 0 0 1 1 0

1 1 0 1 0 0 1

0 0 0 0 1 1 1 1

0 1 1 0 0 0 0 0

0 0 0 0 0 0 0

1 0 1 0 1 0 1

1 1 Product

0 0 0 + 0 1

1 1 0 0 1 1 0

1 1 0 1 0 0 1

0 0 0 0 1 1 1 1

0 1 1 0 0 0 0 0

0 0 0 0 0 0 0

1 0 1 0 1 0 1

1 1 Product

1 x 1 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0

0 1 0 1 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1

1 1 1 1 0 0 1 1

1 1 1 0 1 0 0

0 1 0 1 1 0

1 1 1

M Q A B C S 1 C 1 D E F S 2 C 2 S1 C 1 S2 S 3 C3 C2 S4 C 4

1 x 1 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0

0 1 0 1 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1

1 1 1 1 0 0 1 1

1 1 1 0 1 0 0

0 1 0 1 1 0

1 1 1

M Q A B C S 1 C 1 D E F S 2 C 2 S1 C 1 S2 S 3 C3 C2 S4 C 4

S3, C3 and C2 grouped into three and added by a CSA Outputs: S4 1 and C4 1 0
0 1 0 1 1

0 1 0 1 0 1

1 1 0 0 1 1 0 1 1 0 0 1 1 1 1 0 0

1 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 1 0

S4 and C4 added by a CLA Outputs: Final Product

1 0 1 0 1 0 1 1 0 1 0 1 0 1

1 1 0 0 1 1 0 1 1 0 0 1 1 1 1 0 0

1 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 1 0

0 0 0 + 0 1

1 1 0 0 1 1 0

1 1 0 1 0 0 1

0 0 0 0 1 1 1 1

0 1 1 0 0 0 0 0

0 0 0 0 0 0 0

1 0 1 0 1 0 1

1 1 Product

0 0 0 + 0 1

1 1 0 0 1 1 0

1 1 0 1 0 0 1

0 0 0 0 1 1 1 1

0 1 1 0 0 0 0 0

0 0 0 0 0 0 0

1 0 1 0 1 0 1

1 1 Product

Sequential Multiplication Example

M 1 0 1 1 Initial configuration 0 C 0 0 0 0 1 0 0 0 0 0 0 0 A 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 Q 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 No add Shift A += M Shift A += M Shift No add Shift First cycle

Booth Algorithm Example for Negative Multiplier

1 1 0 0 1 1 X 0 1 1 1 0 0 (-13) (+28) 1 1 0 0 1 1 +1 0 0 -1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Second cycle

0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0

Third cycle

0 0 0 0 0 0 0 0
Fourth cycle

1 1 1 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 ( - 364)

Product